TI MSP50C33N Mixed-signal processor Datasheet

MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
D
D
D
D
D
D
D
D
D
D
Dual Programmable LPC-12 Speech
Synthesizers
Simultaneous LPC and PCM Waveforms
8-Bit Microprocessor with 61 instructions
32 Twelve-Bit Words and 224 Bytes of RAM
3.3V to 6.5V CMOS Technology for Low
Power Dissipation
Direct Speaker Drive Capability
Mask Selectable Internal or External Clock
Internal Clock Generator that Requires No
External Components
Two Software-Selectable Clock Speeds
10-kHz or 8-kHz Speech Sample Rate
N PACKAGE
(TOP VIEW)
PA7
PB0
14 PA0
13 DAC +
12 DAC –
PA6
PA5
PA4
PA3
PA2
1
16
2
15
PA1
PB1/OSC OUT
OSC IN
6
11
7
10
3
4
5
8
VDD
VSS
9 INIT
description
The MSP50x3x family uses a revolutionary architecture to combine an 8-bit microprocessor, two speech
synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic
logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling
the microprocessor to do a multiply operation in 0.8 µs. The MSP50x3x family features two independent
channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code
modulation (PCM) can produce music or sound effects. LPC and PCM can be added together to produce a
composite result. For more information, see the MSP50x3x User’s Guide (literature number SPSU006).
Table 1. MSP50x3x Family
DEVICE
AMOUNT OF ROM/PROM
FEATURES
MSP50C32
16K bytes mask ROM
9/10 I/O lines
MSP50C33
32K bytes mask ROM
9/10 I/O lines
MSP50C34
64K bytes mask ROM
9/10 I/O lines, 24 I/O lines in die form
MSP50P34
64K bytes PROM
9/10 I/O lines
MSP50C37
16K bytes mask ROM
18 I/O lines, A/D converter/analog amplifier
MSP50P37
16K bytes PROM
18 I/O lines, A/D converter/analog amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 8 V
Supply current, IDD or ISS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground.
2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the
device.
recommended operating conditions (MSP50C32, MSP50C33, MSP50x34)
VDD
VIH
VIL
Supply voltage†
High-level input voltage
Low-level input voltage
MAX
MAX
3.3
6.5
VDD = 3.3 V
VDD = 5 V
2.5
3.3
3.8
5
VDD = 6 V
VDD = 3.3 V
4.5
6
0
0.65
TA
Operating free-air temperature
VDD = 5 V
VDD = 6 V
Device functionality
Rspeaker
Minimum speaker impedance
Direct speaker drive using 2 pin push-pull DAC option
0
1
0
1.3
0
70
UNIT
V
V
V
°C
Ω
32
† Unless otherwise noted, all voltages are with respect to VSS.
recommended operating conditions (MSP50x37)
VDD
VIH
VIL
TA
Rspeaker
4
Supply voltage†
VDD = 4 V
VDD = 5 V
High-level input voltage
Low-level input voltage
MAX
4
6.5
3
4
UNIT
V
V
3.8
5
VDD = 6 V
VDD = 4 V
4.5
6
0
1
VDD = 5 V
VDD = 6 V
0
1.2
0
1.5
0
6.5
V
–10
70
°C
MUX input voltage
Reference voltage = 6.5 V
Operating free-air temperature
Device functionality
Minimum speaker impedance
Direct speaker drive using power amp
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V
Ω
MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
MSP50C32, MSP50C33, MSP50x34 electrical characteristics over recommended ranges of supply
voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VT
T+
Positive going threshold voltage (INIT)
Positive-going
VDD = 3.5 V
VDD = 6 V
VT
T–
Negative going threshold voltage (INIT)
Negative-going
VDD = 3.5 V
VDD = 6 V
1.6
Vh
hys
Hysteresis ( VT
T ) (INIT)
T+ – VT–
VDD = 3.5 V
VDD = 6 V
0.4
IIkg
Input leakage current (except for OSC IN)
Istandby
Standby current (INIT low, SETOFF)
IDD†
IOH
IOL
IOH
IOL
Supply current
High level output current (PA,
High-level
(PA PB)
Low level output current (PA,
Low-level
(PA PB)
High level output current (D/A)
High-level
Low level output current (D/A)
Low-level
Pullup resistance
MAX
2
V
3.4
V
2.3
V
1.1
VDD = 3.3 V,
VDD = 5 V,
VOH = 2.75 V
VOH = 4.5 V
VDD = 6 V,
VDD = 3.3 V,
VOH = 5.5 V
VOH = 2.75 V
VDD = 5 V,
VDD = 6 V,
2
µA
10
µA
2.1
mA
3.1
4.5
–4
–12
VOH = 4.5 V
VOH = 5.5 V
–5
–14
–6
– 15
VDD = 3.3 V,
VDD = 5 V,
VOH = 2.2 V
VOH = 3.33 V
–8
–20
–14
– 40
VDD = 6 V,
VDD = 3.3 V,
VOH = 4 V
VOL = 0.5 V
– 20
– 51
5
9
VDD = 5 V,
VDD = 6 V,
VOL = 0.5 V
VOL = 0.5 V
5
9
5
9
VDD = 3.3 V,
VDD = 5 V,
VOL = 1.1 V
VOL = 1.67 V
10
19
20
29
VDD = 6 V,
VDD = 3.3 V,
VOL = 2 V
VOH = 2.75 V
25
35
– 30
–50
VDD = 5 V,
VDD = 6 V,
VOH = 4.5 V
VOH = 5.5 V
–35
–60
–40
– 65
VDD = 3.3 V,
VDD = 5 V,
VOH = 2.3 V
VOH = 4 V
– 50
–90
–90
– 140
VDD = 6 V,
VDD = 3.3 V,
VOH = 5 V
VOL = 0.5 V
– 100
– 150
50
80
VDD = 5 V,
VDD = 6 V,
VOL = 0.5 V
VOL = 0.5 V
70
90
80
110
VDD = 3.3 V,
VDD = 5 V,
VOL = 1 V
VOL = 1 V
100
140
VDD = 6 V,
VOL = 1 V
Resistors selected by software and
connected between terminal and VDD
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
140
150
10
20
50
kΩ
fosc(low)
(l )
Oscillator frequency
freq enc ‡
VDD = 5 V,
TA = 25°C,
Target frequency = 15.36 MHz
14 89
14.89
15 36
15.36
15 86
15.86
MHz
fosc(high)
(hi h)
Oscillator frequency
freq enc ‡
VDD = 5 V,
TA = 25°C,
Target frequency = 19.2 MHz
18 62
18.62
19 2
19.2
19 7
19.7
MHz
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
‡ The frequency of the internal clock has a temperature coefficient of approximately – 0.2 % / °C and a VDD coefficient of approximately ±1%/V.
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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
MSP50x37 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT
T+
Positive going threshold voltage (INIT)
Positive-going
VDD = 4.5 V
VDD = 6 V
VT
T–
Negative going threshold voltage (INIT)
Negative-going
VDD = 4.5 V
VDD = 6 V
Vh
hys
Hysteresis ( VT
T+ – VT
T– ) (INIT)
VDD = 4.5 V
VDD = 6 V
IIkg
Input leakage current (except for OSC IN)
Istandby
Standby current (INIT low, SETOFF)
IDD†
IOH
IOL
IOL
Supply current
High level output current (PA,
High-level
(PA PB,
PB PD)
Low level output current (PA4 – PA7)
Low-level
Low level output current (PA0 – PA3,
Low-level
PA3 PB,
PB PD))
MIN
TYP
MAX
2.7
V
3.65
2.3
V
3.15
0.4
V
0.5
1
25
Power amplifier is off
10
VDD = 4 V,
VDD = 5 V,
VOH = 3.5 V
VOH = 4.5 V
–4
–6
–5
–7.5
VDD = 6 V,
VDD = 4 V,
VOH = 5.5 V
VOH = 2.65 V
–6
– 9.2
VDD = 5 V,
VDD = 6 V,
VOH = 3.33 V
VOH = 4 V
VDD = 4 V,
VDD = 5 V,
VOL = 0.5 V
VOL = 0.5 V
VDD = 6 V,
VDD = 4 V,
µA
µA
10
Power amplifier is on
UNIT
mA
mA
–8
–13
–14
– 20
– 20
– 29
20
28
26
34
VOL = 0.5 V
VOL = 1.33 V
30
39
40
54
VDD = 5 V,
VDD = 6 V,
VOL = 1.67 V
VOL = 2 V
60
74
82
103
VDD = 4 V,
VDD = 5 V,
VOL = 0.5 V
VOL = 0.5 V
10
17
13
20
VDD = 6 V,
VDD = 4 V,
VOL = 0.5 V
VOL = 1.33 V
15
25
20
32
VDD = 5 V,
VDD = 6 V,
VOL = 1.67 V
VOL = 2 V
30
52
41
71
15
30
60
mA
mA
mA
mA
mA
Pullup resistance
Resistors selected by software and
connected between terminal and VDD
fosc(low)
(l )
freq enc ‡
Oscillator frequency
VDD = 5 V,
TA = 25°C,
Target frequency = 15.36 MHz
14 89
14.89
15 36
15.36
15 82
15.82
MHz
fosc(high)
(hi h)
Oscillator frequency
freq enc ‡
VDD = 5 V,
TA = 25°C,
Target frequency = 19.2 MHz
18 62
18.62
19 2
19.2
19 77
19.77
MHz
kΩ
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
‡ The frequency of the internal clock has a temperature coefficient of approximately – 0.2 % / °C and a VDD coefficient of approximately ±1.4%/V.
6
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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
MSP50x37 Power Amplifier Electrical Characteristics Over Recommended Operating
Free-Air Temperature Range
PARAMETER
TEST CONDITIONS
Differential output power
VDD = 5 V,
MIN
TYP
RL = 8 Ω
f = 1 kHz,
MAX
500
UNIT
mW
Bandwidth
3.5
kHz
MSP50x37 ADC Electrical Characteristics, VCC = 5 V, TA = 25°C
PARAMETER
MIN
TYP
MAX
UNIT
Linearity
± 0.5
LSB
Offset
± 1.5
LSB
Full scale error
± 1.5
Conversion time
LSB
40
Instructions
switching characteristics (MSP50C32, MSP50C33, MSP50x34)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tr
Rise time, PA, PB, D/A
VDD = 3.3 V,
CL = 100 pF,
10% to 90%
50
ns
tf
Fall time, PA, PB, D/A
VDD = 3.3 V,
CL = 100 pF,
10% to 90%
50
ns
switching characteristics (MSP50x37)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tr
Rise time, PA, PB, PD
VDD = 4 V,
CL = 100 pF,
10% to 90%
22
ns
tf
Fall time, PA, PB, PD
VDD = 4 V,
CL = 100 pF,
10% to 90%
10
ns
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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
timing requirements
MIN
MAX
UNIT
Initialization
tINIT
INIT pulsed low while the MSP50x3x has power applied (see Figure 1)
1
µs
Setup time prior to wakeup terminal negative transition (see Figure 2)
1
µs
Wakeup
tsu(wakeup)
External Interrupt
tsu(interrupt)
(i t
t)
Setup time prior to B1 terminal negative transition (see Figure 3)
fclock = 15.36 MHz
fclock = 19.2 MHz
1
µs
1.5
Writing (Slave Mode)
tsu1(B1)
tsu(d)
Setup time, B1 low before B0 goes low (see Figure 4)
th1(B1)
th(d)
Hold time, B1 low after B0 goes high (see Figure 4)
tw
tr
Pulse duration, B0 low (see Figure 4)
Rise time, B0 (see Figure 4)
50
ns
tf
Fall time, B0 (see Figure 4)
50
ns
Setup time, data valid before B0 goes high (see Figure 4)
Hold time, data valid after B0 goes high (see Figure 4)
20
ns
100
ns
20
ns
30
ns
100
ns
Reading (Slave Mode)
tsu2(B1)
th2(B1)
Setup time, B1 before B0 goes low (see Figure 5)
20
ns
Hold time, B1 after B0 goes high (see Figure 5)
20
ns
tdis
tw
Output disable time, data valid after B0 goes high (see Figure 5)
tr
tf
Rise time, B0 (see Figure 5)
50
ns
Fall time, B0 (see Figure 5)
50
ns
td
Delay time for B0 low to data valid (see Figure 5)
50
ns
Pulse duration, B0 low (see Figure 5)
PARAMETER MEASUREMENT INFORMATION
INIT
tINIT
Figure 1. Initialization Timing Diagram
Wakeup
tsu(wakeup)
Figure 2. Wakeup Terminal Setup Timing Diagram
8
0
30
100
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ns
ns
MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
B1
tsu(interrupt)
Figure 3. External Interrupt Terminal Setup Timing Diagram
B1
th1(B1)
tsu1(B1)
tw
B0
tr
tf
tsu(d)
th(d)
PA
Data Valid
Figure 4. Write Timing Diagram (Slave Mode)
B1
tsu2(B1)
th2(B1)
tw
B0
tf
tr
tdis
td
PA
Data Valid
Figure 5. Read Timing Diagram (Slave Mode)
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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.035 (0,89) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
0°– 15°
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
10
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright  1998, Texas Instruments Incorporated
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