Intersil CD40160BMS Cmos synchronous programmable 4-bit counter Datasheet

CD40160BMS, CD40161BMS, CD40162BMS,
CD40163BMS
December 1992
File Number
CMOS Synchronous Programmable 4-Bit
Counters
Features
CD40160BMS,
CD40161BMS,
CD40162BMS
and
CD40163BMS are 4-bit synchronous programmable
counters. The CLEAR function of the CD40162BMS and
CD40163BMS is synchronous and a low level at the CLEAR
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and
CD40161BMS is asychronous and a low level at the CLEAR
input sets all four outputs low regardless of the state of the
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree
with the setup data after the next CLOCK pulse regardless of
the conditions of the ENABLE inputs.
• CD40160BMS Decade with Asynchronous Clear
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count-enable
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to
enable COUT. This enabled output produces a positive output
pulses with a duration approximately equal to the positive portion
of the Q1 output. This positive overflow carry pulse can be used
to enable successive cascaded stages. Logic transitions at the
PE or TE inputs may occur when the clock is either high or low.
• Low Power TTL Compatibility
The CD40160BMS through CD40163BMS types are functionally
equivalent to and pin-compatible with the TTL counter series
74LS160 through 74LS163 respectively.
• 5V, 10V and 15V Parametric Ratings
The CD40160BMS, CD40161BMS, CD40162BMS and
CD40163BMS are supplied in these 16 lead outline packages:
CD40160 CD40161 CD40162 CD40163
• High-Voltage Types (20V Rating)
• CD40161BMS Binary with Asynchronous Clear
• CD40162BMS Decade with Synchronous Clear
• CD40163BMS Binary with Synchronous Clear
• Internal Look-Ahead for Fast Counting
• Carry Output for Cascading
• Synchronously Programmable
• Clear Asynchronous Input (CD40160BMS, CD40161BMS)
• Clear Synchronous Input (CD40162BMS, CD40163BMS)
• Synchronous Load Control Input
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series CMOS
Devices”
Applications
• Programmable Binary and Decade Counting
Braze Seal DIP
H4W
H4X
H4X
H4W
• Counter Control/Timers
Frit Seal DIP
H1F
H1F
H1L
H1F
• Frequency Dividing
Ceramic Flatpack
H6P
H6W
H6P
H6W
Pinout
3358
Functional Diagram
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TOP VIEW
PE
TE
16 VDD
CLEAR 1
CLEAR
15 CARRY OUT
CLOCK 2
P1 3
14 Q1
LOAD
P2 4
13 Q2
CLOCK
P3 5
12 Q3
P1
P4 6
11 Q4
P2
10 TE
P3
PE 7
9 LOAD
VSS 8
VDD = 16
VSS = 8
4-1
P4
7
14
Q1
10
1
13
Q2
9
2
12
Q3
3
4
11
Q4
5
6
15
CARRY
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance. . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . .
80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . .
70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
-
50
mV
14.95
-
V
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
Input Leakage Current
IIL
IIH
VIN = VDD or GND
VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
-
-1.8
mA
-
-1.4
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-3.5
mA
-2.8
-0.7
V
0.7
2.8
V
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
VSS = 0V, IDD = 10µA
1
+25oC
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
P Threshold Voltage
Functional
VPTH
F
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented.
2. Go/No Go test with limits applied to inputs.
4-2
3. For accuracy, voltage is measured differentially to VDD. Limit is
0.050V max.
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Q
Propagation Delay
Clock to COut
Propagation Delay
TE to COut
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
Transition Time
Maximum Clock Input Frequency
SYMBOL
TPHL1
TPLH1
TPHL2
TPLH2
TPHL3
TPLH3
TPHL4
CONDITIONS (NOTE 1, 2)
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
FCL
VDD = 5V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
-
400
ns
10, 11
+125oC, -55oC
-
540
ns
9
+25oC
-
450
ns
10, 11
+125oC, -55oC
-
608
ns
9
+25oC
-
250
ns
10, 11
+125oC, -55oC
-
338
ns
9
+25oC
-
500
ns
10, 11
+125oC, -55oC
-
675
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
9
+25oC
2
-
MHz
10, 11
+125oC, -55oC
1.48
-
MHz
MAX
UNITS
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
1, 2
-55oC, +25oC
+125oC
-
5
µA
-
150
µA
-55oC, +25oC
+125oC
-
10
µA
-
300
µA
-55oC, +25oC
+125oC
-
10
µA
-
600
µA
-
50
mV
1, 2
1, 2
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC, 55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC, 55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC, 55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC, 55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
4-3
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH15
CONDITIONS
VDD =15V, VOUT = 13.5V
NOTES
TEMPERATURE
MIN
1, 2
+125oC
MAX
UNITS
-
-2.4
mA
-55oC
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, 55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC, 55oC
7
-
V
Propagation Delay
Clock to Q
TPHL1
TPLH1
VDD = 10V
1, 2, 3
+25oC
-
160
ns
VDD = 15V
1, 2, 3
+25oC
-
120
ns
VDD = 10V
1, 2, 3
+25oC
-
190
ns
VDD = 15V
1, 2, 3
+25oC
-
140
ns
Propagation Delay
Clock to C Out
TPHL2
TPLH2
Propagation Delay
TE to C Out
TPHL3
TPLH3
VDD = 10V
1, 2, 3
+25oC
-
110
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
TPHL4
VDD = 10V
1, 2, 3
+25oC
-
220
ns
VDD = 15V
1, 2, 3
+25oC
-
160
ns
TTHL
TTLH
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
FCL
VDD = 10V
1, 2, 3
+25oC
5.5
-
MHz
VDD = 15V
1, 2, 3
+25oC
8
-
MHz
VDD = 5V
1, 2, 3, 4
+25oC
-
200
µs
VDD = 10V
1, 2, 3, 4
+25oC
-
70
µs
VDD = 15V
1, 2, 3, 4
+25oC
-
15
µs
VDD = 5V
1, 2, 3
+25oC
-
0
ns
VDD = 10V
1, 2, 3
+25oC
-
0
ns
VDD = 15V
1, 2, 3
+25oC
-
0
ns
VDD = 5V
1, 2, 3
+25oC
-
170
ns
VDD = 10V
1, 2, 3
+25oC
-
70
ns
VDD = 15V
1, 2, 3
+25oC
-
50
ns
VDD = 5V
1, 2, 3
+25oC
-
240
ns
VDD = 10V
1, 2, 3
+25oC
-
90
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
VDD = 5V
1, 2, 3
+25oC
-
240
ns
VDD = 10V
1, 2, 3
+25oC
-
90
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
VDD = 5V
1, 2, 3
+25oC
-
340
ns
VDD = 10V
1, 2, 3
+25oC
-
140
ns
VDD = 15V
1, 2, 3
+25oC
-
100
ns
VDD = 5V
1, 2, 3
+25oC
-
170
ns
VDD = 10V
1, 2, 3
+25oC
-
70
ns
VDD = 15V
1, 2, 3
+25oC
-
50
ns
VDD = 5V
1, 2, 3
+25oC
-
340
ns
VDD = 10V
1, 2, 3
+25oC
-
140
ns
1, 2, 3
+25oC
-
100
ns
VDD = 5V
1, 2, 3
+25oC
-
0
ns
VDD = 10V
1, 2, 3
+25oC
-
0
ns
1, 2, 3
+25oC
-
0
ns
Transition Time
Maximum Clock Input Frequency
Maximum Clock Rise or
Fall Time
Minimum Data Hold Time
Clock Operation
Minimum Clock Pulse
Width
Clock Operation
Minimum Setup Time
Data to Clock
Minimum Setup Time
Load to Clock
Minimum Setup Time PE
to TE to Clock
Minimum Clear Pulse
Width (CD40160BMS,
CD40161BMS)
Minimum Setup Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
Minimum Hold Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
TRCL
TFCL
TH
TW
TS
TS
TS
TW
TS
VDD = 15V
TH
VDD = 15V
4-4
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Minimum Clear Removal
Time
(CD40160BMS,
CD40161BMS)
TREM
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
VDD = 5V
1, 2, 3
+25oC
-
200
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
70
ns
VDD = 15V
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of
the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
N Threshold Voltage
N Threshold Voltage Delta
P Threshold Voltage
P Threshold Voltage Delta
VNTH
∆VTN
VTP
∆VTP
Functional
F
CONDITIONS
NOTES
TEMPERATURE
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
VDD = 10V, ISS = -10µA
1, 4
+25oC
VSS = 0V, IDD = 10µA
1, 4
+25oC
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
MIN
MAX
UNITS
-
25
µA
-2.8
-0.2
V
-
±1
V
0.2
2.8
V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
DELTA LIMIT
IDD
± 1.0µA
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
4-5
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
Static Burn-In 1 Note 1
11 - 15
1 - 10
16
Static Burn-In 2 Note 1
11 - 15
8
1 - 7, 9, 10, 16
Dynamic Burn-In Note 1
Irradiation Note 2
VDD
-
8
1, 7, 9, 10, 16
11 - 15
8
1 - 7, 9, 10, 16
9V ± -0.5V
50kHz
25kHz
11 - 15
2-6
-
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagrams
CD40160BMS AND CD40162BMS BCD DECADE COUNTERS
CD40160BMS
ASYNCHRONOUS
CLEAR
*
*
*
*
*
*
*
7
10
3
4
5
16
6
PE
TE
P1
P2
P3
Q1
Q4
VDD
Q1
Q4
P4
Q1
LOAD*
9
CLOCK*
2
CLEAR*
1
Q1
LOAD*
CD40162BMS
SYNCHRONOUS
CLEAR
9
LD PI
Q1
T
CLOCK*
CL
CLR
2
LD PI
Q2
T
Q1
CL
CLR
LD PI
Q3
T
Q2
CL
CLR
LD PI
Q4
T
Q3
CL
CLR
Q4
CLEAR*
1
*INPUTS PROTECTED BY
VDD
CMOS PROTECTION NETWORK
14 Q1
13 Q2
12 Q3
11 Q4
VSS
FIGURE 1. LOGIC DIAGRAM FOR CD40160BMS AND CD40162BMS BCD DECADE COUNTERS
4-6
15 COUT
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Logic Diagrams
(Continued)
CD40161BMS AND CD40163BMS BINARY COUNTERS
CD40161BMS
ASYNCHRONOUS
CLEAR
*
*
*
7
10
3
PE
TE
16
*
*
*
4
5
6
VDD
P1
P2
P3
Q1
Q2
Q1
LOAD*
P4
Q1
Q2
Q2
9
CLOCK*
2
Q2
Q4
Q3
CLEAR*
1
LOAD*
CD40163BMS
SYNCHRONOUS
CLEAR
Q1
9
LD PI
Q1
T
CLOCK*
Q2
T
CL
CLR
2
LD PI
Q1
CL
CLR
LD PI
Q3
T
Q2
LD PI
Q4
T
CL
CLR
Q3
CL
CLR
Q4
CLEAR*
1
*INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
14 Q1
13 Q2
12 Q3
11 Q4
VSS
FIGURE 2. LOGIC DIAGRAM FOR CD40161BMS AND CD40163BMS BINARY COUNTERS
TRUTH TABLE
CLOCK
X
1 = High Level
0 = Low Level
4-7
CLR
LOAD
PE
TE
1
0
X
X
Preset
OPERATION
1
1
0
X
NC
1
1
X
0
NC
1
1
1
1
Count
0
X
X
X
Reset (CD40160BMS, CD40161BMS)
0
X
X
X
Reset (CD40162BMS, CD40163BMS)
1
X
X
X
NC (CD40162BMS, CD40163BMS)
X = Don’t Care
NC = No Change
15 COUT
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-5
-10
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
10V
7.5
5.0
2.5
5V
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q)
4-8
0
-5
-10V
-10
-15V
-15
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
300
20
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (TA) = +25oC
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
TRANSITION TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
FIGURE 4. MIMIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
AMBIENT TEMPERATURE (TA) = +25oC
15.0
0
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSISTION TIME AS A FUNCTION OF
LOAD CAPACITANCE
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
Typical Performance Characteristics
(Continued)
POWER DISSIPATION (PD) (µW)
105 8
AMBIENT TEMPERATURE (TA)
6
o
4 = +25 C
104
2
SUPPLY VOLTAGE (VDD)
= 15V
8
6
4
103
2
10V
8
6
4
102
10V
5V
2
8
6
4
CL = 50pF
CL = 15pF
2
10
2
4 68
2
4 68
2
4 68
2
4 68
103
10
102
CLOCK FREQUENCY (fCL) (kHz)
1
2
4 68
104
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
CLEAR (CD40160BMS)
ASYNCHRONOUS
CLEAR (CD40162BMS)
SYNCHRONOUS
LOAD
P1
P2
DATA INPUTS
P3
P4
CLOCK (CD40160BMS)
CLOCK (CD40162BMS)
PE
ENABLES
TE
Q1
Q2
OUTPUTS
Q3
Q4
CARRY OUT
0
7
8
9
0
1
2
3
COUNT
CLEAR
PRESET
FIGURE 10. TIMING DIAGRAM FOR CD40160BMS, CD40162BMS
4-9
INHIBIT
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
CLEAR (CD40161BMS)
ASYNCHRONOUS
CLEAR (CD40163BMS)
SYNCHRONOUS
LOAD
P1
P2
DATA INPUTS
P3
P4
CLOCK (CD40161BMS)
CLOCK (CD40163BMS)
PE
ENABLES
TE
Q1
Q2
OUTPUTS
Q3
Q4
CARRY OUT
0
12
13
14
15
0
1
2
COUNT
CLEAR
PRESET
FIGURE 11. TIMING DIAGRAM FOR CD40161BMS AND CD40163BMS
4-10
INHIBIT
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TN
PN
LD
CL
p
CLR
CL
n
CL
p
n
CL
CL
p
p
n
n
CL
p
n
CL
p
p
n
n
CL
CL
QN
QN
FIGURE 12. DETAIL OF FLIP-FLOPS OF CD40160BMS AND CD40161BMS (ASYNCHRONOUS CLEAR)
TN
CLR
PN
CL
LD
p
CL
n
CL
p
n
CL
CL
p
p
n
n
CL
CL
p
n
p
p
n
n
CL
CL
QN
QN
FIGURE 13. DETAIL OF FLIP-FLOPS OF CD40162BMS AND CD40163BMS (SYNCHRONOUS CLEAR)
4-11
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
LOAD
VDD
P1
P2
P3
P4
P1
P2
P3
P1
P4
P2
P3
P4
VDD
PE
LD
PE
TE
CD
LD
PE
TE
CLK CLR
CD
TE
CLK CLR
Q1 Q2 Q3
Q4
LD
CD
CLK CLR
Q1 Q2
Q1
Q3 Q4
Q2 Q3 Q4
CLOCK
CLEAR
FIGURE 14. CASCADED COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE
LOAD
VDD
VDD
P1
PE
P2
P3
P1
P4
LD
PE
TE
CD
CLK CLR
CLOCK
VDD
P2
P3
P4
P1
LD
PE
TE
CD
Q4
P3
P4
LD
TE
CLK CLR
Q1 Q2 Q3
P2
CD
CLK CLR
Q1 Q2
Q3 Q4
Q1
Q2 Q3 Q4
CLEAR
FIGURE 15. CASCADED COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE
Chip Dimensions and Pad Layout
Dimensions and pad layout for CD40160BMSH.
Dimensions and pad layout for CD40161BMS,
CD40162BMSH, and CD40163BMSH are identical.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION:
PASSIVATION:
BOND PADS:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
4-12
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
4-13
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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ASIA
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Republic of China
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