IXYS IXDD504D2 4 ampere dual low-side ultrafast mosfet drivers with enable for fast, controlled shutdown Datasheet

IXDD504/ IXDE504
4 Ampere Dual Low-Side Ultrafast MOSFET Drivers
with Enable for fast, controlled shutdown
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 4 Amps
• High 4A Peak Output Current
• Wide Operating Range: 4.5V to 30V
• -55°C to +125°C Extended Operating
Temperature
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in a Single Package
The IXDD504 and IXDE504 each consist of two 4-Amp
CMOS high speed MOSFET gate drivers for driving the
latest IXYS MOSFETs & IGBTs. Each of the dual outputs
can source and sink 4 Amps of peak current while producing voltage rise and fall times of less than 15ns. The input
of each driver is TTL or CMOS compatible and is virtually
immune to latch up. Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by fast,
matched rise and fall times.
Applications
•
•
•
•
•
•
•
•
•
•
•
Limiting di/dt under Short Circuit
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
Additionally, each IXDD504 or IXDE504 driver incorporates a
unique ability to disable the output under fault conditions.
When a logical low is forced into the Enable input of a
driver, both of it's final output stage MOSFETs (NMOS and
PMOS) are turned off. As a result, the respective output of
the IXDD504 enters a tristate mode and, with additional
cicuitry, achieves a soft turn-off of the MOSFET/IGBT when
a short circuit is detected. This helps prevent damage that
could occur to the MOSFET/IGBT if it were to be switched
off abruptly due to a dv/dt over-voltage transient.
The IXDD504 and IXDE504 are each available in the 8-Pin
P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the
8-Lead DFN (D2) package, (which occupies less than 65%
of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number
Description
IXDD504PI
IXDD504SIA
IXDD504SIAT/R
IXDD504D2
IXDD504D2T/R
IXDE504PI
IXDE504SIA
IXDE504SIAT/R
IXDE504D2
IXDE504D2T/R
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
8-Lead DFN
8-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
8-Lead DFN
8-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Dual NonInverting
Drivers with
Enable
Dual Inverting
Drivers
Inverting with
Enable
NOTE: All parts are lead-free and RoHS Compliant
DS99568A(10/07)
Copyright © 2007 IXYS CORPORATION All rights reserved
First Release
IXDD504 / IXDE504
Figure 1 - IXDD504 Dual Non-Inverting + Enable 4A Gate Driver Functional Block Diagram
Vcc
200 K
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
*
EN A
200 K
OUT A
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN B
*
EN B
OUT B
N
GND
Figure 2 - IXDE504 Dual Inverting + Enable 4A Gate Driver Functional Block Diagram
Vcc
200 K
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
*
EN A
200 K
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN B
*
EN B
GND
*
United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
OUT A
N
2
OUT B
N
IXDD504 / IXDE504
Absolute Maximum Ratings (1)
Operating Ratings (2)
Parameter
Supply Voltage
All Other Pins (unless specified
otherwise)
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55 °C to 125 °C
Package Thermal Resistance *
θJ-A (typ) 125 °C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θJ-A(typ) 200 °C/W
8-Lead DFN
(D2)
θJ-A(typ) 125-200 °C/W
θJ-C(max) 2.1 °C/W
8-Lead DFN
(D2)
8-Lead DFN
(D2)
θJ-S(typ) 6.4 °C/W
Value
35 V
-0.3 V to VCC + 0.3V
150 °C
-65 °C to 150 °C
300 °C
Electrical Characteristics @ TA = 25 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .
All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.
(4)
Symbol
Parameter
Test Conditions
Min
VIH, VENH
High input & EN voltage
4.5V ≤ VIN ≤ 18V
3
VIL, VENL
Low input & EN voltage
4.5V ≤ VIN ≤ 18V
VIN
Input voltage range
VEN
Enable voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
High state output resistance
ROL
Low state output resistance
IPEAK
Peak output current
IDC
Continuous output current
tR
Rise time
tF
Fall time
tONDLY
On-time propagation delay
tOFFDLY
Off-time propagation delay
tENOH
VCC
Enable to output high delay time
Disable to high impedance state
delay time
Power supply voltage
REN
Enable Pull-up Resistor
ICC
Power supply current
tDOLD
0V ≤ VIN ≤ VCC
Typ
Max
V
0.8
V
-5
VCC + 0.3
V
- 0.3
VCC + 0.3
V
-10
10
µA
VCC - 0.025
VCC = 18V
IOUT = 10mA
VCC = 18V
IOUT = 10mA
VCC = 15V
Limited by package
dissipation
CLOAD =1000pF
VCC =18V
CLOAD =1000pF
VCC =18V
CLOAD =1000pF
VCC =18V
CLOAD =1000pF
VCC =18V
V
0.025
V
1.5
2.5
Ω
1.2
2.0
Ω
4
4.5
A
1
A
9
16
ns
8
14
ns
19
40
ns
18
35
ns
15
30
ns
63
100
ns
18
30
V
20
3
20
kΩ
µA
mA
mA
200
VCC = 18V, VIN = 0V
VIN = 3.5V
VIN = VCC
IXYS reserves the right to change limits, test conditions, and dimensions.
3
Units
1
IXDD504 / IXDE504
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 18V
3
VIL
Low input voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
IDC
Low output voltage
High state output
resistance
Low state output
resistance
Continuous output current
tR
Rise time
tF
Fall time
0V ≤ VIN ≤ VCC
Typ
Max
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
VCC = 18V, IOUT = 10mA
3
Ω
VCC = 18V, IOUT = 10mA
2.5
Ω
1
A
CLOAD =1000pF VCC =18V
10
ns
CLOAD =1000pF VCC =18V
9
ns
tONDLY
On-time propagation delay CLOAD =1000pF VCC =18V
23
ns
tOFFDLY
Off-time propagation delay CLOAD =1000pF VCC =18V
Enable to output high
delay time
Disable to high impedance
state delay time
Power supply voltage
High impedance state
VCC = 18V, Temp. = 125°C
output leakage
VCC = 18V, VIN = 0V
VIN = 3.5V
Power supply current
VIN = VCC
32
ns
60
ns
120
ns
30
V
200
µA
150
3
150
µA
mA
mA
ROH
ROL
tENOH
tDOLD
VCC
IHIOL
ICC
4.5
18
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 8-Lead DFN package, the θJ-A value supposes the DFN package is soldered
on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance
to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W
easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size,
construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDD504 / IXDE504
Pin Description
SYMBOL
FUNCTION
EN A
A Channel Enable
IN A
A Channel Input
GND
Ground
IN B
B Channel Input
OUT B
B Channel Output
VCC
Supply Voltage
OUT A
A Channel Output
EN B
B Channel Enable
DESCRIPTION
Channel A enable pin. When driven low, this pin disables the A channel and
forces a high impedance state to the A channel output.
A channel input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry, this pin provides
ground reference for the entire chip. This pin should be connected to a low
noise analog ground plane for optimum performance.
B channel input signal-TTL or CMOS compatible.
B channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power to the entire
chip. The range for this voltage is from 4.5V to 30V.
A channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
Channel B enable pin. When driven low, this pin disables the B channel and
forces a high impedance state to the B channel output.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configurations
8 PIN DIP (PI)
8 PIN SOIC (SIA)
8 PIN DIP (PI)
8 PIN SOIC (SIA)
1 EN A
2 IN A
3 GND
4 IN B
I
X
D
D
5
0
4
EN B 8
EN A
1
OUT A 7
IN A
2
I
X
D
E
5
0
4
GND 3
VCC 6
OUT B 5
IN B
4
8 LEAD DFN (D2)
(Bottom View)
OUT A
8
GND
7
VCC
6
OUT B
5
I
X
D
D
5
0
4
8
EN B
7
OUT A
6
VCC
5
OUT B
8 LEAD DFN (D2)
(Bottom View)
1 EN A
OUT A
8
2 IN A
GND
7
3 IN B
VCC
6
4 EN B
OUT B
5
I
X
D
E
5
0
4
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 3 - Characteristics Test Diagram
VIN
IXYS reserves the right to change limits, test conditions, and dimensions.
5
1 EN A
2 IN A
3 IN B
4 EN B
IXDD504 / IXDE504
Typical Performance Characteristics
Fig. 5
Rise Times vs. Supply Voltage
90
80
80
70
70
60
Fall Time (ns)
Rise Time (ns)
Fig. 4
60
50
10000pF
40
30
50
10000pF
40
30
5400pF
20
5400pF
20
Fall Time vs. Supply Voltage
10
10
1000pF
1000pF
0
100pF
0
100pF
0
0
5
10
15
20
25
30
5
15
20
25
30
35
Supply Voltage (V)
Supply Voltage (V)
Rise / Fall Time vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
Fig. 6
10
35
Fig. 7
Rise Time vs. Capacitive Load
70
10
5V
60
8
Rise Time (ns)
Rise / Fall Time (ns)
9
7
6
5
4
3
2
50
15V
30V
40
30
20
10
1
0
100
0
-50
-30
-10
10
30
50
70
90
110
130
150
1000
Temperature (C)
Fig. 8
Fig. 9
Fall Time vs. Capacitive Load
Input Threshold Levels vs. Supply Voltage
70
2.5
Threshold Level (V)
5V
60
Fall Time (ns)
10000
Load Capacitance (pF)
50
15V
30V
40
30
20
2
Positive going input
1.5
Negative going input
1
0.5
10
0
100
0
1000
0
10000
10
15
20
25
Supply Voltage (V)
Load Capacitance (pF)
Copyright © 2007 IXYS CORPORATION All rights reserved
5
6
30
35
IXDD504 / IXDE504
Input Threshold Levels vs. Temperature
Fig. 10
VSUPPLY = 15V
2.5
2
Positive going input
1.5
Negative going input
1
0.5
0
-50
Propagation Delay vs. Supply Voltage
Rising Input, CLOAD = 1000pF
35
Propagation Delay Time (ns)
3
Input Threshold Level (V)
Fig. 11
30
25
20
15
10
5
0
-30
-10
10
30
50
70
90
110
130
0
150
5
10
Temperature (C)
30
35
35
40
Propagation Delay Time (ns)
Propagation Delay Time (ns)
25
Propagation Delay vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
Fig. 13
45
35
30
25
20
15
10
5
0
0
5
10
15
20
25
30
30
Negative going input
25
20
15
Positve going input
10
5
0
-50
35
0
Supply Voltage (V)
Fig. 14
Quiescent Current (uA)
0.01
10
15
20
25
150
30
VSUPPLY = 15V
1000
0.1
5
100
Quiescent Current vs. Temperature
Fig. 15
1
0
50
Temeprature (C)
Quiescent Current vs. Supply Voltage
VIN = 0V
10
Quiesent Current (uA)
20
Supply Voltage (V)
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
Fig. 12
15
100
10
1
Non-inverting, Input= "0"
Inverting Input = "1"
0.1
0.01
-50
35
Supply Voltage (V)
-30
-10
10
30
50
70
Temperature (C)
7
90
110
130
150
IXDD504 / IXDE504
Supply Current vs. Capacitive Load
VSUPPLY = 5V
Fig. 16
Fig. 17
2MHz
100
Supply Current vs. Frequency
VSUPPLY = 5V
100
10000pF
5400pF
Supply Current (mA)
Supply Current (mA)
1MHz
10
100kHz
1
10kHz
0.1
0.01
100
1000pF
10
100pF
1
0.1
0.01
1000
10000
10
Load Capacitance (pF)
1000
Fig. 19
Supply Current vs. Frequency
VSUPPLY = 15V
1000
1000
10000pF
5400pF
2MHz
Supply Current (mA)
Supply Current (mA)
1MHz
100
100kHz
10
10kHz
1
0.1
0.01
100
1000
100
1000pF
100pF
10
1
0.1
0.01
10000
10
Load Capacitance (pF)
Fig. 21
10000
Supply Current vs. Frequency
VSUPPLY = 30V
2MHz
10000pF
1MHz
5400pF
Supply Current (mA)
Supply Current (mA)
1000
1000
1000
100
100kHz
10
10kHz
1
0.1
100
100
Frequency (kHz)
Supply Current vs. Capacitive Load
VSUPPLY = 30V
Fig. 20
10000
Frequency (kHz)
Supply Current vs. Capacitive Load
VSUPPLY = 15V
Fig. 18
100
1000pF
100
100pF
10
1
0.1
1000
10
10000
1000
Frequency (kHz)
Load Capacitance (pF)
Copyright © 2007 IXYS CORPORATION All rights reserved
100
8
10000
IXDD504 / IXDE504
Fig. 22
Output Source Current vs. Supply Voltage
Fig. 23
12
-2
Sink Current (A)
10
Source Current (A)
Output Sink Current vs. Supply Voltage
0
8
6
4
-4
-6
-8
-10
2
-12
0
-14
0
5
10
15
20
25
30
35
0
5
10
Supply Voltage (V)
Fig. 24
Fig. 25
Output Source Current vs. Temperature
VSUPPLY = 15V
25
30
35
Output Sink Current vs. Temperature
VSUPPLY = 15V
0
Output Sink Current (A)
Output Source Current (A)
20
Supply Voltage (V)
6
5
4
3
2
1
-1
-2
-3
-4
-5
-6
0
-50
0
50
100
-50
150
0
50
100
150
Temperature (C)
Temperature (C)
Fig. 26
Fig. 27
Low State Output Resistance vs. Supply Voltage
High State Output Resistance vs. Supply Voltage
3
3
Output Resistance (ohms)
Output Resistance (ohms)
15
2.5
2
1.5
1
0.5
0
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
35
0
Supply Voltage (V)
5
10
15
20
Supply Voltage (V)
9
25
30
35
IXDD504 / IXDE504
Fig. 29
Fig. 28
ENABLE Threshold vs. Temperature
VSUPPLY = 15V
ENABLE Threshold vs. Supply Voltage
1.8
2.5
Positive going input
Enable Threshold (V)
Positive Going Level (V)
1.6
2
Positive going input
1.5
Negative going input
1
0.5
1.4
1.2
Negative going input
1
0.8
0.6
0.4
0.2
0
0
0
5
10
15
20
25
30
-50
35
0
Supply Voltage (V)
50
100
150
Temperature (C)
Fig. 30
Fig. 31
ENABLE Propagation vs. Temperature
VSUPPLY = 15V
ENABLE Propagation Time vs. Supply Voltage
100
400
ENABLE Delay Time (ns)
ENABLE Delay Time (ns)
90
350
300
250
200
150
100
Negative going ENABLE to high impedance state
50
10
15
20
25
60
Negative going ENABLE to high impedance state
50
40
30
Positive going ENABLE to output ON
20
0
-50
0
5
70
10
Positve going ENABLE to output ON
0
80
30
35
0
50
Temperature (C)
Supply Voltage (V)
Figure 32 - Typical Application Short Circuit di/dt Limit
Ref
Copyright © 2007 IXYS CORPORATION All rights reserved
10
100
150
IXDD504 / IXDE504
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 32, can cause the current
through the module to flow in excess of 60A for 10µs or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
The IXDD504 and IXDE504 have the unique capability, with
additional circuitry, to softly switch off the high-power MOSFET
module, significantly reducing these Ldi/dt transients.
Thus, the IXDD504 & IXDE504 help to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients.
The IXDD504 & IXDE504 are designed to not only provide ±4A
per output under normal conditions, but also to allow their
outputs to go into a high impedance state. This permits the
IXDD504 or IXDE504 outputs to control a separate weak pulldown circuit during detected overcurrent shutdown conditions
to limit and separately control dVGS/dt gate turnoff. This circuit
is shown in Figure 33.
Referring to Figure 33, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFN100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7002, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD504 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD504 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD504 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD504 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD504, preventing its destruction.
Ld
10uH
Figure 33 - Application Test Diagram
VCC
+
-
VCC
+
-
VIN
-
Rg
OUT
Rsh
1600
IXFN100N20
1
Rs
Low_Power
2N7000
R+
10k
One Shot Circuit
NAND
CD4011A
NOT1
CD4049A
Rcomp
5k
NOT2
CD4049A
Ros
1M
R
Cos
1pF
Ccomp
1pF
NOT3
CD4049A
Comp
LM339
NOR1
CD4001A
EN
V-
NOR2
CD4001A
SR Flip-Flop
11
C+
100pF
+
S
Ls
20nH
+
V+
REF
Q
VB
Rd
0.1
IXDD504
IN
EN
DGND
+
-
IXDD504 / IXDE504
Supply Bypassing and Grounding Practices, Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD504 or IXDE504, it is very important to keep
certain design criteria in mind, in order to optimize performance
of the driver. Particular attention needs to be paid to Supply
Bypassing, Grounding, and minimizing the Output Lead
Inductance.
Say, for example, we are using the IXDD504 to charge a
2500pF capacitive load from 0 to 25 volts in 25ns.
Using the formula: IC = C (∆V / ∆t), where ∆V=25V C=2500pF
and ∆t=25ns we can determine that to charge 2500pF to 25
volts in 25ns will take a constant current of 2.5A. (In reality, the
charging current won’t be constant, and will peak somewhere
around 4A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD504
must be able to draw this 2.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD504
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD504
must be able to drain this 2.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD504
and it’s load. Path #2 is between the IXDD504 and it’s power
supply. Path #3 is between the IXDD504 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep
these three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD504.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be
placed farther than 0.2” from the load, then the output leads
should be treated as transmission lines. In this case, a
twisted-pair should be considered, and the return line of each
twisted pair should be placed as close as possible to the
ground pin of the driver, and connect directly to the ground
terminal of the load.
Copyright © 2007 IXYS CORPORATION All rights reserved
12
IXDD504 / IXDE504
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
E
H
B
C
D
E
e
H
h
L
M
N
D
A
A1
e
B
h X 45
N
L
C
M
0.048 [1.22]
0.035 [0.90]
0.048 [1.22]
[
S0.002^0.000; o S0.05^0.00;o
]
0.031 [0.78]
0.022 [0.55]
0.016 [0.40]
0.121 [3.06]
0.101 [2.56]
0.158 [4.00]
0.197 [5.00]
0.031 [0.78]
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
13
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