ONSEMI MMDF2C03HDR2G

MMDF2C03HD
Preferred Device
Power MOSFET
2 Amps, 30 Volts
Complementary SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain-to-source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc-dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
Features
•
•
•
•
•
•
•
•
•
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2 AMPERES, 30 VOLTS
RDS(on) = 70 mW (N-Channel)
RDS(on) = 200 mW (P-Channel)
N−Channel
P−Channel
D
D
G
G
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Miniature SO-8 Surface Mount Package − Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO-8 Package Provided
Pb−Free Package is Available
S
S
MARKING
DIAGRAM
8
SO−8
CASE 751
STYLE 14
8
1
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
Vdc
Gate−to−Source Voltage
VGS
± 20
Vdc
ID
4.1
3.0
21
15
A
Rating
Drain Current − Continuous
Drain Current − Pulsed
N−Channel
P−Channel
N−Channel
P−Channel
IDM
Operating and Storage Temperature Range
TJ, Tstg
− 55 to 150
°C
Total Power Dissipation @ TA= 25°C (Note 2)
PD
2.0
W
Thermal Resistance, Junction−to−Ambient
(Note 2)
RqJA
62.5
°C/W
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk,
N−Channel
L = 8.0 mH, RG = 25 W)
(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk,
P−Channel
L = 18 mH, RG = 25 W)
EAS
Max Lead Temperature for Soldering, 0.0625″
from case. Time in Solder Bath is 10 seconds
TL
mJ
February, 2006 − Rev. 7
D2C03 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
N−Source
1
8
N−Drain
N−Gate
2
7
N−Drain
P−Source
3
6
P−Drain
P−Gate
4
5
P−Drain
ORDERING INFORMATION
324
324
°C
260
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with
one die operating, 10 sec. max.
© Semiconductor Components Industries, LLC, 2006
D2C03
AYWWG
G
1
Device
Package
Shipping†
MMDF2C03HDR2
SO−8
2500 Tape & Reel
MMDF2C03HDR2G
SO−8
2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MMDF2C03HD/D
MMDF2C03HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3)
Symbol
Characteristic
Polarity
Min
Typ
Max
−
30
−
−
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
V(BR)DSS
Vdc
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
IDSS
(N)
(P)
−
−
−
−
1.0
1.0
mAdc
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
−
−
−
100
nAdc
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
VGS(th)
(N)
(P)
1.0
1.0
1.7
1.5
3.0
2.0
Vdc
Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)
RDS(on)
(N)
(P)
−
−
0.06
0.17
0.070
0.200
Drain−to−Source On−Resistance
(VGS = 4.5 Vdc, ID = 1.5 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
RDS(on)
(N)
(P)
−
−
0.065
0.225
0.075
0.300
Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)
gFS
(N)
(P)
2.0
2.0
3.6
3.4
−
−
Ciss
(N)
(P)
−
−
450
397
630
550
Coss
(N)
(P)
−
−
160
189
225
250
Crss
(N)
(P)
−
−
35
64
70
126
td(on)
(N)
(P)
−
−
12
16
24
32
ON CHARACTERISTICS (Note 4)
W
W
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
(VDD = 15 Vdc, ID = 3.0 Adc,
VGS = 4.5 Vdc, RG = 9.1 W)
tr
(N)
(P)
−
−
65
18
130
36
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc, RG = 6.0 W)
td(off)
(N)
(P)
−
−
16
63
32
126
tf
(N)
(P)
−
−
19
194
38
390
td(on)
(N)
(P)
−
−
8.0
9.0
16
18
Fall Time
Turn−On Delay Time
Rise Time
(VDD = 15 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc, RG = 9.1 W)
tr
(N)
(P)
−
−
15
10
30
20
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc, RG = 6.0 W)
td(off)
(N)
(P)
−
−
30
81
60
162
tf
(N)
(P)
−
−
23
192
46
384
QT
(N)
(P)
−
−
11.5
14.2
16
19
Fall Time
Total Gate Charge
Gate−Source Charge
(VDS = 10 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
Q1
(N)
(P)
−
−
1.5
1.1
−
−
Gate−Drain Charge
(VDS = 24 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q2
(N)
(P)
−
−
3.5
4.5
−
−
Q3
(N)
(P)
−
−
2.8
3.5
−
−
3. Negative signs for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperature.
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2
ns
nC
MMDF2C03HD
ELECTRICAL CHARACTERISTICS − continued (TA = 25°C unless otherwise noted) (Note 6)
Characteristic
Symbol
Polarity
Min
Typ
Max
Unit
VSD
(N)
(P)
−
−
0.82
1.82
1.2
2.0
Vdc
trr
(N)
(P)
−
−
24
42
−
−
ns
ta
(N)
(P)
−
−
17
16
−
−
tb
(N)
(P)
−
−
7.0
26
−
−
QRR
(N)
(P)
−
−
0.025
0.043
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C)
Forward Voltage (Note 7)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
(IF = IS, dIS/dt = 100 A/ms)
Reverse Recovery Storage
Charge
mC
6. Negative signs for P−Channel device omitted for clarity.
7. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
VGS = 10 V
3.9 V
4.5 V
5
4.3 V
4.1 V
4
4
3.5 V
3.7 V
3.3 V
3
3.1 V
2
2.9 V
1
0
VGS = 10 V 4.5 V
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
6
P−Channel
0
0.2
0.6
0.4
0.8
1.2
1
3.3 V
3.1 V
2
2.9 V
1
2.7 V
2.5 V
1.6
1.4
1.8
0
2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 1. On−Region Characteristics
4
VDS ≥ 10 V
5
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
TJ = 25°C
3.9 V
3
2.7 V
2.5 V
6
4
TJ = 100°C
3
25°C
2
2
VDS ≥ 10 V
3
2
TJ = 100°C
25°C
1
− 55°C
1
0
3.7 V 3.5 V
− 55°C
2
2.5
3
3.5
0
1.5
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
Figure 2. Transfer Characteristics
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3
1.7
3.5
3.7
MMDF2C03HD
N−Channel
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
TYPICAL ELECTRICAL CHARACTERISTICS
0.6
ID = 1.5 A
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
P−Channel
0.6
ID = 1 A
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.08
TJ = 25°C
0.07
VGS = 4.5
0.06
10 V
0.05
3.5
4
0.30
TJ = 25°C
0.25
VGS = 4.5 V
0.20
10 V
0.15
0.10
ID, DRAIN CURRENT (AMPS)
2.5
3
1.5
2
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
0
0.5
1
1.5
2.5
2
3
2.0
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
10
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 3. On−Resistance versus
Gate−To−Source Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
9
VGS = 10 V
ID = 1.5 A
1.5
1.0
0.5
0
−50
−25
0
25
50
75
100
125
150
0
0.5
1
1.6
VGS = 10 V
ID = 2 A
1.4
1.2
1.0
0.8
0.6
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 5. On−Resistance Variation with
Temperature
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4
150
MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
P−Channel
100
1000
VGS = 0 V
TJ = 125°C
10
1
I DSS , LEAKAGE (nA)
I DSS , LEAKAGE (nA)
VGS = 0 V
100°C
0
5
10
15
20
25
100°C
10
30
TJ = 125°C
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
5
10
15
20
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
Figure 6. Drain−To−Source Leakage
Current versus Voltage
30
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
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5
MMDF2C03HD
N−Channel
1200
P−Channel
1200
VDS = 0 V VGS = 0 V
Ciss
C, CAPACITANCE (pF)
800
600
Crss
Ciss
400
800
600 Crss
Ciss
400
Coss
Coss
200
200
Crss
Crss
0
10
5
0
10
15
20
25
5
10
15
20
25
30
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 7. Capacitance Variation
24
9
18
VGS
VDS
6
Q1
12
Q2
3
6
Q3
ID = 3 A
TJ = 25°C
2
4
6
8
10
0
12
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
24
QT
20
10
VGS
8
16
VDS
6
Q1
12
ID = 2 A
TJ = 25°C
Q2
8
4
4
2
Q3
0
0
2
4
6
8
10
12
14
0
16
Qg, TOTAL GATE CHARGE (nC)
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
1000
td(off)
tr
tf
td(on)
10
1
t, TIME (ns)
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25°C
100
t, TIME (ns)
0
VGS
QT
0
5
VDS
12
0
0
10
30
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS
5
TJ = 25°C
Ciss
1000
1000
C, CAPACITANCE (pF)
VDS = 0 V VGS = 0 V
TJ = 25°C
1
10
RG, GATE RESISTANCE (OHMS)
VDD = 15 V
ID = 2 A
VGS = 10 V
TJ = 25°C
100
tf
td(off)
tr
td(on)
10
1
100
1
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
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6
100
MMDF2C03HD
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
N−Channel
P−Channel
3.0
2
I S , SOURCE CURRENT (AMPS)
2.5
IS, SOURCE CURRENT (AMPS)
TJ = 25°C
VGS = 0 V
TJ = 25°C
VGS = 0 V
2.0
1.5
1.0
0.5
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
1.6
1.2
0.8
0.4
0
0.5
0.85
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 10. Diode Forward Voltage versus Current
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7
MMDF2C03HD
di/dt = 300 A/ms
Standard Cell Density
trr
I S , SOURCE CURRENT
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RqJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
N−Channel
P−Channel
10
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
10 ms
100 ms
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
100
10 ms
1
0.1
0.01
0.1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
1
10
10
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
100 ms
1 ms
10 ms
1
dc
0.1
0.01
0.1
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
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8
100
MMDF2C03HD
N−Channel
P−Channel
350
ID = 9 A
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
350
300
250
200
150
100
50
0
25
50
75
100
250
200
150
100
50
0
150
125
ID = 6 A
300
25
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
Normalized to qja at 10s.
Chip
0.0175 W
0.0710 W
0.2706 W
0.5776 W
0.7086 W
0.0154 F
0.0854 F
0.3074 F
1.7891 F
107.55 F
0.01
0.01
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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1.0E+01
1.0E+02
Ambient
1.0E+03
MMDF2C03HD
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MMDF2C03HD/D