Revised February 1999 MM74HC4060 14 Stage Binary Counter General Description The MM74HC4060 is a high speed binary ripple carry counter. These counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS. The MM74HC4060 is a 14-stage counter, which device increments on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. The MM74HC4060 also has two additional inputs to enable easy connection of either an RC or crystal oscillator. This device is pin equivalent to the CD4060. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground. Features ■ Typical propagation delay: 16 ns ■ Wide operating voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA maximum (74 Series) ■ Output drive capability: 10 LS-TTL loads Ordering Code: Order Number MM74HC4060M MM74HC4060SJ MM74HC4060MTC MM74HC4060N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 1999 Fairchild Semiconductor Corporation DS005354.prf www.fairchildsemi.com MM74HC4060 14 Stage Binary Counter August 1984 MM74HC4060 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (ICD) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (VIN, VOUT ) Operating Temperature Range (TA) 600 mW 500 mW Symbol VIH VIL VOH Parameter 0 VCC V −40 +85 °C 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics V Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units 6 (tr, tf) VCC = 2.0V Power Dissipation (PD) S.O. Package only Max 2 Input Rise or Fall Times −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) Note 3: Power Dissipation temperature derating: plastic “N” package: −12 mW/°C from 65°C to 85°C. (Note 4) Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH 2.0V 1.5 1.5 1.5 Level Voltage 4.5V 3.15 3.15 3.15 V (Not Applicable to Pins 9 & 10) 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V (Not Applicable to Pins 9 & 10) 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA Except Pins 9 & 10 V 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL Pins VIN = VIH or VIL 3.98 3.84 3.7 V 9 & 10 |IOUT| = 0.4 mA 5.48 5.34 5.2 V |IOUT| = 0.52 mA VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA Except Pins 9 & 10 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VIH or VIL Pins VIN = VIH or VIL 0.26 0.33 0.4 V 9 & 10 |IOUT| = 0.4 mA 0.26 0.33 0.4 V 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8.0 80 160 µA |IOUT| = 0.52 mA IIN Maximum Input Current VIN = VCC or GND ICC Maximum Quiescent VIN = VCCor GND Supply Current IOUT = 0 µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at V CC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC4060 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC4060 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter fMAX Maximum Clock Frequency tPHL, tPLH Maximum Propagation Conditions Guaranteed Typ (Note 5) Limit Units 30 MHz 40 20 ns 16 40 ns 10 20 ns 10 16 ns Delay to Q4 tPHL, tPLH Maximum Propagation Delay to any Q tREM Minimum Reset Removal Time tW Minimum Pulse Width AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions VCC TA = 25°C Typ Guaranteed Limits Units Maximum Operating 2.0V 6 5 4 MHz Frequency 4.5V 30 24 20 MHz MHz 6.0V tPHL, tPLH Maximum Propagation Delay Clock to Q4 tPHL TA = −40 to 85°C TA = −55 to 125°C 35 28 24 2.0V 120 380 475 171 ns 4.5V 42 76 95 114 ns ns 6.0V 35 65 81 97 Maximum Propagation 2.0V 72 240 302 358 ns Delay Reset to any Q 4.5V 24 48 60 72 ns 6.0V 20 ns 41 51 61 tPHL, tPLH Maximum Propagation 2.0V 125 156 188 ns Delay Between Stages 4.5V 25 31 38 ns tREM tW tr, tf Qn to Qn+1 6.0V 21 26 31 ns Minimum Reset 2.0V 100 125 150 ns Removal Time 4.5V 20 25 30 ns 6.0V 17 21 25 ns 2.0V 80 100 120 ns 4.5V 16 20 24 ns ns Minimum Pulse Width 6.0V 14 17 20 Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time 4.5V 500 500 500 ns ns 6.0V tTHL, tTLH Maximum Output Rise and Fall Time 400 400 400 2.0V 30 75 95 110 ns 4.5V 10 15 19 22 ns 9 13 16 19 6.0V CPD Power Dissipation (per package) 55 ns pF Capacitance (Note 6) CIN Maximum Input 5 10 10 10 pF Capacitance Note 5: Typical Propagation delay time to any output can be calculated using: tP = 17+12(N–1) ns; where N is the number of the output, QW, at VCC = 5V. Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 MM74HC4060 Timing Diagram 5 www.fairchildsemi.com MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com MM74HC4060 14 Stage Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.