HPLR3103, HPLU3103 Data Sheet 52A, 30V, 0.019 Ohm, N-Channel Logic Level, Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. December 2001 Features • Logic Level Gate Drive • 52A†, 30V • Low On-Resistance, rDS(ON) = 0.019Ω • UIS Rating Curve • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” † Calculated continuous current based on maximum allowable junction temperature. Package limited to 20A continuous, see Figure 9. Symbol Ordering Information D PART NUMBER PACKAGE BRAND HPLU3103 TO-251AA HP3103 HPLR3103 TO-252AA HP3103 G NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HPLR3103T. S Packaging JEDEC TO-251AA DRAIN (FLANGE) JEDEC TO-252AA SOURCE DRAIN GATE GATE DRAIN (FLANGE) SOURCE ©2001 Fairchild Semiconductor Corporation HPLR3103, HPLU3103 Rev. B HPLR3103, HPLU3103 Absolute Maximum Ratings TC = 25oC, Unless Othewise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Single Pulse Avalanche Energy (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg HPLR3103, HPLU3103 30 30 ±16V 52 390 240 89 0.71 -55 to 150 UNITS V V V A A mj W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 30 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - - V VDS = 30V, VGS = 0V - - 25 µA VDS = 24V, VGS = 0V, TC = 125oC - - 250 µA VGS = ±16V - - 100 nA - 0.037 - V ID = 28A, VGS = 10V - - 0.019 Ω ID = 23A, VGS = 4.5V - - 0.024 Ω VDD = 15V, ID ≅ 34A, RL = 0.441Ω, VGS = 4.5V, RGS =3.4Ω, Ig(REF) = 3mA - 9 - ns - 210 - ns td(OFF) - 20 - ns tf - 54 - ns VDD = 24V ID ≅ 34A, VGS = 4.5V (Figure 6) - - 50 nC - - 14 nC - - 28 nC VDS = 25V, VGS = 0V, f = 1MHz (Figure 5) - 1600 - pF - 640 - pF - 320 - pF - 7.5 - nH - 4.5 - nH Zero Gate Voltage Drain Current Gate to Source Leakage Current Breakdown Voltage Temperature Coefficient Drain to Source On Resistance (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time (Note 3) Fall Time IDSS IGSS ∆V(BR)DSS Reference to 25oC, ID = 1mA /∆TJ rDS(ON) td(ON) tr Total Gate Charge Qg Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) From Package to Center of Die Internal Drain Inductance LD Measured From the DrainLead, 6mm (0.25in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S ©2001 Fairchild Semiconductor Corporation HPLR3103, HPLU3103 Rev. B HPLR3103, HPLU3103 Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Thermal Resistance Junction to Case RθJC - - 1.4 oC/W Thermal Resistance Junction to Ambient RθJA - - 110 oC/W - - 50 oC/W MIN TYP MAX UNITS - - 52 (Note 1) A - - 220 A ISD = 28A - - 1.3 V trr ISD = 34A, dISD/dt = 100A/µs - 81 120 ns QRR ISD = 34A, dISD/dt = 100A/µs - 210 310 nC (PCB Mount Steady State) Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS ISD Pulsed Source to Drain Current (Note 2) MOSFET Symbol Showing The Integral Reverse P-N Junction Diode ISDM D G S Source to Drain Diode Voltage (Note 3) VSD Reverse Recovery Time (Note 3) Reverse Recovered Charge (Note 3) NOTES: 2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure 11). 3. Pulse width ≤ 300µs; duty cycle ≤ 2%. 4. VDD = 15V, starting TJ = 25oC, L = 300µH, RG = 25Ω, peak IAS = 34A, (Figure 10). Typical Performance Curves ID, DRAIN TO SOURCE CURRENT (A) VGS IN DECENDING ORDER 15V 12V 10V 8.0V 100 6.0V 4.0V 3.0V 2.5V 10 1 0.1 20µs PULSE WIDTH TC = 25oC 1.0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. OUTPUT CHARACTERISTICS ©2001 Fairchild Semiconductor Corporation 100 ID, DRAIN TO SOURCE CURRENT (A) 1000 1000 VGS IN DECENDING ORDER 15V 12V 10V 8.0V 100 6.0V 4.0V 3.0V 2.5V 10 1 0.1 20µs PULSE WIDTH TC = 150oC 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 2. OUTPUT CHARACTERISTICS HPLR3103, HPLU3103 Rev. B HPLR3103, HPLU3103 Typical Performance Curves (Continued) 2.5 VDS = 15V NORMALIZED DRAIN TO SOURCE 20µs PULSE WIDTH 100 TJ = 25oC TJ = 150oC 10 1.5 1.0 0.5 1 2 5 4 3 7 6 0 -80 9 8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 46A, VGS = 10V 2.0 ON RESISTANCE ID, DRAIN TO SOURCE CURRENT(A) 1000 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 3. TRANSFER CHARACTERISTICS 200 2400 2000 CISS 1600 1200 COSS 800 400 ID = 34A VGS, GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 160 20 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 2800 CRSS VDS = 24V 16 VDS = 15V 12 8 4 0 0 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 100 10 20 30 40 QG , TOTAL GATE CHARGE (nC) FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 6. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 1000 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 46A, VGS = 10V ID, DRAIN CURRENT (A) ISD, REVERSE DRAIN CURRENT(A) 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 4. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 3200 1000 -40 10µs 100 100 TJ = 175oC TJ = 25oC 10 0.4 0.8 1.2 1.6 2.0 2.4 2.8 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE ©2001 Fairchild Semiconductor Corporation 100µs OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 10ms VDSS MAX = 30V 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 8. FORWARD BIAS SAFE OPERATING AREA HPLR3103, HPLU3103 Rev. B HPLR3103, HPLU3103 Typical Performance Curves (Continued) 1000 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 60 45 If R = 0 tAV = (L)(IAS)/(1.3*RATED IASVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] EAS POINT 100 30 15 0 25 50 100 75 125 STARTING TJ = 25oC 10 1 150 TC, CASE TEMPERATURE (oC) FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE STARTING TJ = 150oC 0.001 0.01 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 100 FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 2 THERMAL IMPEDANCE ZθJC, NORMALIZED 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01Ω tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation FIGURE 13. UNCLAMPED ENERGY WAVEFORMS HPLR3103, HPLU3103 Rev. B HPLR3103, HPLU3103 Test Circuits and Waveforms (Continued) VDD VDS RL Qg(TOT) Qgd VGS Qgs VGS + VDD VDS DUT 0 IG(REF) IG(REF) 0 FIGURE 14. GATE CHARGE TEST CIRCUIT FIGURE 15. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS HPLR3103, HPLU3103 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4