ON JLC1562BN I2c bus i/o expander Datasheet

JLC1562B
I2C Bus I/O Expander
The JLC1562B facilitates easy I2C Bus expandibility. Multiple
devices (up to 8 on the same I2C Bus) are easily added as each device
has its own selectable 3−bit address. The JLC1562B provides an 8−bit
bidirectional input/output port and 6−bit resolution Digital to Analog
Converter. The voltage on pins P0−P4 is compared with a controllable
threshold voltage and the results are readable through the I2C Bus.
I2C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,
Serial Clock and Device Address respectively. External interface pins
are P0−P7 and VDAC; I/O Port and D/A output.
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MARKING
DIAGRAMS
PDIP−16
N SUFFIX
CASE 648
Features
•
•
•
•
•
•
•
•
•
Low Power Dissipation
I2C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
6−bit DAC
Bus Address Selectable (3−bit)
Address Input Pins are Pulled Up to VDD with Internal Resistor
I/O Pins are Open Drain Outputs
5 Comparators at Inputs
Inputs Protected from External Bus Currents in Power Down Mode
Pb−Free Packages are Available*
A0
1
16
VDD
A1
2
15
SDA
A2
3
14
SCL
P0
4
13
VDAC
P1
5
12
P7
P2
6
11
P6
P3
7
10
P5
VSS
8
9
P4
1
Chip Address Input
Comparator Input / Open Drain Output
P5−P7
Comparator Input / Open Drain Output
SCL
Serial Clock Input
SDA
I2C Data Output
VDAC
DAC Output
1
SOEIAJ−16
F SUFFIX
CASE 966
1
JLC1562B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
PIN LIST
P0−P4
JLC1562BN
AWLYYWWG
16
Device
Package
Shipping †
JLC1562BN
PDIP−16
25 Units/Tube
JLC1562BNG
PDIP−16
(Pb−Free)
25 Units/Tube
JLC1562BF
SOEIAJ−16
50 Units/Rail
JLC1562BFG
SOEIAJ−16
(Pb−Free)
50 Units/Rail
JLC1562BFEL
SOEIAJ−16
2000/Tape & Reel
JLC1562BFELG
SOEIAJ−16
(Pb−Free)
2000/Tape & Reel
Figure 1. Pin Assignment
A0−A2
16
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 5
1
Publication Order Number:
JLC1562B/D
JLC1562B
Power−On
Reset
P7
P6
P5
P4
P3
P2
P1
P0
SDA
Latch
6 Bit
Latch
6−Bit
DAC
VDAC
A0
A1
A2
Write Buffer
Shift Register (PISO) (SIPO)
VDD
I2C Bus Controller
8 Bit
SCL
1/2 VCC
3 Bit
5 Bit
Comp.
A
Latch
(C5−C7)
5 Bit
(C0−C4)
Comp.
B
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 VDD
and selects 1/2 VDD for Comparator “B” threshold.
Figure 2. Block Diagram
Pin 1
VDAC
VDD
16 X R65
Comparator “B”
Vref
R64
R63
Write Data (2)
Vref Selector
Bit D6 of Write Data (2)
R40
D6
Vref Value
1
Vref = VDAC
0
V + 40 V
ref
80 DD
R39
Write Data (2)
D5
D4
D3
D2
D1
D0
Vref
1
1
1
1
1
1
64 V
80 DD
R2
•
•
•
•
R1
•
•
•
•
GND
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
1LSB + 1 V
80 DD
0
0
0
0
0
1
0
0
0
0
0
0
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2
2 V
80 DD
1 V
80 DD
JLC1562B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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MAXIMUM RATINGS (Referenced to GND)
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
DC Input Voltage
–0.5 to Vdd +0.5
V
DC Output Voltage
–0.5 to Vdd +0.5
V
DC Input/Output Current (per Pin)
25
mA
IDD
DC Supply Current (VDD and GND Pins)
75
mA
Tstg
Storage Temperature Range
–65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
300
°C
Vdd
DC Supply Voltage
Vin
Vout
I
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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RECOMMENDED OPERATING CONDITIONS
Symbol
Vdd
Vin, Vout
TA
Parameter
Min
Max
Unit
DC Supply Voltage
4.2
6.0
V
DC Input Voltage
0.0
Vdd
V
Operating Temperature
–40
+85
°C
DC CHARACTERISTICS (Referenced to Vss)
Guaranteed Limit
Symbol
Parameter
Min
Max
Unit
VIH
Maximum Input Voltage, “H”
0.7 Vdd
−
V
VIL
Maximum Input Voltage, “L”
−
0.3 Vdd
V
VOL
Maximum Output Voltage, “L” (Iout = 4mA)
−
0.3
V
Iin
Maximum Input Leakage Current (Vin = Vdd or Vss, SCL pin only)
−
± 1.0
mA
Ioz
Maximum Output Hi−Z Leakage Current (Output = High Impedance; Vout = Vdd)
−
± 5.0
mA
Cin
Maximum Input Capacitance (Input Pin)
−
10
pF
Cout
Maximum Output Capacitance (Output Pin)
−
15
pF
Ci/o
Maximum I/O Capacitance (I/O Pin)
−
15
pF
VICR
Comparator Common Mode Input Voltage Range
0
Vdd −1.5
V
Maximum Quiescent Supply Current (per Package)
−
5.0
mA
ICC
COMPARATOR AC CHARACTERISTICS
Guaranteed Limit
Symbol
tPD
Parameter
Maximum Propagation Delay
Test Conditions
Min
Typ
Max
Unit
Vref = 1.5 V, 10mV overdrive
−
1.0
−
mS
Vref = 1.5 V, 100mV overdrive
−
0.2
−
mS
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3
JLC1562B
DA COMPARATOR CHARACTERISTICS
Guaranteed Limit
Symbol
Min
Parameter
Typ
Max
Unit
±1/4 LSB
DNL
DAC Referential NON−Linearity
eFS
DAC Full Scale Error
±1 LSB
eZC
DAC Zero Scale Error
±1 LSB
TIMING CHARACTERISTICS
Guaranteed Limit
Symbol
Parameter
Min
Max
Unit
fCL
SCL CLOCK Frequency
0
100
kHz
tBUF
BUS Free Time (Between “STOP” and “START”)
4.7
−
ms
HOLD Time for “START”
4.0
−
ms
tLOW
HOLD Time at SCL CLOCK LOW
4.7
−
ms
tHIGH
HOLD Time at SCL CLOCK HI
4.0
−
ms
−
ms
tHD:STA
tHD:DAT
DATA HOLD Time
0
tSU:DAT
DATA SETUP Time
250
−
ns
tR
Rise Time (SDA and SCL)
−
1000
ns
tF
Fall Time (SDA and SCL)
−
300
ns
tSU:STO
SETUP Time for “STOP”
4.0
−
ms
SDA
tBUF
tLOW
SCL
tHD:STA
tR
tF
tHD:DAT
tHIGH
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4
tSU:DAT
tSU:STO
JLC1562B
READ / WRITE MODES
SDA
I/O Expander
MODE
Master Device
Slave Device
I/O Port
READ
Receiver
Transmitter
Input
WRITE
Transmitter
Receiver
Output
SDA
SCL
Micro
Controller
I/O Expander
(Slave Device)
(Master Device)
SDA
SCL
P0 − P7
The JLC1562B Supports the following types of Bus Cycles
1.) WRITE MODE (A)
S
Slave Address & R/W
SACK
Write Data (1)
SACK
SACK
Write Data (1)
SACK Write Data (2)
SACK
Read Data
MACK
P
2.) WRITE MODE (B)
S
Slave Address & R/W
SACK
P
3.) READ MODE (A)
S
Slave Address & R/W
P
4.) READ MODE (B)
S
Slave Address & R/W
SACK
Read Data (1)
MACK
Read Data (2)
S
= START Condition
SACK = Slave Acknowledgement
MACK = Master Acknowledgement
P
= STOP Condition
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5
MACK Read Data (3)
MACK
P
JLC1562B
READ WRITE DATA FORMAT
<<READ MODE>>
S
0
1
1
1
A2
A1
A0
1
ACK D7
D6
D5
Slave Address
Slave Address
Read Data
D4 D3
D2
D1
D0 ACK
P
Read Data
A0 − A2
I/O Expander Device Address (Pins A0 − A2)
A3 − A6
A6
R/W
1 : READ ADDRESS
D5 − D7
Output of Comparator “A”. (Vth = 1/2 VDD)
D0 − D4
Output of Comparator “B”. (Vth = 1/2 VDD OR VDAC)
READ LATCH Bit Controls when Data Will Be Latched.
A5
A4
A3
is hard wired as
0
1
1
1
<<WRITE MODE>>
S
0
1
1
1
A2
A1
A0
0
ACK D7
D6
Slave Address
Slave Address
D5
D4 D3
D2
D1
D0 ACK D7
D6
Write Data (1)
D5
I/O Expander Device Address (Pins A0 − A2)
A3 − A6
A6
R/W
0 : WRITE ADDRESS
Write Data (1)
D0 − D7
Device Pins P0 to P7 Output Bits.
Write Data (2)
D7
READ LATCH CONTROL
A4
A3
D2
D1
Write Data (2)
A0 − A2
A5
D4 D3
is hard wired as
0
1
1
1
Latch Control of Signals C0 − C4
in the Device BLOCK DIAGRAM
0 : Data is latched at the ACK after a READ COMMAND.
1 : Data is latched when Comparator “B” switches from 0 to 1.
(switch point is controlled by Vth.)
1 : Data is reset at the ACK after a READ COMMAND.
D6
COMPARATOR “B” Vref Control Bit
0 : V + 40 V
ref
80 DD
1 : Vref + V
D0 − D5
DAC
DAC Input Bits
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6
D0 ACK
P
JLC1562B
<<WRITE MODE>>
1 2 3 4 5 6 7 8 9 1 2 3 4
5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
WRITE COMMAND
S 0
SDA
DATA (I)
DATA (II)
1 1 1 x x x 0 A
A
A P
Write_buffer
Latch Pulse
I/O Port
(P0 − P7)
DATA (I) valid
DAC
Latch Pulse
DATA (II) valid
DAC Latch
<<READ MODE>> (READ LATCH = 0)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
READ COMMAND
DATA (I) + (II)
S 0 1 1 1 x x x 1 A
SDA
A P
PISO
Load Pulse
Comp_out
(C0 − C4)
DATA (I)
Comp_out
(C5 − C7)
DATA (II)
<<READ MODE>> (READ LATCH = 1)
1 2 3 4 5 6 7 8 9
1 2 3 4
5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
WRITE DATA (II)
SDA
1
READ COMMAND
A P
S 0
DATA (I)
1 1 1 x x x 1 A
DAC Latch
D7 (READ LATCH Bit)
LATCH Reset
Comp._out
Latched Data
DATA (I)
PISO
Load Pulse
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7
A P
JLC1562B
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
D
M
J
G
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOEIAJ−16
CASE 966−01
ISSUE A
16
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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8
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10
0_
_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
JLC1562B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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JCL1562B/D
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