FAIRCHILD 74F398SC

Revised October 2000
74F398 • 74F399
Quad 2-Port Register
General Description
Features
The 74F398 and 74F399 are the logical equivalents of a
quad 2-input multiplexer feeding into four edge-triggered
flip-flops. A common Select input determines which of the
two 4-bit words is accepted. The selected data enters the
flip-flops on the rising edge of the clock. The 74F399 is the
16-pin version of the 74F398, with only the Q outputs of the
flip-flops available.
■ Select inputs from two data sources
■ Fully positive edge-triggered operation
■ Both true and complement outputs—74F398
Ordering Code:
Order Number
74F398SC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F398PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F399SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F399SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F399PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
74F398
© 2000 Fairchild Semiconductor Corporation
74F399
DS009533
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74F398 • 74F399 Quad 2-Port Register
April 1988
74F398 • 74F399
Logic Symbols
74F398
74F398
74F399
74F399
IEEE/IEC
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
Description
S
Common Select Input
1.0/1.0
20 µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
I0a–I0d
Data Inputs from Source 0
1.0/1.0
20 µA/−0.6 mA
I1a–I1d
Data Inputs from Source 1
1.0/1.0
20 µA/−0.6 mA
Qa–Qd
Register True Outputs
50/33.3
−1 mA/20 mA
Qa–Qd
Register Complementary Outputs (74F398)
50/33.3
−1 mA/20 mA
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2
Function Table
The 74F398 and 74F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources
(Ports) under control of a common Select input (S). The
selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-type output register is fully edgetriggered. The Data inputs (I0x, I1x) and Select input (S)
must be stable only a setup time prior to and hold time after
the LOW-to-HIGH transition of the Clock input for predictable operation. The 74F398 has both Q and Q outputs.
Inputs
S
Outputs
I0
I1
I
I
I
h
h
h
Q
Q
(Note 1)
X
L
H
X
H
L
X
I
L
H
X
h
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
X = Immaterial
Note 1: 74F398 only
Logic Diagram
*F398 Only
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F398 • 74F399
Functional Description
74F398 • 74F399
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150 °C
Ambient Temperature under Bias
−55°C to +125 °C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150 °C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL(mA)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
ESD Last Passing Voltage
(Min)—74F399
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
Output HIGH
Voltage
VOL
Output LOW
2.0
10% VCC
2.5
5% VCC
2.7
V
10% VCC
Voltage
IIH
Input HIGH Current
IBVI
Input HIGH Current
Breakdown Test
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
VCC
V
Circuit Current
Recognized as a LOW Signal
Min
Min
IIN = −18 mA
IOH = −1 mA
IOH = −1 mA
0.5
V
Min
IOL = 20 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
4.75
Output Leakage
Conditions
Recognized as a HIGH Signal
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V
−150
mA
Max
VOUT = 0V
All Other Pins Grounded
IIL
Input LOW Current
IOS
Output Short-Circuit Current
ICCH
Power Supply Current (74F398)
25
38
mA
Max
VO = HIGH
ICCL
Power Supply Current (74F398)
25
38
mA
Max
VO = LOW
ICCH
Power Supply Current (74F399)
22
34
mA
Max
VO = HIGH
ICCL
Power Supply Current (74F399)
22
34
mA
Max
VO = LOW
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−60
4
Symbol
Parameter
fMAX
Input Clock Frequency
tPLH
Propagation Delay
tPHL
CP to Q or Q
TA = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Typ
100
140
Max
Min
3.0 (Note 4)
5.7
7.5
3.0
8.5
3.0
6.8
9.0
3.0
10.0
Units
Max
100
MHz
ns
Note 4: 74F398 3.3 ns
AC Operating Requirements
TA = +25°C
Symbol
VCC = +5.0V
Parameter
Min
Max
TA = 0°C to +70°C
VCC = +5.0V
Min
tS(H)
Setup Time, HIGH or LOW
3.0
3.0
tS(L)
In to CP
3.0
3.0
tH(H)
Hold Time, HIGH or LOW
1.0
1.0
1.0
tH(L)
In to CP
1.0
tS(H)
Setup Time, HIGH or LOW
7.5
8.5
tS(L)
S to CP (F398)
7.5
8.5
tS(H)
Setup Time, HIGH or LOW
7.5
8.5
tS(L)
S to CP (F399)
7.5
8.5
tH(H)
Hold Time, HIGH or LOW
0
0
tH(L)
S to CP
0
0
tW(H)
CP Pulse Width
4.0
4.0
tW(L)
HIGH or LOW
5.0
5.0
5
Units
Max
ns
ns
ns
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74F398 • 74F399
AC Electrical Characteristics
74F398 • 74F399
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
74F398 • 74F399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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74F398 • 74F399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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8
74F398 • 74F399 Quad 2-Port Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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9
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