Mitsubishi M5M5V4R04J-15 4194304-bit (1048576-word by 4-bit) cmos static ram Datasheet

MITSUBISHI LSIs
M5M5V4R04J-12,-15
1997.11.20 Rev.F
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V4R04J is a family of 1048576-word by 4-bit static
PIN CONFIGURATION (TOP VIEW)
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M5V4R04J is offered in a 32-pin plastic small outline Jlead package(SOJ).
These device operate on a single 3.3V supply, and are directly
FEATURES
• Fast access time
M5M5V4R04J-12 •••• 12ns(max)
M5M5V4R04J-15 •••• 15ns(max)
• Low power dissipation
Active •••••••••• 297mW(typ)
Stand by ••••••• 3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
APPLICATION
High-speed memory units
BLOCK DIAGRAM
A3
3
4
A4 5
A5 12
A6 13
A7 14
A8 15
S
W
6
11
3
30
4
29
5
28
6
7
8
9
10
11
12
27
26
25
24
23
22
21
13
20
14
19
15
18
16
17
Outline
A19
A18
address
A17
inputs
A16
A15
output enable
OE input
DQ4 data inputs/
GND (0V) outputs
VCC (3.3V)
DQ3 data inputs/
outputs
A14
A13
address
A12
inputs
A11
A10
NC
32P0K(SOJ)
7
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
COLUMN ADDRESS
COLUMN
DECODERS
ADDRESS
DECODERS
COLUMN INPUT BUFFERS
OE 27
OUTPUT BUFFERS
2
31
DATA INPUT BUFFERS
A1
A2
32
2
PACKAGE
32pin 400mil SOJ
ROW ADDRESS DECODERS
1
ROW INPUT BUFFERS
address
inputs
A0
1
M5M5V4R04J
TTL compatible. They include a power down feature as well.
A0
A1
address
A2
inputs
A3
A4
chip select
S
input
data inputs/ DQ 1
outputs(3.3V)
VCC
(0V) GND
data inputs/
DQ2
outputs
write control W
input
A5
A6
address
A7
inputs
A8
A9
DQ1
10
DQ2
23
DQ3
26
DQ4
data
inputs/
outputs
8
24
9
25
VCC (3.3V)
GND (0V)
16 18 19 20 21 22 28 29 30 31 32
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
address
inputs
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V4R04J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are
disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
FUNCTION TABLE
S
H
W
X
OE
X
Mode
Non selection
DQ
High-impedance
Icc
Stand by
L
L
X
Write
Din
L
H
L
Read
Dout
Active
Active
L
H
H
High-impedance
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
V cc
VI
Parameter
Conditions
Ratings
Supply voltage
-2.0 ~ 4.6
Input voltage
VO
Output voltage
Pd
Power dissipation
T opr
Operating temperature
Unit
*
With respect to GND
V
*
V
*
-2.0 ~ VCC+0.5
V
1000
mW
-2.0 ~ VCC+0.5
Ta=25 C
0 ~ 70
C
Tstg(bias) Storage temperature (bias)
-10 ~ 85
C
T stg
-65 ~ 150
C
Storage temperature
*Pulse width ≤ 20ns, In case of DC:-0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V
Symbol
VIH
VIL
VOH
VOL
II
unless otherwise noted)
Limits
Condition
Parameter
Min
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
I OZ
IOH =-4mA
IOL= 8mA
V I = 0~Vcc
VI (S)= V IH
Output current in off-state
VO= 0~Vcc
I CC1
Active supply current
(TTL level)
I CC2
+10%
-5%
Typ
Stand by current
(TTL level)
VI (S)= VIH
Stand by current
VI (S)= Vcc≥0.2V
other inputs V I≤0.2V
or VI≥Vcc-0.2V
AC
AC
10
µA
160
15ns cycle
150
90
mA
100
12ns cycle
75
15ns cycle
70
DC
I CC3
0.4
2
12ns cycle
DC
Unit
V
V
V
V
µA
Vcc+0.3
0.8
2.0
-0.3
2.4
VI (S)= VIL
other inputs V IH or VIL
Output-open(duty 100%)
Max
mA
50
1
10
mA
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0 ~ 70 C, Vcc=3.3V
Symbol
+10%
-5%
unless otherwise noted)
Parameter
Test Condition
Min
Limit
Typ
Max
Unit
CI
Input capacitance
V I =GND, V I =25mVrms,f=1MHz
7
pF
CO
Output capacitance
V O=GND, VO =25mVrms,f=1MHz
8
pF
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=5V,Ta=25 C
3: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS
(Ta=0 ~ 70 C, Vcc=3.3V
+10%
-5%
unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels •••••••••••••••••••••••• V IH =3.0V, V IL =0.0V
Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns
Input timing reference levels •••••••••••• V IH =1.5V, V IL=1.5V
Output timing reference levels •••••••••• V OH=1.5V, V OL =1.5V
Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1 ,Fig2
Vcc
OUTPUT
Z0=50Ω
480Ω
DQ
255Ω
RL=50Ω
5pF
(including
scope and JIG)
VL=1.5V
Fig.1 Output load
Fig.2 Output load for t en, t
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(2)READ CYCLE
Limits
M5M5V4R04J -12
Parameter
Symbol
Min
M5M5V4R04J -15
Max
Min
Unit
Max
tCR
Read cycle time
ta (A)
Address access time
12
15
ns
ta(S)
Chip select access time
12
15
ns
ta (OE)
Output enable access time
6
8
ns
tdis(S)
Output disable time after S high
0
6
0
7
ns
tdis (OE)
Output disable time after OE high
0
6
0
7
ns
ten (S)
Output enable time after S low
0
0
ns
ten (OE)
Output enable time after OE low
0
0
ns
tv(A)
Data valid time after address change
3
3
ns
tPU
Power-up time after chip selection
0
0
ns
tPD
Power-down time after chip selection
15
12
12
ns
15
ns
(3)WRITE CYCLE
Limits
M5M5V4R04J -12
Parameter
Symbol
Min
Max
M5M5V4R04J -15
Min
Unit
Max
t CW
Write cycle time
12
15
ns
tw(W)
Write pulse width
10
12
ns
tsu (A)1
Address setup time(W)
0
0
ns
tsu (A)2
Address setup time(S)
0
0
ns
tsu (S)
Chip select setup time
10
12
ns
tsu (D)
Data setup time
6
7
ns
th (D)
Data hold time
0
0
ns
trec(W)
Write recovery time
1
1
ns
tdis (W)
Output disable time after W low
0
6
0
7
ns
tdis (OE)
Output disable time after OE high
0
6
0
7
ns
ten (W)
Output enable time after W high
0
0
ns
ten (OE)
Output enable time after OE low
0
0
ns
tsu(A-WH)
Address to W High
10
12
ns
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M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~19
t CR
VIH
VIL
ta (A)
tv (A)
tv (A)
DQ1~4
VOH
PREVIOUS DATA VALID
VOL
UNKNOWN
DATA VALID
W=H
S=L
OE=L
Read cycle 2 (Note 4)
t CR
VIH
S
VIL
tdis (S)
ta(S)
(Note 5)
ten (S)
DQ1~4
(Note 5)
VOH
UNKNOWN
DATA VALID
VOL
tPU
tPD
ICC1
Icc
50%
ICC2
50%
W=H
OE=L
Note 4. Addresses valid prior to or coincident with S transition low.
5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6)
t CR
VIH
OE
VIL
ta (OE)
(Note 5)
DQ1~4
VOH
tdis (OE)
(Note 5)
ten (OE)
UNKNOWN
DATA VALID
VOL
W=H
S=L
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
Write cycle ( W control mode )
t CW
A 0~19
S
VIH
VIL
tsu (S)
VIH
VIL
(Note7)
(Note7)
tsu (A-WH)
OE
VIH
VIL
tsu (A)
W
tw (W)
trec (W)
VIH
VIL
tsu (D) th(D)
DQ1~4
(Input Data)
VIH
DATA STABLE
VIL
tdis(W) (Note 5)
ten (OE) (Note 5)
ten (W)
tdis(OE)
DQ1~4
(Output Data)
VOH
VOL
Hi-Z
Write cycle (S control mode )
t CW
A 0~19
VIH
VIL
tsu (A)
tsu (S)
trec (W)
VIH
S
VIL
tw(W)
VIH
W
VIL
(Note7)
(Note7)
tsu (D)
DQ1~4
VIH
(Input Data)
VIL
th (D)
DATA STABLE
tdis (W)
ten (S)
DQ1~4
(Output Data)
VOH
(Note5)
(Note5)
Hi-Z
VOL
(Note8)
Note 7: Hatching indicates the state is don't care.
8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.
9: t en,tdis are periodically sampled and are not 100% tested.
MITSUBISHI
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