Renesas M66312FP 8-bit led driver with shift register and latched 3-state output Datasheet

M66312P/FP
8-Bit LED Driver with Shift Register and Latched 3-State Outputs
REJ03F0178-0201
Rev.2.01
Mar 31, 2008
Description
M66312 is a LED array driver having a 8-bit serial input and parallel output shiftregister function with 3-state output
latch.
This product guarantees the output electric current of 16 mA which is sufficient for LED drive, capable of flowing 8
bits continuously at the same time, and use either of cathode common LED and anode common LED.
In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when
compared with conventional BIPOLAR or Bi-CMOS products.
Features
• High output current IOL = 16 mA, IOH = −16 mA
• High speed (clock frequency): 30 MHz (typ)
(CL = 50 pF, VCC = 5 V)
• Low power dissipation: 20 µW/package (max)
(VCC = 5 V, Ta = 25°C, quiescent state)
• 3-state output (except serial data output)
• Wide operating temperature range: Ta = −40 to +85°C
Application
LED array drive of PRINTER
LED array drive of BUTTON TELEPHONE
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 1 of 8
M66312P/FP
Block Diagram
Serial data
output
Parallel data outputs
13
12
OE
CKL
QA
QB
QC
QD
QE
QF
QG
QH
SQH
VCC
15
1
2
3
4
5
6
7
9
16
0
CK
D
0
CK
D
0
CK
D
0
CK
D
0
CK
D
0
CK
D
0
CK
D
0
CK
D
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
14
11
10
8
A
CKS
R
GND
Shift
clock
input
Direct
reset
input
Output Latch Serial
enable clock data
input input input
Pin Arrangement
M66312P/FP
QB ← 1
Parallel data
outputs
16
QC ← 2
QC
QB Q
A
QD ← 3
QD
A
QE ← 4
QE
QF ← 5
VCC
15 → QA
Parallel data output
14 ← A
Serial data input
OE
13 ← OE
Output enable input
QF
CKL
12 ← CKL
Latch clock input
QG ← 6
QG
CKS
11 ← CKS
Shift clock input
QH ← 7
QH SQ R
H
10 ← R
Direct reset input
GND
8
9
→ SQH Serial data output
(Top view)
Outline: PRDP0016AA-A (16P4)
PRSP0016DE-A (16P2N-A)
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 2 of 8
M66312P/FP
Functional Description
As M66312 uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive
while maintaining low power consumption and allowance for high noises.
Each bit of a shiftregister consists of two flip-flops having independent clocks for shifting and latching.
As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch
operations being made when “L” changes to “H”.
Serial data input A is the data input of the first-step shiftregister and the signal of A shifts shiting registers one by one
when a pulse is impressed to CKS. When A is “H”, the signal of “H” shifts. When A is “L”, the signal of “L” shifts.
When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register,
and they appear in the output from QA through QH are 3-state outputs.
To extend the number of bits, serial data output SQH is used to output the 8-bit of the shift register.
By connecting CKS and CKL, the shift register state delayed by 1 clock cycle is output at QA through QH.
When reset input R is low, shift register and SQH will be reset. To reset QA through QH to low-level, CKL must be
changed from low-level to high-level after the shift register is reset by R.
When output-enable input OE is high, QA through QH will become high impedance state, but SQH is not changed.
Even if OE is changed, shift operation is not affected.
Function Table (Note)
Input
Parallel Data Output
Serial Data
Output SQH
R
CKS
CKL
A
OE
QA
QB
QC
QD
QE
QF
QG
QH
Shift t1
L
X
X
X
L
QA0
QB0
QC0
QD0
QE0
QF0
QG0
QH0
Latch t2
X
X
↑
X
L
L
L
L
L
L
L
L
L
L
Shift
Shift t1
H
↑
X
H
L
QA0
QB0
QC0
QD0
QE0
QF0
QG0
QH0
qG0
latch
Latch t2
H
X
↑
X
L
H
qA0
qB0
qC0
qD0
qE0
qF0
qG0
qG0
H
↑
X
L
L
QA0
QB0
QC0
QD0
QE0
QF0
QG0
QH0
qG0
H
X
↑
X
L
L
qA
0
qB
0
qC
0
qD
0
qE
0
qF
0
qG
0
qG0
X
X
X
X
H
Z
Z
Z
Z
Z
Z
Z
Z
qH
Operation Mode
Reset
operation Shift t1
Latch t2
3 state
Note
↑: Change from low-level to high-level
0
Q : Output state Q before CKL changed
X: Irrelevant
0
q : Contents of shift register before CKS changed
q: Contents of shift register
t1, t2: t2 is set after t1 is set
Z: High impedance
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 3 of 8
L
M66312P/FP
Absolute Maximum Ratings
(Ta = −40 to +85°C, unless otherwise noted)
Item
Supply voltage
Input voltage
Output voltage
Input protection diode current
Symbol
VCC
VI
VO
IIK
Output parasitic diode current
IOK
Output current per output pin
QA to QH
SQH
IO
Supply/GND current
Power dissipation
Storage temperature range
Note:
ICC
Pd
Tstg
Ratings
−0.5 to +7.0
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
−20
20
−20
20
±35
±25
±132
500
−65 to +150
Unit
V
V
V
mA
mA
Conditions
VI < 0 V
VI > VCC
VO < 0 V
VO > VCC
mA
mA
mW
°C
VCC, GND
(Note)
M66312FP; Ta = −40 to +70°C, Ta = 70 to 85°C are derated at −6 mW/°C.
Recommended Operating Conditions
(Ta = −40 to +85°C, unless otherwise noted)
Item
Supply voltage
Input voltage
Output voltage
Operating temperature range
Input rising and falling time VCC = 4.5 V
VCC = 5.5 V
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 4 of 8
Symbol
VCC
VI
VO
Topr
tr, tf
Min
Limits
Typ
Max
Unit
4.5
0
0
−40
0
0
5
—
—
—
—
—
5.5
VCC
VCC
+85
500
400
V
V
V
°C
ns
M66312P/FP
Electrical Characteristics
(VCC = 4.5 to 5.5V, unless otherwise noted)
Limits
Item
Sym
bol
High-level input
voltage
VIH
Low-level Input
voltage
VIL
High-level output
voltage
VOH
Ta = 25°C
Ta = −40 to +85°C
Min
Typ
Max
Min
Max
Unit
0.70× VCC
—
—
0.70×VCC
—
V
Conditions
VO = 0.1 V, VCC−0.1 V
IO = 20 µA
—
—
0.30×VCC
—
0.30×VCC
V
VO = 0.1 V, VCC−0.1 V
IO = 20 µA
VCC−0.1
—
—
VCC−0.1
—
3.70(note)
—
—
3.55(note)
—
VCC−0.1
—
—
VCC−0.1
—
V
VI = VIH, VIL
IOH = −20 µA
VCC = 4.5 V
IOH = −16 mA
VI = VIH, VIL
IOH = −20 µA
VCC = 4.5 V
IOH = −4 mA
VI = VIH, VIL
IOL = 20 µA
VCC = 4.5 V
IOL = 16 mA
QA to QH
High-level output
voltage SQH
VOH
Low-level output
voltage QA to QH
VOL
Low-level output
voltage SQH
VOL
High-level input
current
4.0
—
—
3.9
—
—
—
0.1
—
0.1
(note)
V
(note)
—
—
—
—
0.1
—
0.1
—
—
0.4
—
0.5
IIH
—
—
0.1
—
1.0
µA
VI = VCC, VCC = 5.5 V
Low-level input
current
IIL
—
—
−0.1
—
−1.0
µA
VI = GND, VCC = 5.5 V
Off state highlevel output
current QA to QH
IOZH
—
—
1.0
—
10.0
µA
VI = VIH, VIL
Off state lowlevel output
current QA to QH
IOZL
—
—
−1.0
—
−10.0
µA
Quiescent supply
current
ICC
—
—
4.0
—
40.0
µA
Note:
0.7
V
—
0.85
V
VI = VIH, VIL
IOL = 20 µA
VCC = 4.5 V
IOL = 4 mA
VO = VCC
VCC = 5.5 V
Limits of single PIN operating state
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 5 of 8
VO = GND
VI = VCC, GND, VCC = 5.5 V
M66312P/FP
Switching Characteristics
(VCC = 5 V)
Limits
Min
Ta = 25°C
Typ
Max
fmax
tPLH
tPHL
15
—
—
—
—
—
—
70
70
12
—
—
High-level to low-level
output propagation time RSQH
tPHL
—
—
60
Low-level to high-level and
high-level to low-level
output propagation time
CKL-QA to QH
tPLH
tPHL
—
—
—
—
Output disable time from
low-level and high-level
OE-QA to QH
tPLZ
tPHZ
—
—
Output enable time to lowlevel and high-level OE-QA
to QH
tPZL
tPZH
Item
Symbol
Maximum clock frequency
Low-level to high-level and
high-level to low-level
output propagation time
CKS-SQH
Note:
Ta = −40 to +85°C
Min
Max
Unit
Conditions
—
88
88
MHz
ns
ns
CL = 15 pF
—
76
ns
60
60
—
—
76
76
ns
ns
CL =
(Note)
—
—
50
50
—
—
64
64
ns
ns
CL = 5 pF
—
—
56
—
70
ns
CL = 50 pF
—
—
56
—
70
ns
CL = 50 pF
(Note)
50 pF
(Note)
(Note)
Test Circuit
VCC
Input
Output
VCC
RL = 1 kΩ
SW1
PG
DUT
SW2
50 Ω
CL
GND
RL = 1 kΩ
Item
SW1
SW2
tPLH, tPHL
Open
Open
tPLZ
Close
Open
tPHZ
Open
Close
tPZL
Close
Open
tPZH
Open
Close
(1) The pulse generator (PG) has the following characteristics (10% to 90%): tr = 6 ns, tf = 6 ns
(2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
Timing Requirements
(VCC = 5 V)
Limits
Item
Symbol
Min
Ta = 25°C
Typ
Max
Ta = −40 to +85°C
Min
Max
—
—
—
—
40
50
—
—
ns
ns
Unit
CKS, CKL, R pulse width
tw
A setup time with respect to
CKS
tsu
32
40
CKS setup time with respect
to CKL
tsu
40
—
—
50
—
ns
A hold time with respect to
CKS
th
10
—
—
10
—
ns
R recovery time with
respect to CKS
trec
20
—
—
26
—
ns
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 6 of 8
Conditions
M66312P/FP
Timing Chart
tw
VCC
CKS
50%
50%
50%
tPLH
tPHL
VCC
CKL
50%
GND
GND
tPLH
VOH
SQH
VOH
QA to QH
50%
50%
50%
VOL
VOH
tw
VCC
R
VOL
tPHL
50%
50%
trec
50%
QA to QH
VOL
GND
VCC
CKS
VCC
50%
A
50%
50%
GND
tPHL
GND
tsu
th
VOH
50%
SQH
VCC
CKS
VOL
50%
GND
VCC
OE
50%
50%
tPZL
tPLZ
GND
CKS
50%
QA to QH
tPZH
QA to QH
10%
tPHZ
50%
90%
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 7 of 8
tsu
VOL
VOH
VCC
50%
CKL
GND
tw
VCC
50%
50%
GND
M66312P/FP
Package Dimensions
RENESAS Code
PRDP0016AA-A
Previous Code
16P4
MASS[Typ.]
1.0g
9
1
8
c
*1
E
16
e1
JEITA Package Code
P-DIP16-6.3x19-2.54
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
e1
D
E
A
A1
A2
bp
b2
b3
c
L
A1
A
A2
Reference
Symbol
*3
e
*3
bp
b3
b2
SEATING PLANE
e
L
JEITA Package Code
P-SOP16-5.3x10.1-1.27
RENESAS Code
PRSP0016DE-A
Previous Code
16P2N-A
Min
7.32
18.8
6.15
Nom
7.62
19.0
6.3
Max
7.92
19.2
6.45
4.5
0.51
0.4
0.9
1.4
0.22
0°
2.29
3.0
3.3
0.5
1.0
1.5
0.27
2.54
0.6
1.3
1.8
0.34
15°
2.79
MASS[Typ.]
0.2g
E
9
*1
HE
16
Dimension in Millimeters
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
8
Index mark
A2
A1
c
D
Reference
Symbol
L
A
*2
e
y
*3
bp
Detail F
D
E
A2
A1
A
bp
c
HE
e
y
L
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Page 8 of 8
Dimension in Millimeters
Min Nom Max
10.0 10.1 10.2
5.2 5.3 5.4
1.8
0.1 0.2
0
2.1
0.35 0.4 0.5
0.18 0.2 0.25
0°
8°
7.5 7.8 8.1
1.12 1.27 1.42
0.1
0.4 0.6 0.8
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