NCP4331 Advance Information Synchronous Buck Controller for High Efficiency Post Regulation http://onsemi.com The NCP4331 houses a dual MOSFET driver intended to be used as a companion chip in ac-dc or dc-dc multi-output post regulated power supplies. Directly fed by the secondary ac signal, the device keeps power dissipation to the lowest while reducing external component count. Further, the implementation of N-channel MOSFETs gives NCP4331-based applications a significant advantage in terms of efficiency. MARKING DIAGRAMS 16 16 1 Features •High Gate Drive Capability •Bootstrap for N-MOSFET High-Side Drive •Two Embedded Error Amplifiers Allowing Constant Current Constant Voltage (CCCV) Operation •±1.5% Regulation Voltage Reference Over 0°C to 85°C Temperature Range •Programmable Soft-Start •Thermal Shutdown for Overtemperature Protection •PWM Operation Synchronized to the Converter Frequency •Over-Lap Management for Soft Switching •Internal Regulator to Ease the Circuit Feeding •Undervoltage Detection •These are Pb-Free Devices Typical Applications •Off-line Switch Mode Power Supplies •Power Dc-dc Converters •Efficient Alternative to Mag-Amp Post-Regulators NCP4331G ALYYWW SO-16 D SUFFIX CASE 751B 1 16 16 NCP 4331 ALYWG G 1 TSSOP-16 DB SUFFIX 1 CASE 948F A = Assembly Location L = Wafer Lot YY = Year WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS CSout 1 16 VCC CSin- 2 15 BST CSin+ 3 14 HS_DRV UVP/STDWN 4 13 HB COMP 5 12 VDD FB 6 11 LS_DRV SS/Dmax 7 10 GND Cramp 8 9 SYNC (Top View) ORDERING INFORMATION This document contains information on a new product. Specifications and information herein are subject to change without notice. Device Package Shipping NCP4331DR2G SOIC-16 (Pb-Free) 2500 / Tape & Reel NCP4331DBR2G TSSOP-16 (Pb-Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2007 October, 2007 - Rev. P1 1 Publication Order Number: NCP4331/D NCP4331 Vin Vout1 VIN_FORWARD + LOAD1 Regulation Block Ruvp1 VCC 1 CSout VCC 16 2 CSin- BST 15 3 CSin+ HS_ DRV 14 4 UVP 5 COMP HB 13 Vout2 L VDD 12 FB Ruvp2 Forward Driver (e.g. NCP1280) Rsync 6 FB LS_ DRV 11 7 SS GND 10 8 Cramp SYNC + LOAD2 9 FB Figure 1. Typical Application Schematic http://onsemi.com 2 NCP4331 VCC BST + + VsyncH / VsyncL Q Level Shifter R Delay HS-DRV + S - - SYNC Fault HB 7.5 V COMP VDD RESET Fault ERROR AMPLIFIER 100 ns Delay - FB R PWM Latch VDD + + Vref + + S + Vpwm (3 V) ISS Q LS-DRV RESET dominant Q high to turn on HS_DRV Q low to turn off HS_DRV GND + Iramp Soft-Start VDD Bandgap Vref Fault Iuvp Fault SW2 VDD CSout + CSin+ Thermal Shutdown RESET Fault Auxiliary OPAMP (SINK Only) UVP / STDWN + CSin- UVLO + Vuvp SW2 prevents Iuvp from being sourced when an UVP is detected (programmable hysteresis) Cramp Figure 2. Block Diagram http://onsemi.com 3 NCP4331 DETAILED PIN DESCRIPTIONS Pin Number Name Function 1 CSout Pin 1 is the output of the auxiliary error amplifier embedded in the NCP4331. This allows for the prevention of excessive coil or load current. Pin 1 can clamp the main error amplifier output. Controlling the coil current by this auxiliary error amplifier can provide a CCCV characteristic. 2 CSin- Inverting input of the auxiliary error amplifier that is generally used to control the coil current. 3 CSin+ Noninverting input of the auxiliary error amplifier that is generally used to control the coil current. 4 UVP/ STDWN 5 COMP 6 FB Pin 6 is the feed-back pin that must receive a portion of the output voltage to regulate. It is connected to the inverting input of the internal error amplifier. The regulation reference is better $2% over the -40°C to 125°C temperature range. 7 Soft-Start/ Dmax Apply a capacitor to Pin 7 to slow down the start-up phase and reduce the stress during this sequence. Place a resistor between Pin 7 and ground to adjust the maximum duty-cycle of the high-side MOSFET. Combine the two functions by implementing these two components in parallel. 8 Cramp This pin sources a constant current. Connect a capacitor to create a voltage ramp. This ramp is summed to the error amplifier output and compared to a constant voltage reference (VPWM) to adjust the post-regulator duty-cycle. 9 SYNC This pin is designed to receive a portion of the input voltage, to synchronize the post-regulator activity to its pulsed input voltage. Also, the high-side drive cannot be high state if the “SYNC” pin voltage is low. 10 GND Ground pin of the circuit. 11 LS_DRV 12 VDD This pin is designed to detect too low input voltage pulses and to turn off both the low-side and high-side drivers in such a faulty condition. Also, the soft-start pin is grounded so that the circuit smoothly recovers operation when the detected fault disappears. This UVP detection function features some programmable hysteresis to avoid erratic turns on and off of the device. Ground Pin 4 to shutdown the part. This pin makes available the output of the internal error amplifier, for appropriate compensation of the regulation loop. ”LS_DRV“ is the driver output of the low-side MOSFET gate. “VDD” is the circuit power source that is typically provided by the VCC Pin. A 0.1 mF to 1 mF ceramic capacitor should be connected between this pin and ground for decoupling. 13 HB 14 HS_DRV Connect the common node of the two MOSFETs to this pin. 15 BST “BST” is the bootstrap pin. A 0.1 mF to 1 mF ceramic capacitor should be connected between this pin and the “HB” node. The “BST” voltage feeds the high-side driver (“HS_DRV”). 16 VCC A DC voltage (up to 30 V) must be applied to this pin. This voltage is internally post-regulated down to 7.5 V to provide the VDD voltage that powers the circuit. “HS_DRV” is the driver output of the high-side MOSFET gate. http://onsemi.com 4 NCP4331 MAXIMUM RATINGS Symbol Value Unit -2, +40 V Bootstrap Pin Voltage Referenced to the HB Node -0.3, +10 V VCC Internal Regulator Input -0.3, +30 V Vin Pins 1, 2, 3, 4, 5, 6, 7, 8 and 9 -0.3, +5 V VDD Supply Voltage -0.3, +10 V RqJA Thermal Resistance (TSSOP-16 and SOIC-16) 145 °C/W 2 kV 200 V -40, +125 °C 150 °C -65 to 150 °C BST, HB BSTHB Rating Bootstrap and “Half-Bridge” Node Inputs (Referenced to GND) ESD Capability, Human Body Model (HBM) ESD Capability, Machine Model (MM) (Note 2) TA Operating Temperature Range (Note 1) TJmax Maximum Junction Temperature TSmax Storage Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum junction temperature should not be exceeded. 2. The Machine Model ESD capability is 150 V for Pin 9. ELECTRICAL CHARACTERISTICS (VCC = 20 V, VBST = 7 V, HB Grounded, TJ = 0°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit Source Resistance @ Isource = 100 mA - 3 6 W Sink Resistance @ Isink = 100 mA - 2 4 W Rise and Fall Times: High-Side Output Voltage Rise Time (CL = 1 nF) (Note 3) High-Side Output Voltage Fall Time (CL = 1 nF) (Note 3) - 13 8 20 15 35 55 75 ns Source Resistance @ Isource = 100 mA - 3 6 W Sink Resistance @ Isink = 100 mA - 2 4 W Rise and Fall Times: High-Side Output Voltage Rise Time (CL = 1 nF) (Note 3) High-Side Output Voltage Fall Time (CL = 1 nF) (Note 3) - 13 8 20 15 HIGH-SIDE OUTPUT STAGE RHS_source RHS_sink tr-HS tf-HS TLS-HS Delay from Low-Side Gate Drive Low (High) to High-Side Drive High (Low) (Note 6) ns LOW-SIDE OUTPUT STAGE RLS_source RLS_sink tr-LS tf-LS ns CURRENT CONTROL ERROR AMPLIFIER (Auxiliary Error Amplifier) IBpin3 Noninverting Input Bias Current @ Vpin3 = Vpin2 = Vref -500 -100 0 nA IBpin2 Inverting Input Bias Current @ Vpin3 = Vpin2 = Vref -500 -100 0 nA Vio Input Offset Voltage (Note 5) -5 1 5 mV BW Gain Bandwidth - 4 - MHz GEA Open Loop Voltage Gain - 70 - dB VLL Pin 1 Voltage if Vpin2 = 1 V and Vpin3 = 0 V, 100 mA Being Sourced Into Pin 1 0 - 0.5 V 3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design. 4. Guaranteed by design. Tested through the RRESET parameter. 5. Guaranteed by characterization and design. 6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically http://onsemi.com 5 NCP4331 ELECTRICAL CHARACTERISTICS (VCC = 20 V, VBST = 7 V, HB Grounded, TJ = 0°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit Referenced Voltage Regulation @ Pin 7 Being Open 0°C < TJ < 85°C -40°C < TJ < 125°C (Guaranteed by Test from 0°C < TJ < 125°C and Extended to -40°C by Design) 0.738 0.735 0.750 0.750 0.762 0.765 IBFB Feedback Input Bias Current @ Vpin6 = Vref -500 -250 0 nA BW Gain Bandwidth - 4 - MHz GEA Open Loop Voltage Gain - 70 - dB 3.50 - 3.70 0.05 0.50 40 65 90 mA ERROR AMPLIFIER Vref EAout -EAmax -EAmin Isource-EA Pin 5 (Compensation) Voltage Vpin6 = 0 V Vpin6 = 1 V V V Output Source Current @ Vpin6 = 0 V SOFT-START AND MAXIMUM DUTY-CYCLE LIMITATION (Dmax) ISS Source Current @ VSS = 0 V to 3.5 V 40 50 63 mA VSS Clamp Voltage 3.5 3.7 - V - 0.05 0.5 V 1.9 2.0 2.1 V Cramp Current Source @ Vramp = 0 V to 3.5 V 40 50 63 mA VrampH Cramp Ramp Clamp 3.5 3.7 - V VrampL Low Voltage of the Ramp Saw-Tooth - - 100 mV 2.30 0.80 2.50 1.00 2.65 0 1.20 EAMIN Error Amplifier Output @ Vpin5 = 0.5 V EASS Error Amplifier Output @ Vpin6 = 0 V and Vpin7 = 2 V RAMP CONTROL Iramp VrampON Ramp Voltage Enabling the High-Side Driver: @Vpin5 = 0.5 V @ Vpin5 = 3.5 V (Min Highest EA Value) @ Vpin5 = 2 V V QRESET Current Charge Extracted During the RESET Pulse (Note 4) 5 - - nC TRESET Delay from SYNC Pin low to Reset Completion (a Falling Pulse Being Applied to Pin 16) - 200 350 ns RRESET Sink Resistance of Pin 8 during the Reset Time @ Ipin8 = 10 mA (This is the Resistance of the Switch that Discharges the Cramp Capacitor during the Reset Pulse - Capability of 5 nC Min) - 15 25 W Synchronization Comparator Threshold (Vpin9 Rising) 2.4 2.5 2.6 V Synchronization Comparator Hysteresis 1.2 1.5 1.8 V VCL-SYNC Negative Clamp Voltage of the Synchronization Pin @ Ipin16 = 2 mA -0.3 - 0 TSYNCwHS Delay From SYNC Pin High to HS_DRV High (A Rising PUlse Being Applied to Pin 16) SYNCHRONIZATION BLOCK VSYNCH HSYNC V ns - 100 250 1.92 2.00 2.08 V UNDERVOLTAGE DETECTION (UVP)/SHUTDOWN VUVPL Comparator Threshold (Vpin4 Being Falling) VUVPH Comparator Threshold (Vpin4 Being Rising) (Note 5) - - 2.20 V HUVP Hysteresis of the UVP Comparator - 40 - mV IUVP UVP Current Source 15 25 30 mA Bias Current - - 0.1 mA IBUVP 3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design. 4. Guaranteed by design. Tested through the RRESET parameter. 5. Guaranteed by characterization and design. 6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically http://onsemi.com 6 NCP4331 ELECTRICAL CHARACTERISTICS (VCC = 20 V, VBST = 7 V, HB Grounded, TJ = 0°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit 150 160 170 °C - 50 - °C - 60 - mA TEMPERATURE PROTECTION TLIMIT Thermal Shutdown Threshold (Note 5) HTEMP Thermal Shutdown Hysteresis VCC BIASING (Internal Voltage Regulator) IVCC-max VDD VDROP ICC Regulator Current Limitation VDD Voltage @ VCC = 20 V and IVDD = 20 mA 7.0 7.5 8.0 V Voltage Drop Between the VCC and VDD Pin @ IVCC = 20 mA - 0.17 1.0 V Operating Consumption: No Switching (Fault Mode) Switching (100 kHz) - 1.5 2.0 1.9 4.0 mA VDD MANAGEMENT UVDH Undervoltage Lockout Threshold (VDD rising) 5.3 6.0 6.7 V UVDL Undervoltage Lockout Threshold (VDD falling) 5.0 5.6 6.2 V HUVD Undervoltage Lockout Hysteresis 300 400 - mV 3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design. 4. Guaranteed by design. Tested through the RRESET parameter. 5. Guaranteed by characterization and design. 6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically http://onsemi.com 7 NCP4331 0.765 0.76 IFB (nA) Vref (V) 0.755 0.75 0.745 0.74 0.735 -40 -15 10 35 60 85 110 0 20 40 60 80 100 TEMPERATURE (°C) Figure 3. Regulation Voltage Reference (Vref) versus Temperature Figure 4. FB Pin Bias Current versus Temperature 120 4 RHS-source 4.5 RHS-source 3.5 4 3 RHS_sink (W) RHS_source (W) -20 TEMPERATURE (°C) 5 3.5 3 2.5 2.5 2 1.5 2 1 1.5 0.5 1 -40 -15 10 35 60 85 0 -40 110 -15 10 35 60 85 110 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Source Resistance of the High-Side Output @ Isource = 100 mA versus Temperature Figure 6. Sink Resistance of the High-Side Output @ Isink = 100 mA versus Temperature 5 4.5 4 RHS-source RLS_sink (W) 3 3.5 3 2.5 2.5 2 1.5 2 1 1.5 0.5 1 -40 RHS-source 3.5 4 RLS_source (W) 0 -50 -100 -150 -200 -250 -300 -350 -400 -450 -500 -550 -600 -650 -700 -750 -40 -15 10 35 60 85 0 -40 110 TEMPERATURE (°C) -15 10 35 60 85 110 TEMPERATURE (°C) Figure 7. Source Resistance of the Low-Side Output @ Isource = 100 mA versus Temperature Figure 8. Sink Resistance of the Low-Side Output @ Isink = 100 mA versus Temperature http://onsemi.com 8 NCP4331 1.2 2.8 1.15 2.7 1.1 VrampON (V) VrampON (V) 2.6 2.5 2.4 1.05 1 0.95 0.9 2.3 0.85 2.2 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 0.8 -40 120 100 100 90 90 80 80 70 60 50 30 40 60 80 100 20 -40 120 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. Low-Side to High-Side Delay versus Temperature, High-Side Falling Figure 12. Low-Side to High-Side Delay versus Temperature, High-Side Rising 2.5 100 2.4 90 2.3 80 2.2 70 2.1 60 2 1.9 50 40 1.8 30 1.7 20 1.6 10 1.5 -40 -20 TEMPERATURE (°C) HUVP (V) VUVP (V) 20 120 50 30 0 100 60 40 -20 20 40 60 80 TEMPERATURE (°C) 70 40 20 -40 0 Figure 10. VrampON versus Temperature @ Vpin5 = 2.0 V tLSwHS (ns) tLSwHS (ns) Figure 9. VrampON versus Temperature @ Vpin5 = 0.5 V -20 -20 0 20 40 60 80 TEMPERATURE (°C) 100 0 -40 120 Figure 13. UVP Threshold versus Temperature -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 14. Hysteresis of the UVP Comparator versus Temperature http://onsemi.com 9 40 200 35 175 30 150 TSYNCH-HS (ns) IUVP (mA) NCP4331 25 20 -20 0 20 40 60 80 100 50 -40 120 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 15. UVP Current Source versus Temperature Figure 16. Delay Synchronization Pulse to HS High versus Temperature 100 275 90 250 80 IVCC-max (mA) 300 225 200 175 70 60 50 150 40 125 30 100 -40 -20 TEMPERATURE (°C) -20 0 20 40 60 80 100 20 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Reset Time versus Temperature Figure 18. Current Limitation of the VCC Internal Regulator versus Temperature 7.6 7.58 7.56 7.54 7.52 VDD (V) Treset (ns) 100 75 15 10 -40 125 7.5 7.48 7.46 7.44 7.42 7.4 -40 -15 10 35 60 85 110 TEMPERATURE (°C) Figure 19. VDD Voltage versus Temperature @ Vcc = 20 V and IVDD = 20 mA http://onsemi.com 10 NCP4331 DETAILED OPERATING DESCRIPTION Introduction The NCP4331 is ideal in multi-outputs applications where efficiency, ease of implementation and compactness are key requirements. Since it is often impossible to tightly regulate all the outputs and since a further regulation of the outputs is not an efficient option, it is preferable to do as follows: • Traditionally regulate the highest output voltage. • Post-regulate the other ones, by directly drawing the energy from the transformer secondary ac voltage. The NCP4331 is a controller developed to drive such buck converters that have the ability to operate from pulsed voltage. Typically, NCP4331 driven post-regulators are associated to forward converters as portrayed by Figure 20. For the sake of the simplicity, the forward of Figure 20 consists of a simple demagnetization winding and output diodes, but more sophisticated options including active clamp and synchronous rectification, would lead to a better global efficiency of the solution. Also, one can associate the NCP4331 to other architectures (like two switches' forward or half-bridge converters). Any converter able to provide the NCP4331 post-regulator with a square wave source could use this concept, as long as the NCP4331 maximum ratings are not exceeded (in particular, the “BST” and “HB” maximum voltage). • • sequencing in a smart manner so that three over the four transitions are soft. The high gate drive capability of the NCP4331 and the utilization of N-MOSFETs for both the high and low sides reduce the conduction losses to a minimum (synchronous rectification). Ease of implementation and compactness: The NCP4331 is housed in a small SO16 package and it incorporates all the functions necessary for a reliable post-regulation (synchronization block, accurate regulation block, soft-start, current control). Hence, NCP4331 driven post-regulation requires few external components. Also the high switching frequency levels it can handle (up to 400 kHz) allows the utilization of small output coil and capacitor. An internal regulator highly eases the circuit feeding. Robustness: The NCP4331 embeds powerful features to protect the application from possible over-stresses and make the post-regulator very rugged. In particular, it incorporates a second operational amplifier to lower the duty-cycle and ultimately clamp the coil current when it tends to become excessive (CCCV characteristic). Also, the soft-start and the undervoltage protections improve reliability. In addition, they help control the start and end of the post-regulator operation. Ultimately, the integration within the whole system is eased. Post-Regulation Operation Finally, the NCP4331 has the following main benefits: • Efficiency: The NCP4331 concept avoids the implementation of downstream converters to re-process the main converter output voltage when two or more outputs are to be tightly regulated. Instead, like Mag-amp systems, NCP4331 driven post-regulators directly draw the energy from the secondary side of the main converter transformer, for a more efficient power processing. In addition, the circuit manages the Figure 20 illustrates the concept where two outputs are to be regulated (”Vout1” and “Vout2”). The highest output (Vout1) is traditionally regulated thanks to a regulation arrangement that modulates the forward converter duty cycle. The other output (Vout2) is regulated by a dual MOSFET arrangement driven by the NCP4331. The high-side MOSFET turns on during one part of the forward converter on-time, while the low-side power switch is ON for the rest of the period (free wheeling). http://onsemi.com 11 NCP4331 X1 D3 D1 Vout1 L1 Demag. Winding + D2 LOAD1 C1 Forward Input Source X2 Forward Controller Feed-back with isolation GND Vin X12 Vout2 L2 NCP4331 NCP4331 X13 + C2 Driven LOAD2 Post-Regulator Feed-back Figure 20. NCP4331 Post-Regulator Associated to a Forward Converter Vin (PostRegulator Input Voltage In the case of a forward operating in continuous conduction mode (CCM) operation, the cycle is simply given by the following equation (the converter losses being neglected): dF + High-Side MOSFET Drive V out1 ǒ Ǔ @ ǒV Ǔ N N S P (eq. 1) in forward The duty-cycle of the high-side MOSFET is modulated by adjusting the leading edge of its drive (Leading Edge Modulation) Where: dF is the forward duty cycle, NS/NP is the transformer turn ratio (NP: primary number of turns, NS: secondary number of turns), (Vin)forward is the forward converter input voltage, Vout1 is the main output voltage of the forward converter. Figure 21. Leading Edge Modulation http://onsemi.com 12 NCP4331 As portrayed in Figure 21, the post-regulator controls the energy to be drawn from the power source Vin by adjusting the time during which the high-side MOSFET is on. This conduction time is modulated by adjusting the leading edge of the high side drive while the trailing edge stays synchronized to the input voltage Vin. As in a traditional buck, the post-regulated output voltage is given by the following equation: V out + d n @ NS NP @ ǒV inǓ forward Where: dn is the duty cycle of the post-regulator n. dn < dF since (NS/NP • (Vin)forward) is available only during the forward converter on-time and that anyway, the high-side MOSFET cannot be turn on as long as Vin is low (i.e., during the forward off-time). Post-regulated output voltages are then necessarily lower than the main regulated one. However, the NCP4331 scheme allows dn to nearly equal df so that if necessary, a post-regulated output voltage (Voutn) can be very closed the main one (Vout1). (eq. 2) Sequencing and Regulation Block The following timing diagram portrays the sequencing. Vin (Post-Regulator Input Voltage) TIME Internal Reset Signal TIME 250 ns Vramp (Cramp Timing Ramp) TIME TIME Sum (Vramp + EAout) EAout (Error Amplifier Out TIME Low-Side Driver TIME High-Side Driver TIME 70 ns 70 ns The Low-Side and High-Side Trans‐ itions are Delayed until Vin is High. Figure 22. Timing Diagram Sequencing and Overlapping The high-side driver turns on (off) after some delay just after the low-side has switched off (on). More precisely, the high-side MOSFET: Figure 22 portrays the sequencing of a NCP4331 driven post-regulator. http://onsemi.com 13 NCP4331 • Turns on 70 ns after the low-side MOSFET opening, • Turns off 70 ns after the low-side MOSFET closing. no input voltage. Also, this feature prevents the high-side MOSFET from keeping high in the case of any interruption in the VIN generation (if the main converter enters some skip mode or during the system stop). Practically, the input voltage presence is detected by the “SYNC” pin. Hence, there are 70 ns when both the high-side and low-side MOSFETs are on. Such a behavior is possible because this event occurs just after the input voltage has dropped to zero (the post-regulator is not the seat of cross-conduction and instead, as it will be seen in next sections, this sequencing optimizes the switching performance), i.e., at the beginning of the forward free wheeling phase. Hence, no energy can then be drawn from the converter transformer during this delay and these 70 ns should not be considered as a part of the high-side MOSFET conduction time. Similarly, there are 70 ns during which both MOSFETs are off, just before the low side conduction phase. During this short time, the body diode of the low side MOSFET derives the coil current. Hence, its drain-source voltage is already low when the low-side MOSFET turns on. The resulting Zero Voltage Switching optimizes the efficiency. In light load, the body diode of the high-side MOSFET may conduct the coil current if it is negative (flowing back from the load to the input). Soft-Start The voltage reference of the error amplifier is internally clamped by the voltage of pin 7. A current source (ISS = 50 mA) flows out of this pin. A capacitor should be applied to pin7 so that during the startup phase, the pin voltage slowly ramps up. As a consequence, the error amplifier output increases in a soft manner. Hence, the high-side MOSFET duty-cycle smoothly increases and as a result, this leads to a soft-start and to a reduction of the stress during this sequence. A resistor can also be placed between pin 7 and ground to adjust the maximum duty-cycle of the high-side MOSFET. Combine the two functions by implementing these two components in parallel. If no component is placed in parallel to the capacitor, the soft-start voltage ramps up until the internal clamp is activated. At that moment, the soft-start has no limiting action on the duty-cycle that is only controlled by the error amplifier and if used, by the auxiliary operational amplifier. Error Amplifier The NCP4331 embeds an error amplifier. The internal 0.75 V reference is better than $1.5% accurate over the 0°C to 85°C temperature range ($2% over the 0°C to 85°C range). The circuit provides access to its inverting input and to its output. Typically, the output voltage of the post-regulator is scaled down by a resistive divider to be monitored by the inverting input (”FB” pin - Pin 6). The bias current is minimized (less than 500 nA) to allow the use of a relatively high impedance feed-back network. The output of the error amplifier is pinned out for external loop compensation (Pin 5). Please note that a NCP4331 driven post-regulator can be viewed as a voltage mode buck converter and hence, that a type 3 compensation network is recommended (see application schematic of page 1). OverLapping and Transitions Vin Cramp > 2.5 V HS MOSFET LS MOSFET LS Body Diode ILOAD Coil Current Ramp Generation and PWM Section t1 An internal current source (IRAMP = 50 mA) charges the CRAMP timing capacitor to form a ramp that is reset by the synchronization pin when the input voltage falls down. The circuit adds the resulting, synchronized saw-tooth (Vramp) to the error amplifier output (EAOUT). The PWM comparator monitors the obtained sum and sets the PWM latch when this voltage (Vramp+ EAOUT) exceeds the internal PWM reference (“VPWM”). As a consequence, the low-side MOSFET turns off. 70 ns later, the high-side MOSFET switches on and remains closed until the next RESET sequence, i.e., when the input voltage drops to zero. Hence, the raising edge of the high-side MOSFET is modulated by the moment when the sum crosses the PWM reference. In other words, the NCP4331 operates in the so called Leading Edge Modulation. In fact, the PWM latch cannot be set before the input voltage is in high state. This is to avoid that the high-side MOSFET is on while there is t2 t3 t4 Figure 23. Sequencing and Overlaps Management As portrayed by Figure 23, three transitions over four are soft: 1. Low-side Turn On (t3): The synchronization block detects when the input voltage (Vin) drops to zero and following this event, it resets the circuit to prepare it for the next switching period. Practically, the CRAMP timing capacitor and the PWM latch are re-initialized and the low-side MOSFET is turned on. Just before this low-side transition, the post-regulator input voltage is low and its high-side MOSFET is still on. As a consequence, the low-side MOSFET drain potential is closed to 0 V. Thus the low-side MOSFET turns on in a Zero Voltage Switching mode (ZVS). Hence, the energy Qg necessary to http://onsemi.com 14 NCP4331 turn on the low-side MOSFET is significantly minimized (no Miller plateau) and the switching losses are very low. 2. Low-side Turn Off (t1): The high-side MOSFET turns on about 70 ns after the low-side opening. During this 70 ns time when both switches are off, the body diode of the low-side MOSFET derives the coil current (in nominal load condition, when the coil current is positive, i.e., when it flows toward the output). As a result, the low-side MOSFET turns off while its drain-source voltage keeps around zero due to its body diode activation. Again, the energy Qg to be extracted for opening the low-side MOSFET is small and the switching losses are low. 3. High-side Turn Off (t4): The low-side MOSFET turns on 70 ns before the high-side MOSFET turns off. Hence, just before t4, the input voltage being low and the low-side MOSFET being on, the voltage across the high-side MOSFET is nearly zero while the low-side MOSFET generally already derives the major part of the coil current. Finally, this transition is very soft (low current, no voltage) Only the high-side turn on (t2) that leads to switch the full current and voltage, is “hard”. This sequencing that makes soft 3 transitions over 4, helps maximize the efficiency of the post-regulator. may lead to a parasitic turn on of the low-side MOSFET if the driver impedance is too high to absorb this current without a significant increase of the driver voltage. For instance, a 30 V / 10 ns dV/dt produces a 450 mA current through a 150 pF Crss (450 = 150 pF • (30 V / 10 ns)). If the driver voltage must keep below 2.5 V to prevent unwanted turn on, the driver sink resistor should be less than: Rsink = (2.5 V/0.45 A) = 5.5 W. 2. Similarly, the sink capability of the high-side driver must be high enough to face the high dV/dt that occurs when the post-regulator input voltage abruptly turns high. Again, a 30 V / 10 ns dV/dt would produce a 450 mA current through a 150 pF Crss and the driver sink resistor should be less than: Rsink = 5.5 W. Finally, the immunity to (dV/dt)s is the main criterion in the dimensioning of the driver sink capability. Both the low and high side drivers that features a 4 W maximal sink resistance, allows a robust post-regulator operation. It must be noted that the drivers remain in a sinking mode whenever the circuit is off following an Undervoltage Lockout condition, the activation of the thermal shutdown or an undervoltage condition. Synchronization Block The “SYNC” pin is designed to receive the post-regulator input voltage (“Vin” of the application schematic). When this voltage drops below the 2.5 V internal threshold, the circuit generates a “RESET” pulse signal that is long enough (about 250 ns) to: • Activate the internal switch that is implemented to ground and fully discharge the CRAMP timing capacitor. The circuit is then initialized for a next cycle. • Reset the PWM latch and hence, initiate a free-wheeling phase (the circuit turns on the low-side MOSFET and 70 ns later, it opens the high-side MOSFET). Other Drive Constraints The post-regulator is the seat of large “dV/dt” that may disturb the system operation if the drivers are not strong enough to contain them. There are two “dV/dt” the circuit must face: 1. When the high-side MOSFET turns on, the potential of the “HB” node sharply increases and hence, it produces a huge current through the Crss capacitor of the low-side MOSFET. This current VDD SYNC SYNC + - S Q + VsyncH/ VsyncL Delay Q R RESET RESET Delay Figure 24. Synchronization Block The synchronization block generates a short reset pulse. Its duration (“delay) is 250 ns typically. The voltage that is applied to the “SYNC” pin, may be clamps the negative spikes that may cause an improper slightly negative during one part of the period. The operation of the circuit. The protection is fully effective as NCP4331 incorporates a negative protection system that long as the pin 16 source current is kept below 2 mA. http://onsemi.com 15 NCP4331 detected because of a spike or of some noise. When the NCP4331 detects an under-voltage lockout condition, the “fault” flag is asserted and both the high-side and low-side drivers are forced off. A minimum VCC voltage must be present (at least 3 V) to ensure the active grounding of the drivers. If VCC is lower, the drivers may be only tied to ground by a 60 kW internal resistor The undervoltage lockout has a 5 V minimum threshold (falling). As a consequence, 5 V minimum are available to drive the power switch. Such a level generally allows an efficient drive of most MOSFETs. Generally speaking the pin voltage is clamped to be between -100 mV and 10 V. It is recommended to apply the synchronization signal (“Vin” typically) through a resistor so that the current absorbed and sourced by the pin clamp network stays in the range of 1 mA. Bootstrap Pin The circuit features a bootstrap pin (“BST”) to optimally drive the high-side N-MOSFET. A 0.1 mF to 1 mF ceramic capacitor should be connected between this pin and the 'HB” node that is connected to the source of the high-side MOSFET. The “BST” voltage feeds the high-side driver (“HS_DRV”). Practically, the VDD voltage is applied to the “BST” pin through a diode (see application schematic of page 1) so that the bootstrap capacitor is charged to VDD when the “HB” pin is low (when the low-side MOSFET conducts). Hence, some voltage source referenced to the “HB” node (and then to the high-side MOSFET source) is made available for an effective control of the high-side MOSFET. Undervoltage Protection (UVP) The circuit incorporates a voltage regulator to ease the circuit feeding. Pin 16 makes the input of this regulator available. It can receive a dc voltage (up to 30 V). This voltage is post-regulated down to 9 V to provide the VDD voltage that supplies the circuit. This pin is designed to receive a low inertia voltage representative of the input voltage magnitude, in order detect too low input voltage pulses and to turn off both the low-side and high-side drivers in such a faulty condition. The soft-start pin is grounded when an UVP condition is detected so that the circuit smoothly recovers operation when the fault disappears. In addition to the permanent 60 mV hysteresis of the UVP comparator, this block sources 25 mA out of pin4 when no UVP is detected, to further increase the hysteresis as much as necessary to avoid erratic turns on and off of the device. A 5 ms blanking time avoids inappropriate UVP detection that may result from the application noise. Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Internal Voltage Regulator An under-voltage lockout comparator is incorporated to guarantee that the device is properly supplied before enabling the output stages. The NCP4331 starts to operate when the power supply VDD exceeds 6.0 V. A 0.4 V hysteresis avoids erratic turning on and off of the device. Also, a post-regulator having to operate in a noisy environment, a 30 ms blanking time avoids that an UVLO is The NCP4331 senses its junction temperature. When it exceeds 150°C, the circuit turns low both the high-side and low-side drivers. The power switches are kept off until the temperature has dropped to about 100°C (50°C hysteresis). Like the Undervoltage Lockout block, the TSD incorporates a 30 ms blanking time to avoid any false detection that may result from noise. http://onsemi.com 16 NCP4331 APPLICATION INFORMATION Vin Vout1 VIN_FORWARD + LOAD1 Regulation Block Ruvp1 VCC Forward Driver (e.g. NCP1280) 1 CSout VCC 16 2 CSin- BST 15 3 CSin+ HS_ DRV 14 4 UVP 5 COMP HB 13 VDD 12 Ruvp2 FB Rsync 6 FB LS_ DRV 11 7 SS GND 10 8 Cramp SYNC Vout2 L RS (Coil Series Resistor) + LOAD2 9 FB Figure 25. “Basic” Configuration (No Use of the Auxiliary Operational Amplifier) The input voltage (VIN) is rectified and a portion of the resulting signal is applied to the UVP pin so that the NCP4331 stops operating when VIN is too low. The low and high thresholds of the UVP comparator set the VIN limits (VIN rising and falling) together with the VCC capacitor. http://onsemi.com 17 NCP4331 Vin Vout1 VIN_FORWARD + LOAD1 Regulation Block VCC CSinRuvp1 Forward Driver (e.g. NCP1280) FB 1 CSout VCC 16 ROVP1 2 CSin- BST 15 CSin- 3 CSin+ HS_ DRV 14 4 UVP 5 COMP HB 13 VDD 12 Ruvp2 FB Rsync 6 FB LS_ DRV 11 7 SS GND 10 8 Cramp SYNC ROVP2 L Vout2 RS (Coil Series Resistor) + LOAD2 9 FB Figure 26. “Basic” Configuration Further Including an Overvoltage Protection (OVP) Compared to the “basic” configuration, Figure 26 further includes an OVP feature that utilizes the auxiliary operational amplifier (OPAMP2). Two resistors Rovp1 and Rovp2 scale down the output voltage and the resulting portion of Vout2 is applied to the inverting input of OPAMP2. The non inverting input receives the feedback signal that nominally equates the internal reference voltage (VREF). Hence, VREF also serves as the OVP reference. Rovp1 and Rovp2 must be dimensioned so that OPAMP2 “triggers” when Vout2 exceeds its maximum acceptable level. The output of OPAMP2 (“CSout” that is SINK only) is connected to the COMP pin to reduce the duty-cycle in case of OVP. CSout can be connected to the soft-start pin if a low duty-cycle re-start-up is preferred after an OVP event. It can be noted that both options offer a protection if the feedback is accidentally grounded since in this case, the pin6 voltage and hence, the OVP threshold are close to zero. Ultimately, the post-regulator is protected in this fault condition. http://onsemi.com 18 NCP4331 Vin Vout1 VIN_FORWARD + LOAD1 Regulation Block VCC 1 CSout VCC 16 2 CSin- BST 15 3 CSin+ HS_ DRV 14 CSinRuvp1 Forward Driver (e.g. NCP1280) CSin+ 4 UVP 5 COMP Ruvp2 FB Rsync HB 13 VDD 12 6 FB LS_ DRV 11 7 SS GND 10 8 Cramp SYNC CSinC1 R1 CSin+ Vout1 Rth0 R2 Vout2 L RS (Coil Series Resistor) + LOAD2 9 FB Figure 27. Post-Regulation with CCCV Protection In Figure 27, the series resistor RS of the inductor senses the coil current. Practically if the resistors R1and R2 are equal and if Rth0 is high compared to them, the inductor voltage is integrated by the auxiliary OPAMP. Since the average voltage across the pure inductive part of the coil is zero in steady state, this sensing technique actually returns the averaged voltage across the series resistor RS (”VRS”). VRS is compared to an offset created using the main output voltage (“Vout1”) together with of the R2 and Rth0 resistors (more specifically, this offset is [(R2/(R2 + Rth0)) • Vout1]). Finally, the coil maximum current is given by: (Icoil)max = (R2/(R2 + Rth0)) • Vout1/RS). Any accurate voltage source could be used instead of Vout1. This technique that limits the coil current as a function of the main output Vout1, further performs some soft-start function and helps Vout2 track Vout1. http://onsemi.com 19 NCP4331 Vout1 Vin Vout1 VIN_FORWARD Rtrack1 to Pin 7 + LOAD1 Regulation Block Rtrack2 VCC 1 CSout VCC 16 2 CSin- BST 15 3 CSin+ HS_ DRV 14 CSinRuvp1 Forward Driver (e.g. NCP1280) CSin+ 4 UVP 5 COMP HB 13 VDD 12 Ruvp2 FB Rsync 6 FB LS_ DRV 11 7 SS GND 10 8 Cramp SYNC CSinC1 R1 CSin+ Vout1 Rth0 R2 Vout2 L RS (Coil Series Resistor) + LOAD2 9 FB Figure 28. Post-Regulation with CCCV, OVP and Enhanced Tracking of the Main Output Voltage (“Vout1”) Compared to Figure 27, Figure 28 further consists of the resistors “Rtrack1” and “Rtrack2” that serve to apply a portion of the main output voltage (“Vout1”) to the NCP4331 soft-start pin. Hence, the post-regulator duty-cycle is limited by the Vout1 level for an improved tracking. http://onsemi.com 20 NCP4331 PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 16 9 1 8 -B- P 8 PL 0.25 (0.010) B M S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 21 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 NCP4331 PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 22 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NCP4331 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 23 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP4331/D