SEMICONDUCTOR TECHNICAL DATA The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. • • • • • • • 1.8GHz Minimum Count Frequency Differential Clock Input and Data Output Pins VBB Output for Single-Ended Use Internal 75kΩ Input Pulldown Resistors Synchronous and Asynchronous Enable Pins Asynchronous Master Reset Extended 100E VEE Range of –4.2V to –5.46V 8-BIT RIPPLE COUNTER The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device’s flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter FN SUFFIX while overriding any synchronous enable signals. The E137 features PLASTIC PACKAGE XORed enable inputs, EN1 and EN2, which are synchronous to the CLK CASE 776-02 input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. PIN NAMES If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been PIN FUNCTION inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable CLK, CLK Differential Clock Inputs signal is clocked correctly, hence, the counter is disabled. Q0-Q7, Q0-Q7 Differential Q Outputs The E137 can also be driven single-endedly utilizing the VBB output A_Start Asynchronous Enable Input supply as the voltage reference for the CLK input signal. If a single-ended EN1, EN2 Synchronous Enable Inputs signal is to be used the VBB pin should be connected to the CLK input and MR Asynchronous Master Reset bypassed to ground via a 0.01µF capacitor. VBB can only source/sink VBB Switching Refernce Output 0.5mA, therefore it should be used as a switching reference for the E137 only. All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. LOGIC DIAGRAM A_Start EN1 EN2 D R Q0 Q0 Q1 CLK CLK Q CLK CLK CLK CLK Q Q CLK CLK Q Q D D R VBB Q Q R 7/96 2–1 CLK CLK D R MR Motorola, Inc. 1996 Q7 Q1 Q REV 2 Q7 MC10E137 MC100E137 Pinout: 28-Lead PLCC (Top View) Q7 Q7 Q6 Q6 VCCO Q5 Q5 25 24 23 22 21 20 19 A_Start 26 18 Q4 EN1 27 17 Q4 EN2 28 16 VCC VEE 1 15 Q3 CLK 2 14 Q3 CLK 3 13 Q2 VBB 4 12 Q2 5 6 7 8 9 10 11 MR VCCO Q0 Q0 Q1 Q1 VCCO * All VCC and VCCO pins are tied together on the die. SEQUENTIAL TRUTH TABLE Function EN1 EN2 A_Start MR CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Reset X X X H X L L L L L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L L L L L L L H H H L H Stop H H L L L L L L Z Z L L L L L L L L L L L L H H H H Asynch Start H H L L L L H H H L L L Z Z Z L L L L L L L L L L L L L L L H H H L L H L H L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L H H H L L H L L H L H Stop L L H H L L L L Z Z L L L L L L L L H H L L L L H H Synch Start H H H H H H L L L L L L Z Z Z L L L L L L L L L L L L H H H L L H H H L L H L Stop H H L L L L L L Z Z L L L L L L L L H H H H L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L H H H H H H L H H H L H Reset X X X H X L L L L L L L L Z = Low to High Transition MOTOROLA 2–2 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E137 MC100E137 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol VBB Characteristic Output Reference Voltage 10E 100E IIH Input HIGH Current IEE Power Supply Current 10E 100E Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Condition V –1.38 –1.38 –1.27 –1.27 –1.35 –1.38 –1.25 –1.26 150 –1.31 –1.38 –1.19 –1.26 150 150 µA mA 121 121 145 145 121 121 145 145 121 139 145 167 AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 1800 2200 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 85°C Max Min Typ 1800 2200 1350 1650 2025 2350 2700 3050 3375 3700 950 700 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 Max Unit fCOUNT Maximum Count Frequency 1800 2200 tPLH tPHL Propagation Delay to Output CLK to Q0 CLK to Q1 CLK to Q2 CLK to Q3 CLK to Q4 CLK to Q5 CLK to Q6 CLK to Q7 A_Start to Q0 MR to Q0 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 ts Setup Time (EN1, EN2) 0 –150 0 –150 0 –150 ps th Hold Time (EN1, EN2) 300 150 300 150 300 150 ps tRR Reset Recovery Time MR, A_Start 400 200 400 200 400 200 Minimum Pulse Width CLK, MR, A_Start 400 VPP Minimum Input Swing (CLK) 0.25 1.0 0.25 1.0 0.25 1.0 V VCMR Com Mode Range (CLK) –0.4 –2.0 –0.4 –2.0 –0.4 –2.0 V tr tf Rise/Fall Times Q0,Q1 Q2 to Q7 150 275 400 600 150 275 400 600 150 275 400 600 tPW Condition MHz ps 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 2200 2550 3000 3425 3825 4250 4600 4950 1700 1300 ps ps 400 400 ps Note 1 20%–80% 1. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings. ECLinPS and ECLinPS Lite DL140 — Rev 4 2–3 MOTOROLA MC10E137 MC100E137 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 2–4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E137 MC100E137 Motorola reserves the right to make changes without further notice to any products herein. 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