PD -95050
AUTOMOTIVE MOSFET
IRFP2907PbF
HEXFET® Power MOSFET
Typical Applications
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Benefits
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D
Integrated Starter Alternator
42 Volts Automotive Electrical Systems
Lead-Free
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
VDSS = 75V
RDS(on) = 4.5mΩ
G
ID = 209A
S
Description
Specifically designed for Automotive applications, this
Stripe Planar design of HEXFET® Power MOSFETs
utilizes the lastest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed
and improved repetitive avalanche rating. These benefits
combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a
wide variety of other applications.
TO-247AC
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Max.
Units
209
148
840
470
3.1
± 20
1970
See Fig.12a, 12b, 15, 16
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
Units
–––
0.24
–––
0.32
–––
40
°C/W
1
2/26/04
IRFP2907PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
75
–––
–––
2.0
130
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.085
3.6
–––
–––
–––
–––
–––
–––
410
92
140
23
190
130
130
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
5.0
LS
Internal Source Inductance
–––
13
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
––– 13000
––– 2100
––– 500
––– 9780
––– 1360
––– 2320
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
4.5
mΩ VGS = 10V, ID = 125A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 25V, ID = 125A
20
VDS = 75V, VGS = 0V
µA
250
VDS = 60V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
620
ID = 125A
140
nC
VDS = 60V
210
VGS = 10V
–––
VDD = 38V
–––
ID = 125A
ns
–––
RG = 1.2Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 209
showing the
A
G
integral reverse
––– ––– 840
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 125A, VGS = 0V
––– 140 210
ns
TJ = 25°C, IF = 125A
––– 880 1320 nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.25mH
RG = 25Ω, IAS = 125A. (See Figure 12).
ISD ≤ 125A, di/dt ≤ 260A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 90A.
Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
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IRFP2907PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
100
10
4.5V
20µs PULSE WIDTH
TJ = 25 °C
1
0.1
1
10
4.5V
10
0.1
100
Fig 1. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.0
TJ = 175 ° C
100
TJ = 25 ° C
10
V DS = 25V
20µs PULSE WIDTH
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
5.0
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
1
4.0
20µs PULSE WIDTH
TJ = 175 ° C
10.0
ID = 209A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFP2907PbF
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
16000
Coss = Cds + Cgd
Ciss
12000
8000
4000
Coss
20
VGS , Gate-to-Source Voltage (V)
20000
1
16
12
8
4
10
0
100
VDS, Drain-to-Source Voltage (V)
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
200
300
400
500
600
700
QG , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
TJ = 175 ° C
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
VDS = 60V
VDS = 37V
Crss
0
1000
10
1
V GS = 0 V
0.5
1.0
1.5
10us
100us
100
TJ = 25 ° C
0.1
0.0
2.0
2.5
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
ID = 125A
3.0
1ms
10
TC = 25 ° C
TJ = 175 ° C
Single Pulse
1
10ms
10
100
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFP2907PbF
240
200
ID , Drain Current (A)
RD
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+
-VDD
160
10V
120
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
80
Fig 10a. Switching Time Test Circuit
40
VDS
90%
0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
175
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.1
0.01
0.20
0.10
0.05
0.02
0.01
PDM
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFP2907PbF
D.U.T
RG
+
- VDD
IAS
20V
0.01Ω
tp
ID
51A
88A
BOTTOM 125A
TOP
4000
DRIVER
L
VDS
EAS , Single Pulse Avalanche Energy (mJ)
5000
15V
3000
A
2000
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
1000
tp
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
VG
4.0
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) , Variace ( V )
3.5
Charge
3.0
ID = 250µA
2.5
2.0
1.5
VGS
1.0
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
-75 -50 -25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 14. Threshold Voltage Vs. Temperature
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IRFP2907PbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
100
0.05
0.10
10
1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
2000
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 125A
1600
1200
800
400
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRFP2907PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 17. For N-channel HEXFET® power MOSFETs
8
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IRFP2907PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
-D-
3.65 (.143)
3.55 (.140)
15.90 (.626)
15.30 (.602)
-B-
-A-
0.25 (.010) M D B M
2.50 (.089)
1.50 (.059)
4
5.50 (.217)
20.30 (.800)
19.70 (.775)
2X
1
2
5.30 (.209)
4.70 (.185)
NOTES:
5.50 (.217)
4.50 (.177)
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE
TO-247-AC.
3
-C-
14.80 (.583)
14.20 (.559)
2.40 (.094)
2.00 (.079)
2X
5.45 (.215)
2X
4.30 (.170)
3.70 (.145)
0.80 (.031)
3X 0.40 (.016)
1.40 (.056)
3X 1.00 (.039)
0.25 (.010) M
2.60 (.102)
2.20 (.087)
C A S
3.40 (.133)
3.00 (.118)
LEAD ASSIGNMENTS
Hexfet
IGBT
1 -LEAD
GateASSIGNMENTS
1 - Gate
1 - GATE2 - Collector
2 - Drain
2 - DRAIN
3 - Source
3 - Emitter
3 - SOURCE
4 - Drain
4 - DRAIN4 - Collector
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WIT H ASSEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN THE AS SEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNATIONAL
RECT IFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
IRFPE30
56
035H
57
DAT E CODE
YEAR 0 = 2000
WEEK 35
LINE H
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/04
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9
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/