ONSEMI NB3N3011

NB3N3011
3.3 V 100 MHz / 106.25 MHz
PureEdge Clock Generator
with LVPECL Differential
Output
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Description
The NB3N3011 is a Fibre Channel Clock Generator and uses a
26.5625 MHz crystal to synthesize 106.25 MHz or a 25 MHz crystal
to synthesize 100 MHz. The NB3N3011 has excellent <1 ps phase
jitter performance over the 637 kHz – 10 MHz integration range. The
NB3N3011 is packaged in an 8−Pin 4.4 mm x 3.0 mm TSSOP, making
it ideal for use in systems with limited board space.
MARKING
DIAGRAM
Features
• PureEdge Clock Family Provides Accuracy and Precision
• One Differential LVPECL Output
• Crystal Oscillator Interface Designed for Fundamental Mode 18 pF
A
Y
WW
G
Parallel Resonant Crystal (25 MHz or 26.5625 MHz)
• Output Frequency: 106.25 MHz (26.5625 MHz Crystal) or 100 MHz
•
•
•
•
•
•
(25 MHz Crystal)
VCO Range: 760 MHz − 950 MHz
RMS Phase Jitter @ 100 MHz, using a 25 MHz Crystal
(637 kHz − 10 MHz): 0.29 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase noise:
Offset Noise Power
100 Hz −108 dBc/Hz
1 kHz −122 dBc/Hz
10 kHz −135 dBc/Hz
100 kHz −135 dBc/Hz
3.3 V Power Supply
−40°C to 85°C Ambient Operating Temperature
These are Pb−Free Devices*
XIN
25 MHz
or
26.5625 MHz X
OUT
Crystal
Oscillator
Phase
Detector
311
YWW
AG
TSSOP−8
DT SUFFIX
CASE 948S
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VCO
850 MHz
w/26.5625
MHz Ref.
Charge
Pump
N =B8
LVPECL
Output
Q
100 MHz
or
Q 106.25 MHz
M = B32
Figure 1. Logic Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 0
1
Publication Order Number:
NB3N3011/D
NB3N3011
VCCA
1
8
VCC
VEE
2
7
Q
XOUT
3
6
Q
XIN
4
5
NC
NB3N3011
Figure 2. Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Symbol
Type
Description
1
VCCA
Power
Positive Analog Power Supply Pin. Connected to VCC with filter components (See Figure 8).
2
VEE
Power
Negative Supply Pin.
3
XOUT
Input
Crystal Input (OUT).
4
XIN
Input
Crystal Input (IN).
5
NC
Unused
No Connect.
6
Q
Output
Inverted Differential Output. Typically terminated with 50 to VCC−2.0 V.
7
Q
Output
Noninverted Differential Output. Typically terminated with 50 to VCC−2.0 V.
8
VCC
Power
Positive Digital Core Power Supply Pin. Connected to 3.3 V.
Table 2. ATTRIBUTES
Characteristic
Value
ESD Protection
Moisture Sensitivity (Note 1)
Human Body Model
Machine Model
> 6 kV
> 200 V
Pb−Free Pkg, TSSOP−8
Level 3
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
4150
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
VCC
Supply Voltage
VI
Inputs
IO
Output Current
JA
Thermal Resistance (Junction−to−Ambient)
TSTG
Storage Temperature
Value
Unit
4.6
V
−0.5 to VCC + 0.5
V
Continuous
Surge
50
100
mA
0 Lfpm
500 Lfpm
142
103
°C/W
−65 to 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NB3N3011
Table 4. POWER SUPPLY DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C)
Symbol
Min
Typ
Max
Unit
VCC
Core Supply Voltage
Parameter
Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
ICCA
Analog Supply Current
19
23
mA
IEE
Power Supply Current
27
31
mA
Included in IEE
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. LVPECL DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
Output High Voltage (Note 2)
VCC − 1.4
VCC − 0.9
V
VOL
Output Low Voltage (Note 2)
VCC − 2.0
VCC − 1.7
V
VSWING
Peak−to−Peak Output Voltage Swing
1.0
V
0.6
0.75
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs terminated with 50 to VCC − 2.0 V. See Figures 4 and 12.
Table 6. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Conditions
Min
Input Capacitance
Typ
Max
4
Unit
pF
Table 7. CRYSTAL CHARACTERISTICS (Fundamental Mode 18 pF Parallel Resonant Crystal)
Parameter
Conditions
Frequency
Min
Typ
24
Max
Unit
30
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7.0
pF
Table 8. AC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C (Note 4))
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
96
100/106.25
120
MHz
fOUT
Output Frequency
24 MHz − 30 MHz Crystal
(Typ. 25 MHz − 26.5625 MHz)
tjit(∅)
RMS Phase Jitter (Random)
(Note 3)
106.25 MHz; Integration Range:
637 kHz −10 MHz
0.29
100 MHz; Integration Range:
637 kHz −10 MHz
0.29
ps
tR/tF
Output Rise/Fall Time
20% to 80% (See Figure 7)
275
600
ps
odc
Output Duty Cycle
(See Figure 6)
48
52
%
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Please refer to the Phase Noise Plot.
4. Output terminated with 50 to VCC− 2.0 V. See Figures 4 and 12.
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NOISE POWER (dBc)
NB3N3011
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
PARAMETER MEASUREMENT INFORMATION
2V
Q
VCC
Noise Power
Phase Noise Plot
Z = 50 SCOPE
50 LVPECL
Z = 50 Phase Noise Mask
Q
VEE
50 Offset Frequency
f1
−1.3 V " 0.165 V
RMS + ǸArea Under the Masked Phase Noise Plot
Figure 4. Output Load AC Test Circuit
(Split Power Supply)
Figure 5. RMS Phase Jitter
Q
Q
Q
f2
Clock
Outputs
Pulse Width
tPERIOD
odc +
Q
80%
80%
VSWING
20%
20%
tR
tPW
tF
tPERIOD
Figure 6. Output Duty Cycle/Pulse Width/Period
Figure 7. Output Rise/Fall Time
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NB3N3011
APPLICATION INFORMATION
Power Supply Filtering
Figure 9 illustrates a parallel resonant crystal with its
associated load capacitors. The capacitor values shown were
determined using a 26.5625 MHz, 18 pF parallel resonant
crystal and were chosen to minimize the ppm error.
Capacitor values can be adjusted slightly for different board
layouts to optimize accuracy.
The NB3N3011 is a mixed analog/digital product, and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB3N3011 also
generates sub−nanosecond output edge rates, and therefore,
a good power supply bypassing scheme is a must.
The NB3N3011 provides separate power supplies for the
digital circuitry (VCC) and the internal PLL (VCCA). The
simplest form of noise isolation is a power supply filter on
the VCCA pin.
Figure 8 illustrates a typical power supply filter scheme.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
The purpose of this design technique is to try and isolate
the high switching noise of the digital outputs from the
relatively sensitive internal analog phase−locked loop. The
power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply
noise−related problems in most designs.
3.3 V
VCC
0.01 F
10 VCCA
0.01 F
10 F
Figure 8. Power Supply Filtering
C1
33 pF
XOUT
X1
Crystal Oscillator Input Interface
18 pF Parallel Crystal
The NB3N3011 features an integrated crystal oscillator to
minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
As the oscillator is somewhat sensitive to loading on its
inputs, the user is advised to mount the crystal as close to the
NB3N3011 as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
C2
27 pF
XIN
Figure 9. Crystal Input Interface
APPLICATION SCHEMATIC
Figure 10 shows a schematic example of the NB3N3011.
An example of LVPECL termination is shown in this
schematic. Additional LVPECL termination approaches are
shown in the AND8020 Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
generating 106.25 MHz output frequency. The C1 = 27 pF
and C2 = 33 pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
VCC
VCC
VCCA
R2
10
C2
33 pF
C3
10 F
18 pF
VCC
0.01 F
X1
C1
27 pF
R3
ZO = 50 133
U1
C4
1
8
VCC
7
Q
Q 6
NC 5
VCCA
2 V
EE
3 X
OUT
4
XIN
Q
+
Q
ZO = 50 C5
0.1 VCC = 3.3 V
Figure 10. Typical Application Schematic
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5
R5
133
−
R4
82.5
R6
82.5
NB3N3011
PC Board Layout Example
Table 9. Footprint Table
Figure 11 shows a representative board layout for the
NB3N3011. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or through−hole HC49 package. The
footprints of other components in this example are listed in
Table 9. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between VCC and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3011 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
The voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
Q
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
C2
C1
Figure 11. PC Board Layout
Zo = 50 D
Receiver
Device
Driver
Device
Q
D
Zo = 50 50 50 VTT
VTT = VCC − 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
NB3N3011DTG
TSSOP8 4.4 mm
(Pb−Free)
100 Units / Rail
NB3N3011DTR2G
TSSOP8 4.4 mm
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N3011
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE B
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
L
0.20 (0.008) T U
1
S
T U
5
B
−U−
PIN 1
IDENT
M
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
J J1
4
K1
K
A
−V−
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
DETAIL E
G
PLANE
P
0.25 (0.010)
N
M
N
P1
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
P
P1
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
−−−
1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
−−−
2.20
−−−
3.20
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
−−− 0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
−−− 0.087
−−− 0.126
F
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your local
Sales Representative
NB3N3011/D