NUP2201MR6 Low Capacitance TSOP−6 Diode−TVS Array for High Speed Data Lines Protection http://onsemi.com The NUP2201MR6 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lightning. Features: • Low Capacitance (3 pF Maximum Between I/O Lines) • ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model • • and Class C (Exceeding 400 V) per Machine Model Protection for the Following IEC Standards: IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000−4−4 (EFT) 40 A (5/50 ns) IEC 61000−4−5 (lightning) 23 A (8/20 ms) UL Flammability Rating of 94 V−0 PIN CONFIGURATION AND SCHEMATIC Typical Applications: • • • • • TSOP−6 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) Monitors and Flat Panel Displays Pb−Free Package is Available I/O 1 6 I/O VN 2 5 VP N/C 3 4 N/C 6 1 TSOP−6 CASE 318G PLASTIC MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Peak Power Dissipation 8 x 20 mS @ TA = 25°C (Note 1) Rating Ppk 500 W Operating Junction Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 235 °C ESD 16000 400 20000 20000 V Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Air (ESD) IEC 61000−4−2 Contact (ESD) MARKING DIAGRAM Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2) 6 62 MG G 1 62 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NUP2201MR6T1 Package Shipping† TSOP−6 3000/Tape & Reel NUP2201MR6T1G TSOP−6 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 2 1 Publication Order Number: NUP2201MR6/D NUP2201MR6 ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions VRWM Breakdown Voltage Min Typ (Note 2) VBR IT=1 mA, (Note 3) Max Unit 5.0 V 6.0 V Reverse Leakage Current IR VRWM = 5 V 5.0 mA Clamping Voltage VC IPP = 5 A (Note 4) 12.5 V Clamping Voltage VC IPP = 8 A (Note 4) 20 V Maximum Peak Pulse Current IPP 8x20 ms Waveform 25 A Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2) TYPICAL PERFORMANCE CURVES 100 100 90 90 % OF PEAK PULSE CURRENT PEAK POWER DISSIPATION (%) (TJ = 25°C unless otherwise noted) 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 200 PEAK VALUE IRSM @ 8 ms tr 0 20 TA, AMBIENT TEMPERATURE (°C) 20 4.5 18 CLAMPING VOLTAGE (V) JUNCTION CAPACITANCE (pF) 5.0 4.0 3.5 I/O−Ground 2.5 2.0 I/O lines 1.5 1.0 0.5 0.0 80 60 Figure 2. 8 × 20 ms Pulse Waveform Figure 1. Pulse Derating Curve 3.0 40 t, TIME (ms) 16 14 12 10 8 6 4 2 0 1 2 3 4 0 5 0 VBR, REVERSE VOLTAGE (V) 10 20 30 40 50 PEAK PULSE CURRENT (A) Figure 3. Junction Capacitance vs Reverse Voltage Figure 4. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform) http://onsemi.com 2 NUP2201MR6 APPLICATIONS INFORMATION Option 2 Protection of two data lines with bias and power supply isolation resistor. The NUP2201MR6 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used on high speed I/O data lines. The integrated design of the NUP2201MR6 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (TSOP−6). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. I/O 1 I/O 2 VCC 1 10 k 5 3 4 3 4 I/O 1 I/O 2 I/O 1 I/O 2 2 5 Option 3 Protection of two data lines using the internal TVS diode as reference. Option 1 Protection of two data lines and the power supply using Vcc as reference. 6 2 The NUP2201MR6 can be isolated from the power supply by connecting a series resistor between pin 5 and Vcc. A 10 kW resistor is recommended for this application. This will maintain bias on the internal TVS and steering diodes, reducing their capacitance. NUP2201MR6 Configuration Options The NUP2201MR6 is able to protect two data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or Vcc+Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductance. 1 6 1 6 2 5 3 4 NC In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). VCC ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: For this configuration, connect pin 5 directly to the positive supply rail (Vcc), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. http://onsemi.com 3 NUP2201MR6 Power Supply IESDpos VCC Protected Data Line Device inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP2201MR6 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. D1 IESDpos IESDneg D2 IESDneg VF + VCC −VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = Vcc + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply D1 D3 D2 D4 0 IESDpos NUP2201MR6 Equivalent Circuit VCC Protected Device D1 IESDpos D2 VC = VCC + Vf + (L diESD/dt) IESDneg During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. IESDneg Data Line Power Supply VCC D1 VC = −Vf − (L diESD/dt) Protected Device An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = Vcc + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic IESDpos Data Line D2 The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode is provided in Figure 4 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 4 NUP2201MR6 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS VBUS VBUS D+ RT D+ RT D− VBUS GND USB Controller D− VBUS NUP4201MR6 CT CT DOWNSTREAM USB PORT GND VBUS VBUS NUP2201MR6 RT D+ RT CT CT ESD Protection for USB Port http://onsemi.com 5 D− GND DOWNSTREAM USB PORT NUP2201MR6 PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A L 6 S 1 5 4 2 3 B MILLIMETERS DIM MIN MAX A 2.90 3.10 B 1.30 1.70 C 0.90 1.10 D 0.25 0.50 G 0.85 1.05 H 0.013 0.100 J 0.10 0.26 K 0.20 0.60 L 1.25 1.55 M 0_ 10 _ S 2.50 3.00 D G M J C 0.05 (0.002) K H INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 SOLDERING FOOTPRINT* 2.4 0.094 1.9 0.075 0.95 0.037 0.95 0.037 0.7 0.028 1.0 0.039 Figure 5. TSOP−6 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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