Samsung M470L3224DT0-CB3 256mb ddr sdram module Datasheet

M470L3224DT0
200pin DDR SDRAM SODIMM
256MB DDR SDRAM MODULE
(32Mx64 based on 16Mx 16 DDR SDRAM)
200pin SODIMM
64bit Non-ECC/Parity
Revision 0.1
Jan. 2002
Rev. 0.1 Jan. 2002
M470L3224DT0
200pin DDR SDRAM SODIMM
Revision History
Revision 0.0 (Dec. 2001)
1. First release.
Revision 0.1 (Jan, 2002)
1. Added tRAP(Active to Read w/ autoprecharge command)
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
M470L3224DT0 200pin DDR SDRAM SODIMM
32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16
FEATURE
GENERAL DESCRIPTION
The Samsung M470L3224DT0 is 32M bit x 64 Double Data
Rate SDRAM high density memory modules.
The Samsung M470L3224DT0 consists of eight CMOS 16M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOPII(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the
• Performance range
Part No.
Max Freq.
Interface
M470L3224DT0-C(L)B3 166MHz(6ns@CL=2.5)
M470L3224DT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L3224DT0-C(L)B0 133MHz(7.5ns@CL=2.5)
SSTL_2
M470L3224DT0-C(L)A0 100MHz(10ns@CL=2)
printed circuit board in parallel for each DDR SDRAM.
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
The M470L3224DT0 is Dual In-line Memory Modules and
• Double-data-rate architecture; two data transfers per clock cycle
intended for mounting into 200pin edge connector sockets.
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
PIN DESCRIPTION
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
Key
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
41
43
45
47
49
51
53
55
57
59
61
63
65
Pin
Front
Pin
Front
67
DQ27 135
DQ34
69
VDD
137
VSS
71
CB0
139
DQ35
73
CB1
141
DQ40
75
VSS
143
VDD
77
DQS8 145
DQ41
79
CB2
147
DQS5
81
VDD
149
VSS
83
CB3
151
DQ42
85
DU
153
DQ43
87
VSS
155
VDD
89
CK2
157
VDD
91
/CK2
159
VSS
93
VDD
161
VSS
95
CKE1 163
DQ48
97
DU
165
DQ49
99
A12
167
VDD
101
A9
169
DQS6
103
VSS
171
DQ50
105
A7
173
VSS
107
A5
175
DQ51
109
A3
177
DQ56
111
A1
179
VDD
113
VDD
181
DQ57
115 A10/AP 183
DQS7
117
BA0
185
VSS
119
/WE
187
DQ58
121
/S0
189
DQ59
123 DU(A13) 191
VDD
125
VSS
193
SDA
127
DQ32 195
SCL
129
DQ33 197 VDDSPD
131
VDD
199 VDDID
133 DQS4
Pin
Back
Pin
Back
Pin
Back
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/S1
DU
VSS
DQ36
DQ37
VDD
DM4
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
42
44
46
48
50
52
54
56
58
60
62
64
66
Pin Name
*
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS7
Data Strobe input/output
CK0~ CK2,
CK0~ CK2
Clock input
CKE0
Clock enable input
CS0
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DM0 ~ DM7
Data - in mask
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD identification flag
NC
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
FUNCTIONAL BLOCK DIAGRAM
S1
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS2
DM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS3
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
S
D0
S
D4
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
S
D1
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D5
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D7
A0 - A13
A0-A13: DDR SDRAMs D0 - D7
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
CKE0
CKE: SDRAMs D0 - D3
CKE1
CKE: SDRAMs D4 - D7
WE
WE: SDRAMs D0 - D7
V DDSPD
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
D0 - D7
VREF
D0 - D7
VSS
D0 - D7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS5
DM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS6
DM6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS7
DM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D2
S
D6
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D3
S
D7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
Dram1
R=120Ω
5%
±
Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
SPD
V DD/V DDQ
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDRAMs
4 SDRAMs
4 SDRAMs
NC
Card
Edge
*Clock Net Wiring
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
Dram2
CK
CK
Dram3
Dram4
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
Absolute Maximum Rate
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
12
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
VTT
VREF-0.04
VREF+0.04
V
2
Input logic high voltage
VIH(DC)
VREF+0.15
VDDQ+0.3
V
4
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
4
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.3
VDDQ+0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX(DC)
1.15
1.35
V
5
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver)
;VOUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver)
;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver)
;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver)
;VOUT = VTT - 0.45V
IOL
9
mA
Input leakage current
Unit
Note
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
DDR SDRAM IDD spec table
Symbol
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Unit
IDD0
580
500
460
mA
IDD1
720
640
580
mA
IDD2P
24
24
24
mA
IDD2F
200
160
144
mA
IDD2Q
160
144
128
mA
IDD3P
280
240
200
mA
IDD3N
440
360
320
mA
IDD4R
1020
860
760
mA
IDD4W
980
800
680
mA
IDD5
940
840
760
mA
Normal
24
24
24
mA
Low power
12
12
12
mA
1620
1380
1200
mA
IDD6
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
Parameter/Condition
Symbol
Max
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF + 0.31
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
Unit
Note
V
3
VREF - 0.31
V
3
VDDQ+0.6
V
1
0.5*VDDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
VREF +0.31/VREF-0.31
V
VREF
V
Vtt
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Load Circuit
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11 , BA0 ~ BA1,RAS,CAS, WE )
CIN1
36
44
pF
Input capacitance(CKE0)
CIN2
36
44
pF
Input capacitance( CS0, CS1)
CIN3
26
30
pF
Input capacitance( CLK0, CLK1)
CIN4
34
38
pF
Data & DQS input/output capacitance(DQ0~DQ63)
COUT
12
14
pF
Input capacitance(DM0~DM8)
CIN5
12
14
pF
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
AC Timming Parameters & Specifications
Parameter
Symbol
-TCB3
(DDR333)
Min
Row cycle time
tRC
60
Refresh row cycle time
tRFC
72
Row active time
tRAS
42
RAS to CAS delay
tRCD
18
Row precharge time
Max
-TCA2
(DDR266A)
-TCB0
(DDR266B)
Min
Min
Max
65
65
75
70K
45
Max
20
45
Min
ns
80
120K
48
Unit Note
Max
70
75
120K
-TCA0
(DDR200)
ns
120K
ns
20
20
ns
tRP
18
20
20
20
ns
Row active to Row active delay
tRRD
12
15
15
15
ns
Write recovery time
tWR
15
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
1
Clock cycle time
CL=2.0
CL=2.5
tCK
7.5
12
7.5
12
10
12
tCK
10
12
ns
5
ns
5
6
12
7.5
12
7.5
12
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
ns
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.6
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
0
ns
DQS-in hold time
tWPRE
0.25
0.25
0.25
0.25
tCK
tDSS
0.2
0.2
0.2
0.2
tCK
DQS-out access time from CK/CK
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
tIS
0.75
0.9
0.9
1.1
ns
6
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
1.1
ns
6
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
1.1
ns
6
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
1.1
ns
6
Data-out high impedence time from CK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
+0.7
-0.75
+0.75
-0.75
+0.75
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
0.9
1.1
0.9
1.1
0.9
1.1
2
Address and Control Input setup time(fast)
Data-out low impedence time from CK/CK
1.1
5
-0.8
+0.8
-0.8
+0.8
tCK
ns
tLZ
-0.7
tSL(I)
0.5
0.5
0.5
0.5
V/ns
6
tSL(IO)
0.5
0.5
0.5
0.5
V/ns
7
V/ns
10
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
1.0
4.5
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
ns
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
Parameter
-TCB3
(DDR333)
Symbol
Min
Max
-TCA2
(DDR266A)
-TCB0
(DDR266B)
Min
Min
Max
Max
-TCA0
(DDR200)
Min
Unit Note
Max
Mode register set cycle time
tMRD
12
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
0.6
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
0.6
ns
7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
2.5
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
2
ns
Power down exit time
tPDEX
6
7.5
7.5
10
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
80
ns
Exit self refresh to read command
tXSRD
200
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
0.8
ns
0.4
0.6
tCK
3
tCK
11
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tQHS
0.55
0.75
0.6
0.4
0.6
0.75
tWPST
0.4
0.4
0.6
tRAP
18
20
20
20
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
4
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
∆tDH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
8. I/O Setup/Hold Plateau Derating
I/O Input Level
∆tDS
∆tDH
(mV)
(ps)
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
∆tDH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
(Single ended)
∆tIH/tIS
(ps)
∆tDSS/tDSH
(ps)
∆tAC/tDQSCK
(ps)
∆tLZ(min)
(ps)
∆tHZ(max)
(ps)
1.0V/ns
0
0
0
0
0
0.75V/ns
+50
+50
+50
-50
+50
0.5V/ns
+100
+100
+100
-100
+100
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A12, A 11
A9 ~ A 0
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
H
H
L
L
H
H
H
H
X
X
X
X
L
L
H
H
V
X
L
H
L
H
V
L
H
Bank Active & Row Addr.
H
Read &
Column Address
Auto Precharge Disable
H
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
H
X
L
H
L
L
H
X
L
H
H
L
H
X
L
L
H
L
Entry
H
L
H
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
Precharge Power Down Mode
Exit
L
DM
H
No operation (NOP) : Not defined
H
H
X
X
X
X
X
L
H
H
H
3
3
X
V
3
Row Address
L
Column
Address
(A0~A9)
H
L
Column
Address
(A0~A9)
H
X
V
L
X
H
4
4
4
4, 6
7
X
5
X
X
X
H
3
X
8
9
9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA 1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 Jan. 2002
200pin DDR SDRAM SODIMM
M470L3224DT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
1
39 41
0.456
11.40
0.086
2.15
199
2-φ 0.07
(1.80)
1.896
(47.40)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
0.79
(20.00)
0.24
(6.0)
0.16 ± 0.039
(4.00 ± 0.10)
1.25
(31.75)
Full R 2x
Z
Y
0.098
2.45
200
0.157 Min
(4.00 Min)
0.157 Min
(4.00 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.04 ± 0.0039
(1.00 ± 0.1)
Detail Z
0.102 Min
40 42
(2.55 Min)
2
0.018 ± 0.001
(0.45 ± 0.03)
0.01
(0.25)
0.024 TYP
(0.60 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOP
SDRAM Part No. : K4H561638D
Rev. 0.1 Jan. 2002
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