NB7L14 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer Multi−Level Inputs w/ Internal Termination http://onsemi.com MARKING DIAGRAM* Description ÇÇ ÇÇ The NB7L14 is a differential 1:4 LVPECL fanout buffer. The NB7L14 produces four identical LVPECL output copies of Clock or Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT Pin. This feature allows the NB7L14 to accept various logic standards, such as LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB7L14 is a member of the GigaComm™ family of high performance clock products. (Note: Microdot may be in either location) Features *For additional marking information, refer to Application Note AND8002/D. • • • • • • • • • • • • • • • Input Data Rate > 10.7 Gb/s Input Clock Frequency > 7 GHz 165 ps Typical Propagation Delay 45 ps Typical Rise and Fall Times <15 ps max Output Skew <0.8 ps maximum RMS Clock Jitter <15 ps pp of Data Dependent Jitter Differential LVPECL Outputs, 720 mV peak−to−peak, typical LVPECL Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V NECL Operating Range: VCC = 0 V with GND = −2.375 V to −3.6 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices 16 1 1 QFN−16 MN SUFFIX CASE 485G XXXX A L Y W G NB7L 14 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Q0 Q0 Q1 IN 50 W VT 50 W Q1 IN Q2 Q2 VREFAC Q3 Q3 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. 2 1 Publication Order Number: NB7L14MD NB7L14 GND Q0 16 IN 1 VT 2 15 Q0 VCC Exposed Pad (EP) 14 13 12 Q1 11 Q1 NB7L14 VREFAC 3 10 Q2 IN 4 9 5 6 7 8 GND Q3 Q3 VCC Q2 Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IN ECL, CML, LVCMOS, LVDS, LVTTL Input 2 VT − 3 VREFAC 4 IN ECL, CML, LVCMOS, LVDS, LVTTL Input 5 GND − 6 Q3 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 7 Q3 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 8 VCC − 9 Q2 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 10 Q2 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 11 Q1 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 12 Q1 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 13 VCC − 14 Q0 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 15 Q0 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V. 16 GND − Negative Supply Voltage − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically connected to device GND. Non−inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT Internal 50−W Termination Pin for IN/IN inputs. Output Reference Voltage for capacitor−coupled inputs Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT. Negative Supply Voltage Positive Supply Voltage Positive Supply Voltage 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN input, then, the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7L14 Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 3) Flammability Rating QFN−16 Oxygen Index: 28 to 34 Transistor Count > 2.0 V > 150 V Level 1 UL 94 V−0 @ 0.125 in 173 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIO Positive Input/Output Voltage GND = 0 V VINPP Differential Input Voltage |D − D| IIN Input Current Through RT (50 W Resistor) IOUT Output Current (LVPECL Output) IVFREFAC VREFAC Sink/Source Current TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 4) qJC Thermal Resistance (Junction−to−Case) (Note 4) Tsol Wave Solder Condition 2 Rating Unit −0.5 V to +4.0 V 4.0 V 2.8 V "40 mA 50 100 mA "1.5 mA −40 to +85 °C −65 to +150 °C QFN−16 QFN−16 42 35 °C/W QFN−16 4 °C/W 265 °C −0.5 v VIo v VCC + 0.5 Continuous Surge QFN−16 0 lfpm 500 lfpm Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L14 Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = 2.375 V to 3.6V, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min Typ Max Unit 2.375 3.0 2.5 3.3 2.625 3.6 V 85 105 mA POWER SUPPLY CURRENT VCC Power Supply Voltage VCC = 2.5 V VCC = 3.3 V ICC Power Supply Current (Inputs and Outputs Open) LVPECL OUTPUTS (Notes 5 & 6) VOH Output HIGH Voltage VOL Output LOW Voltage VCC = 2.5V VCC = 3.3V VCC – 1145 1355 2155 VCC – 900 1600 2400 VCC – 825 1675 2475 mV VCC = 2.5 V VCC = 3.3 V VCC – 2000 500 1300 VCC – 1700 800 1600 VCC – 1500 1000 1800 mV VCC mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7) VIH Single−ended Input HIGH Voltage Vth + 75 VIL Single−ended Input LOW Voltage GND Vth − 75 mV Vth Input Threshold Reference Voltage Range (Note 8) 1125 VCC − 75 mV VISE Single−ended Input Voltage Amplitude (VIH − VIL) 150 2800 mV VCC − 1000 mV VREFAC VREFAC VCC − 1400 Output Reference Voltage (100 mA Load) VCC − 1300 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 50 mV VID Differential Input Voltage (VIHD − VILD) 100 2800 mV VCMR Input Common Mode Range (Differential Configuration) (Note 10) (Figure 9) 950 VCC − 50 mV IIH Input HIGH Current IN / IN, (VT Open) −150 150 mA IIL Input LOW Current IN / IN, (VT Open) −150 150 mA 55 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor 45 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVPECL outputs loaded with 50 W to VCC − 2.0 V for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7L14 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C ; (Note 11) Symbol Min Typ fMAX Maximum Input Clock Frequency; VOUT w 400 mV Characteristic 7 8 GHz fDATAMAX Maximum Operating Data Rate; NRZ, (PRBS23) 10 11 Gbps VOUTPP Output Voltage Amplitude (Note 15) (See Figure 9) 500 400 720 450 mV tPLH, tPHL Propagation Delay IN to Q 125 165 200 ps tSKEW Duty Cycle Skew (Note 12) Output – Output Within Device Skew Device to Device Skew 3 15 15 50 ps tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) 50 55 % tJITTER RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14) 0.5 5 0.8 15 VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) tr tf Output Rise/Fall Times @ 1.0 GHz (20% − 80%) fin v 5 GHz fin ≤ 7 GHz fin v 7 GHz 45 fin v 7 GHz fin v 10.7 Gb/s 100 Qx, Qx 30 45 Max Unit ps rms ps pk−pk 1200 mV 60 ps OUTPUT VOLTAGE AMPLITUDE (mV) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured by forcing VINPP(min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates 40 ps (20% − 80%). 12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. 800 VCC Q AMP (mV) 700 600 IN 500 50 W VT 400 300 50 W IN 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fin, Clock Input Frequency (GHz) Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure http://onsemi.com 5 NB7L14 IN VIH Vth IN VIL IN IN Vth Figure 5. Differential Input Driven Single−Ended VCC Vthmax Figure 6. Differential Inputs Driven Differentially VIHmax VILmax VIH Vth VIL Vth IN IN VIHmin Vthmin Figure 7. Vth Diagram VCC VILD Figure 8. Differential Inputs Driven Differentially VIHDmax VCMmax IN VILDmax IN VCMR IN GND VIHD VILmin GND VCMmin VID = |VIHD(IN) − VILD(IN)| IN VIHDtyp VID = VIHD − VILD VINPP = VIH(IN) − VIL(IN) Q VILDtyp Q VIHDmin VOUTPP = VOH(Q) − VOL(Q) tPHL VILDmin tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement http://onsemi.com 6 NB7L14 VCC VCC NB7L14 ZO = 50 W LVPECL Driver VCC VCC ZO = 50 W IN 50 W VT = VCC − 2 V ZO = 50 W LVDS Driver 50 W 50 W 50 W IN Figure 11. LVPECL Interface GND GND VCC VCC VCC VCC ZO = 50 W IN 50 W VT = VCC ZO = 50 W Differential Driver 50 W NB7L14 IN 50 W VT = VREFAC* ZO = 50 W IN GND GND Figure 12. LVDS Interface NB7L14 ZO = 50 W CML Driver IN VT = Open ZO = 50 W IN GND NB7L14 50 W IN GND GND GND Figure 14. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) Figure 13. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor VCC VCC ZO = 50 W Single−Ended Driver VT = VREFAC* NB7L14 IN 50 W 50 W IN (open) GND GND Figure 15. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 7 NB7L14 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NB7L14MNG QFN−16 (Pb−Free) 123 Units / Rail NB7L14MNTXG QFN−16 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB7L14 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D ÇÇÇ ÇÇÇ ÇÇÇ L1 DETAIL A PIN 1 LOCATION ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.15 C TOP VIEW 0.15 C A3 MOLD CMPD A1 DETAIL B (A3) DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG L L A B ÉÉ ÇÇ ÇÇ DIM A A1 A3 b D D2 E E2 e K L L1 ALTERNATE CONSTRUCTIONS A 16 X SEATING PLANE 0.08 C SIDE VIEW 16X L DETAIL A 5 8 0.575 0.022 e EXPOSED PAD 4 9 1 12 3.25 0.128 0.30 0.012 EXPOSED PAD E2 K 16 16X e 1.50 0.059 3.25 0.128 13 b 0.10 C A B 0.05 C SOLDERING FOOTPRINT* C D2 NOTE 5 16X A1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Components Industries LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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