NCP5422A Dual Out−of−Phase Synchronous Buck Controller with Current Limit The NCP5422A is a dual N−channel synchronous buck regulator controller. It contains all the circuitry required for two independent buck regulators and utilizes the V2 control method to achieve the fastest possible transient response and best overall regulation, while using the least number of external components. The NCP5422A features out−of−phase synchronization between the channels, reducing the input filter requirement. The NCP5422A also provides undervoltage lockout, Soft Start, built in adaptive non−overlap time and hiccup mode overcurrent protection. http://onsemi.com SO−16 AD SUFFIX CASE 751B 16 1 PIN CONNECTIONS AND MARKING DIAGRAMS Features V2 Control Topology Hiccup Mode Overcurrent Protection 150 ns Transient Response Programmable Soft Start 100% Duty Cycle for Enhanced Transient Response 150 kHz to 600 kHz Programmable Frequency Operation Switching Frequency Set by Single Resistor Out−Of−Phase Synchronization Between Channels Undervoltage Lockout Both Gate Drive Outputs Held Low During Fault Condition SO−16 16 1 GATE(H)1 GATE(L)1 GND BST IS+1 IS−1 VFB1 COMP1 A WL Y WW NCP5422A AWLYWW • • • • • • • • • • GATE(H)2 GATE(L)2 VCC ROSC IS+2 IS−2 VFB2 COMP2 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device NCP5422ADR2 Package Shipping† SO−16 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2003 November, 2003 − Rev. 4 1 Publication Order Number: NCP5422A/D NCP5422A 12 V R10 Q5 2N3904 220 1.5 V/10 A + C11−C13 3 × 680 F/4.0 V L2 1.3 H Q4 MTD3302 R3 2.0 k R4 C7 0.1 F 2.0 k C15 0.1 F R7 5.0 k ± 1.0% C17 100 pF R8 10 k ± 1.0% D1 C4 0.2 F 18 V MA3180 C3 1.0 F Q3 MTD3302 MBR0530T MBR0530T1 D2 C5 Q1 MTD3302 4 VCC BST 1 16 GATE(H)2 GATE(H)1 GATE(L)2 GATE(L)1 12 IS+2 9 Q2 MTD3302 COMP1 2.0 k 0.1 F R2 2.0 k 8 10 C14 0.1 F GND 3 R5 VFB1 7 R9 30.9 k 8.0 k ± 1.0% R6 10 k±1.0% C16 100 PF Figure 1. Application Diagram, 12 V to 1.5 V/10 A and 1.8 V/10 A Converter http://onsemi.com 2 + C8−C10 3 × 680 F/4.0 V C6 IS−1 6 COMP2 1.8 V/10 A 1.3 H R1 IS+1 5 IS−2 VFB2 13 R OSC L1 2 NCP5422A 11 C1−C2 2 × 220 F 0.2 F 14 15 + NCP5422A ABSOLUTE MAXIMUM RATINGS* Rating Value Unit 150 °C −65 to +150 °C ESD Susceptibility (Human Body Model) 2.0 kV Package Thermal Resistance, SO−16: Junction−to−Case, RJC Junction−to−Ambient, RJA 28 115 °C/W °C/W 230 peak °C Operating Junction Temperature, TJ Storage Temperature Range, TS Lead Temperature Soldering: Reflow: (Note 1) 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ABSOLUTE MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK VCC IC Power Input 16 V −0.3 V N/A 1.5 A peak 200 mA DC COMP1, COMP2 Compensation Capacitor for Channel 1 or 2 4.0 V −0.3 V 1.0 mA 1.0 mA VFB1, VFB2 Voltage Feedback Input for Channel 1 or 2 5.0 V −0.3 V 1.0 mA 1.0 mA BST Power Input for GATE(H)1, 2 20 V −0.3 V N/A 1.5 A peak 200 mA DC ROSC Oscillator Resistor 4.0 V −0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High−Side FET Driver for Channel 1 or 2 20 V −2.0 V for 100 ns −0.3 V DC 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC GATE(L)1, GATE(L)2 Low−Side FET Driver for Channel 1 or 2 16 V −2.0 V for 100 ns −0.3 V DC 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC GND Ground 0V 0V 1.5 A peak 200 mA DC N/A IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V −0.3 V 1.0 mA 1.0 mA IS−1, IS−2 Negative Current Sense for Channel 1 or 2 6.0 V −0.3 V 1.0 mA 1.0 mA http://onsemi.com 3 NCP5422A ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 F, 10.8 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit − 0.5 1.6 A 0 − 1.1 V Error Amplifier VFB1(2) Bias Current VFB1(2) = 0 V VFB1(2) Input Range − COMP1,2 Source Current COMP1,2 = 1.2 V to 2.5 V; VFB1(2) = 0.8 V 15 30 60 A COMP1,2 Sink Current COMP1,2 = 1.2 V; VFB1(2) = 1.2 V 15 30 60 A Reference Voltage 1(2) COMP1 = VFB1; COMP2 = VFB2 0.980 1.000 1.020 V COMP1,2 Max Voltage VFB1(2) = 0.8 V 3.0 3.3 − V COMP1,2 Min Voltage VFB1(2) = 1.2 V − 0.25 0.35 V Open Loop Gain − − 95 − dB Unity Gain Band Width − − 40 − kHz PSRR @ 1.0 kHz − − 70 − dB Transconductance − − 32 − mmho Output Impedance − − 2.5 − M GATE(H) and GATE(L) High Voltage (AC) Measure: VCC − GATE(L)1,2; BST − GATE(H)1,2; Note 2 − 0 0.5 V Low Voltage (AC) Measure:GATE(L)1,2 or GATE(H)1,2; Note 2 − 0 0.5 V Rise Time 1.0 V < GATE(L)1,2 < VCC − 1.0 V 1.0 V < GATE(H)1,2 < BST − 1.0 V, BST ≤ 14 V − 20 50 ns Fall Time VCC − 1.0 > GATE(L)1,2 > 1.0 V BST − 1.0 > GATE(H)1,2 > 1.0 V, BST ≤ 14 V − 15 50 ns GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V BST ≤ 14 V 20 40 70 ns GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V; BST ≤ 14 V 20 40 70 ns GATE(H)1(2) and GATE(L)1(2) pull−down. Resistance to GND Note 2 50 125 280 k 0.30 0.425 0.55 V PWM Comparator PWM Comparator Offset VFFB1(2) = 0 V; Increase COMP1,2 until GATE(H)1,2 starts switching Artificial Ramp Duty cycle = 50%, Note 2 40 70 100 mV Minimum Pulse Width Note 2 − − 300 ns Oscillator Switching Frequency ROSC = 61.9 k; Measure GATE(H)1; Note 2 112 150 188 kHz Switching Frequency ROSC = 30.9 k; Measure GATE(H)1 250 300 350 kHz Switching Frequency ROSC = 15.1 k; Measure GATE(H)1; Note 2 450 600 750 kHz ROSC Voltage ROSC = 30.9 k, Note 2 0.970 1.000 1.030 V − 180 − ° Phase Difference − http://onsemi.com 4 NCP5422A ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 F, 10.8 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Supply Currents VCC Current COMP1,2 = 0 V (No Switching) − 13 17 mA BST Current COMP1,2 = 0 V (No Switching) − 3.5 6.0 mA Undervoltage Lockout Start Threshold GATE(H) Switching; COMP1,2 charging 7.8 8.6 9.4 V Stop Threshold GATE(H) not switching; COMP1,2 discharging 7.0 7.8 8.6 V Hysteresis Start−Stop 0.5 0.8 1.5 V 0 V < IS+ 1(2) < 5.5 V, 0 V < IS− 1(2) < 5.5 V 55 70 85 mV − 0.20 0.25 0.30 V Hiccup Mode Overcurrent Protection OVC Comparator Offset Voltage Discharge Threshold IS+ 1(2) Bias Current 0 V < IS+ 1(2) < 5.5 V −1.0 0.1 1.0 A IS− 1(2) Bias Current 0 V < IS− 1(2) < 5.5 V −1.0 0.1 1.0 A OVC Common Mode Range Note 2 0 − 5.5 V OVC Latch COMP1 Discharge Current COMP1 = 1.0 V 2.0 5.0 8.0 A OVC Latch COMP2 Discharge Current COMP2 = 1.0 V 0.3 1.2 3.5 mA 5.0 6.0 7.0 − COMP1 Charge/Discharge Ratio in OVC − 2. Guaranteed by design, not 100% tested in production. http://onsemi.com 5 NCP5422A PACKAGE PIN DESCRIPTION PIN NO. PIN SYMBOL FUNCTION 1 GATE(H)1 High Side Switch FET driver pin for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC. 4 BST Power input for GATE(H)1 and GATE(H)2 pins. 5 IS+1 Positive input for channel 1 overcurrent comparator. 6 IS−1 Negative input for channel 1 overcurrent comparator. 7 VFB1 Error amplifier inverting input for channel 1. 8 COMP1 Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation. The same capacitor provides Soft Start timing for channel 1. This pin also disables the channel 1 output when pulled below 0.3 V. 9 COMP2 Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation and Soft Start timing for channel 2. Channel 2 output is disabled when this pin is pulled below 0.3 V. 10 VFB2 Error amplifier inverting input for channel 2. 11 IS−2 Negative input for channel 2 overcurrent comparator. 12 IS+2 Positive input for channel 2 overcurrent comparator. 13 ROSC Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency. 14 VCC 15 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16 GATE(H)2 High Side Switch FET driver pin for channel 2. Input Power supply pin. http://onsemi.com 6 NCP5422A VCC ROSC BIAS − + VCC + 8.6 V − 7.8 V CURRENT SOURCE GEN RAMP2 RAMP1 BST IS+1 CLK1 + IS−1 PWM Comparator 1 + − 70 mV S − + FAULT Set Dominant RAMP1 BST − + + − 0.25 V Reset Dominant FAULT non−overlap VCC GATE(L)2 R FAULT RAMP2 E/A OFF GND E/A OFF 0.425 V 1.2 mA − E/A1 + − − + E/A2 1.0 V VFB1 GATE(H)2 S PWM Comparator 2 1.0 V GATE(L)1 FAULT 0.425 V R 5.0 A non−overlap VCC GATE(H)1 R Q FAULT − + − + IS−2 S Reset Dominant 70 mV + IS+2 CLK2 − + − BST OSC COMP1 VFB2 COMP2 Figure 2. Block Diagram http://onsemi.com 7 FAULT NCP5422A APPLICATIONS INFORMATION THEORY OF OPERATION time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation is drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulations. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity particularly at higher duty cycle (above 50%). The NCP5422A is a dual power supply controller that utilizes the V2 control method. Two synchronous V2 buck regulators can be built using a single controller. The fixed−frequency architecture, driven from a common oscillator, ensures a 180° phase differential between channels. V2 Control Method The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current. − GATE(H) PWM + GATE(L) RAMP Slope Compensation Output Voltage Error Amplifier VFB − COMP Error Signal + Reference Voltage Figure 3. V2 Control with Slope Compensation Start Up The V2 control method is illustrated in Figure 3. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch to 0% or 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction The NCP5422A features a programmable Soft Start function, which is implemented through the Error Amplifier and the external Compensation Capacitor. This feature prevents stress to the power components and overshoot of the output voltage during start−up. As power is applied to the regulator, the NCP5422A Undervoltage Lockout circuit (UVL) monitors the IC’s supply voltage (VCC). The UVL circuit prevents the MOSFET gates from switching until VCC exceeds the 8.6 V threshold. A hysteresis function of 800 mV improves noise immunity. The Compensation Capacitor connected to the COMP pin is charged by a 30 A current source. When the capacitor voltage exceeds the 0.425 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated turning on the upper MOSFET. The current then ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the http://onsemi.com 8 NCP5422A instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, several high frequency and bulk output capacitors are usually used. 0.40 V PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse. VIN 8.6 V Out−of−Phase Synchronization In out−of−phase synchronization, the turn−on of the second channel is delayed by half the switching cycle. This delay is supervised by the oscillator, which supplies a clock signal to the second channel which is 180° out of phase with the clock signal of the first channel. The advantages of out−of−phase synchronization are many. Since the input current pulses are interleaved with one another, the overlap time is reduced. The effect of this overlap reduction is to reduce the input filter requirement, allowing the use of smaller components. In addition, since peak current occurs during a shorter time period, emitted EMI is also reduced, thereby reducing shielding requirements. VCOMP 0.45 V VFB GATE(H)1 GATE(H)2 UVLO STARTUP tS NORMAL OPERATION Figure 4. Idealized Waveforms Normal Operation During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation. Overvoltage Protection Overvoltage Protection (OVP) is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 150 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases. Gate Charge Effect on Switching Times When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading, according to the following graphs. Average Fall Time Hiccup Overcurrent Protection A lossless hiccup mode short circuit protection feature is provided on the chip. The only external component required is the COMP1 capacitor. Any overcurrent condition results in the immediate shutdown of both output phases. Both the upper and lower gate drives are driven low, turning off both MOSFETs. A comparator between the IS+ and IS− on each output phase detects a short circuit when the voltage difference between the two pins exceeds 70 mV and sets the fault latch. The fault latch immediately turns off the error amplifier and discharges both COMP capacitors. The capacitor connected to COMP1 is discharged through a 5.0 A current sink in order to provide timing for the reset cycle. When COMP1 has fallen below 0.25 V, a comparator resets the fault latch and error amplifier 1 begins to charge COMP1 with a 30 A source current. When COMP1 exceeds the feedback voltage plus the PWM Comparator offset voltage, the normal switching cycle will resume. If the short circuit condition persists through the restart cycle, the overcurrent reset cycle will repeat itself until the short circuit is removed, resulting in small hiccup output pulses while the COMP capacitor charges, as shown in Figure 6. Average Rise Time 90 Fall/Rise Time (ns) 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 Load (nF) Figure 5. Average Rise and Fall Times Transient Response The 150 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse−by−pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed http://onsemi.com 9 NCP5422A Selecting Feedback Divider Resistors VOUT R1 VFB R2 Figure 7. Selecting Feedback Divider Resistors Selection of Feedback Divider Resistors Feedback divider resistors R1 and R2 are selected based on a design trade−off between efficiency and output voltage accuracy. Both error amplifiers are referenced to 1.0 V, and resistors R1 and R2 are connected from each channel’s output voltage to the inverting pin (VFB1(2)) of each error amplifier. To set the channel output voltage, first choose a value for R1, and then R2 can be sized as follows: Figure 6. Hiccup Overcurrent Protection Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. The COMP pins must be driven below the 0.425 V PWM comparator offset voltage in order to disable the switching of the GATE drivers. R2 R1 Vout 1 1.0 The output voltage error due to the bias current of the error amplifier and the parallel combination of R1 and R2 can now be estimated: DESIGN GUIDELINES Definition of the design specifications Error 1.6 · 10−6 · R1 · R2 R1 R2 The output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; 3. output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an output voltage that will meet the specified tolerance at the load. The designer must also ensure that the regulator component temperatures are kept within the manufacturer’s specified ratings at full load and maximum ambient temperature. Reducing the size of R1 and R2 will reduce the output voltage error, but increase the power dissipation. Calculating Duty Cycle The duty cycle of a buck converter (including parasitic losses) is given by the formula: Duty Cycle D VOUT VLFET VL VIN VLFET VHFET where: VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance; VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON). http://onsemi.com 10 NCP5422A Selecting the Switching Frequency The minimum value of inductance which prevents inductor saturation or exceeding the rated FET current can be calculated as follows: Selecting the switching frequency is a trade−off between component size and power losses. Operation at higher switching frequencies allows the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. The value of the oscillator resistor is designed to be linearly related to the switching period. If the designer prefers not to use Figure 8 to select the necessary resistor, the following equation quite accurately predicts the proper resistance for room temperature conditions. ROSC (VIN(MIN) VOUT) VOUT LMIN fSW VIN(MIN) ISW(MAX) where: LMIN = minimum inductance value; VIN(MIN) = minimum design input voltage; VOUT = output voltage; fSW = switching frequency; ISW(MAX) − maximum design switch current. The inductor ripple current can then be determined: V (1 D) IL OUT L fSW 21700 fSW 2.31 fSW where: IL = inductor ripple current; VOUT = output voltage; L = inductor value; D = duty cycle. fSW = switching frequency The designer can now verify if the number of output capacitors will provide an acceptable output voltage ripple (1.0% of output voltage is common). The formula below is used: where: ROSC = oscillator resistor in k; fSW = switching frequency in kHz. 800 Frequency (kHz) 700 600 VOUT IL ESRMAX 500 Rearranging we have: 400 ESRMAX 300 200 100 10 20 30 40 50 VOUT IL where: ESRMAX = maximum allowable ESR; VOUT = 1.0% × VOUT = maximum allowable output voltage ripple ( budgeted by the designer ); IL = inductor ripple current; VOUT = output voltage. The number of output capacitors is determined by: 60 ROSC (k) Figure 8. Switching Frequency Selection of the Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. There are many factors to consider in selecting the inductor including cost, efficiency, EMI and ease of manufacture. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. There are a variety of materials and types of magnetic cores that could be used for this application. Among them are ferrites, molypermalloy cores (MPP), amorphous and powdered iron cores. Powdered iron cores are very commonly used. Powdered iron cores are very suitable due to its high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low EMI. Number of capacitors ESRCAP ESRMAX where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform): I IL(PEAK) IOUT L 2 where: IL(PEAK) = inductor peak current; IOUT = load current; IL = inductor ripple current. I IL(VALLEY) IOUT L 2 http://onsemi.com 11 NCP5422A ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula: where: IL(VALLEY) = inductor valley current. Input Capacitor Selection The choice and number of input capacitors is determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst case input voltage with an adequate margin. To calculate the number of input capacitors one must first determine the RMS ripple current through the capacitors. To this end, first calculate the average input current to the converter: V · I V2 · I2 where is the expected Iin(Avg) 1 1 · Vin efficiency (typical 85%) With the average input current determined, the RMS ripple current through the input capacitor will be: Irms ESRMAX Ip12 Ip22 Io12 · D1 Io22 · D2−Iin2 3 3 where: VESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: where: Io1,2 is the maximum DC output current for channel 1 and 2 respectively. Ip1,2 is the peak inductor current (1/2 IL) for channel’s 1 and 2 respectively. If the channel peak inductor current is less than 50% of the channel output current it may be neglected. D1,2 is the channel duty cycle. Here it is assumed that each channel’s duty cycle is less than 50% so that each phase does not overlap. Once the RMS ripple current has been determined, the required number of input capacitor’s needed is based on the rated RMS ripple current rating of the chosen capacitor. Number of capacitors ESRCAP ESRMAX where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: VESR IOUT ESRMAX Selection of the Output Capacitors Similarly, the maximum allowable ESL is calculated from the following formula: These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: VESR IOUT ESLMAX VESL t I Selection of the Input Inductor A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. t VOUT IOUT ESL ESR TR t COUT where: IOUT / t = load current slew rate; IOUT = load transient; t = load transient duration time; http://onsemi.com 12 NCP5422A will be driven rail−to−rail due to overshoot caused by the capacitive load they present to the controller IC. The minimum inductance value for the input inductor is therefore: V LIN (dIdt)MAX Selection of the Switching (Upper) FET The designer must ensure that the total power dissipation in the FET switch does not cause the power component to exceed it’s maximum rating. The maximum RMS current through the switch can be determined by the following formula: where: LIN = input inductor value; V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double−pole network with a slope of −2.0, a roll−off rate of −40 dB/dec, and a corner frequency: fC IRMS(H) IL(PEAK)2 (IL(PEAK) IL(VALLEY)) IL(VALLEY)2 D 3 where: IRMS(H) = maximum switching MOSFET RMS current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current; D = duty cycle. Once the RMS current through the switch is known, the switching MOSFET conduction losses can be calculated: 1 2 LC where: L = input inductor; C = input capacitor(s). PRMS(H) IRMS(H)2 RDS(ON) SELECTION OF THE POWER FETS where: PRMS(H) = switching MOSFET conduction losses; IRMS(H) = maximum switching MOSFET RMS current; RDS(ON) = FET drain−to−source on−resistance The upper MOSFET switching losses are caused during MOSFET switch−on and switch−off and can be determined by using the following formula: FET Basics The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOSFET are considered to be those of a perfect switch. Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of VGS, and the faster the turn−on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn−on switching losses, 4) turn−off switching losses, and 5) gate−transitions losses. The latter three losses are proportional to frequency. The most important aspect of FET performance is the Static Drain−To−Source On−Resistance (RDS(ON)), which affects regulator efficiency and FET thermal management requirements. The On−Resistance determines the amount of current a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the continuous rating, the On−Resistance also increases. Its positive temperature coefficient is between +0.6%/°C and +0.85%/°C. The higher the On−Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. Both logic level and standard FETs can be used. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates PSWH PSWH(ON) PSWH(OFF) V IOUT (tRISE tFALL) IN 6T where: PSWH(ON) = upper MOSFET switch−on losses; PSWH(OFF) = upper MOSFET switch−off losses; VIN = input voltage; IOUT = load current; tRISE = MOSFET rise time (from FET manufacturer’s switching characteristics performance curve); tFALL = MOSFET fall time (from FET manufacturer’s switching characteristics performance curve); T = 1/fSW = period. The total power dissipation in the switching MOSFET can then be calculated as: PHFET(TOTAL) PRMS(H) PSWH(ON) PSWH(OFF) where: PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMS(H) = upper MOSFET switch conduction Losses; PSWH(ON) = upper MOSFET switch−on losses; PSWH(OFF) = upper MOSFET switch−off losses; Once the total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ TA [PHFET(TOTAL) RJA] http://onsemi.com 13 NCP5422A The IC power dissipation is determined by the formula: where: TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RJA = upper FET junction−to−ambient thermal resistance. PCONTROL(IC) ICC1VCC1 IBSTVBST PGATE(H)1 PGATE(L)1 PGATE(H)2 PGATE(L)2 where: PCONTROL(IC) = control IC power dissipation; ICC1 = IC quiescent supply current; VCC1 = IC supply voltage; PGATE(H) = upper MOSFET gate driver (IC) losses; PGATE(L) = lower MOSFET gate driver (IC) losses. The upper (switching) MOSFET gate driver (IC) losses are: Selection of the Synchronous (Lower) FET The switch conduction losses for the lower FET can be calculated as follows: PRMS(L) IRMS2 RDS(ON) [IOUT (1 D)]2 RDS(ON) where: PRMS(L) = lower MOSFET conduction losses; IOUT = load current; D = Duty Cycle; RDS(ON) = lower FET drain−to−source on−resistance. The synchronous MOSFET has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. The MOSFET body diode will conduct during the non−overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: PGATE(H) QGATE(H) fSW VBST where: PGATE(H) = upper MOSFET gate driver (IC) losses; QGATE(H) = total upper MOSFET gate charge at VCC; fSW = switching frequency; The lower (synchronous) MOSFET gate driver (IC) losses are: PGATE(L) QGATE(L) fSW VCC where: PGATE(L) = lower MOSFET gate driver (IC) losses; QGATE(L) = total lower MOSFET gate charge at VCC; fSW = switching frequency; The junction temperature of the control IC is primarily a function of the PCB layout, since most of the heat is removed through the traces connected to the pins of the IC. PSWL VSD ILOAD non−overlap time fSW where: PSWL = lower FET switching losses; VSD = lower FET source−to−drain voltage; ILOAD = load current; Non−overlap time = GATE(L)−to−GATE(H) or GATE(H)−to−GATE(L) delay (from NCP5422A data sheet Electrical Characteristics section); fSW = switching frequency. The total power dissipation in the synchronous (lower) MOSFET can then be calculated as: Current Sensing The current supplied to the load can be sensed easily using the IS+ and IS− pins for the output. These pins sense a voltage, proportional to the output current, and compare it to a fixed internal voltage threshold. When the differential voltage exceeds 70 mV, the internal overcurrent protection system goes into hiccup mode. Two methods for sensing the current are available. Sense Resistor. A sense resistor can be added in series with the inductor. When the voltage drop across the sense resistor exceeds the internal voltage threshold of 70 mV, a fault condition is set. The sense resistor is selected according to: PLFET(TOTAL) PRMS(L) PSWL where: PLFET(TOTAL) = Synchronous (lower) FET total losses; PRMS(L) = Switch Conduction Losses; PSWL = Switching losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction temperature can be calculated: RSENSE 0.070 V ILIMIT TJ TA [PLFET(TOTAL) RJA] In a high current supply, the sense resistor will be a very low value, typically less than 10 m. Such a resistor can be either a discrete component or a PCB trace. The resistance value of a discrete component can be more precise than a PCB trace, but the cost is also greater. Setting the current limit using an external sense resistor is very precise because all the values can be designed to specific tolerances. However, the disadvantage of using a sense resistor is its additional constant power loss and heat generation. where: TJ = MOSFET junction temperature; TA = ambient temperature; PLFET(TOTAL) = total synchronous (lower) FET losses; RJA = lower FET junction−to−ambient thermal resistance. Control IC Power Dissipation The power dissipation of the IC varies with the MOSFETs used, VCC, and the NCP5422A operating frequency. The average MOSFET gate charge current typically dominates the control IC power dissipation. http://onsemi.com 14 NCP5422A voltage ripple. The consequence is, however, that very little voltage ramp exists at the control IC feedback pin (VFB), resulting in increased regulator sensitivity to noise and the potential for loop instability. In applications where the internal slope compensation is insufficient, the performance of the NCP5422A−based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off−time. Referring to Figure 10, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2. Inductor ESR. Another means of sensing current is to use the intrinsic resistance of the inductor. A model of an inductor (Figure 9) reveals that the windings of an inductor have an effective series resistance (ESR). The voltage drop across the inductor ESR can be measured with a simple parallel circuit: an RC integrator. If the value of RS1 and C are chosen such that: L R C S1 ESR then the voltage measured across the capacitor C will be: VC ESR ILIM Selecting Components. Select the capacitor C first. A value of 0.1 F is recommended. The value of RS1 can be selected according to: RS1 VSLOPECOMP VGATE(L) ILIM 0.070 V ESR L −t where: VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = tON or tOFF (switch off−time); = RC constant determined by C1 and the parallel combination of R1, R2 neglecting the low driver output impedance. 1 ESR C Typical values for inductor ESR range in the low m. Consult manufacturer’s datasheet for specific details. Selection of components at these values will result in a current limit of: VCC R1 R2 (1 e ) R2 ESR COMP GATE(H) RS1 C CCOMP Co NCP5422A GATE(L) R2 C1 R1 IS+ IS− GATE(L) Figure 9. Inductor ESR Current Sensing To Synchronous FET Figure 10. Small RC Filter Provides the Proper Voltage Ramp at the Beginning of Each On−Time Cycle Given an ESR value of 3.5 m, the current limit becomes 20 A. If an increased current limit is required, a resistor divider can be added. The advantages of setting the current limit by using the winding resistance of the inductor are that efficiency is maximized and heat generation is minimized. The tolerance of the inductor ESR must be factored into the design of the current limit. Finally, one or two more components are required for this approach than with resistor sensing. Note that, in the example of Figure 9, the IS+ input bias current flowing through RS1 will introduce a small offset error. If RS1 = 4 k, at the maximum bias current limit of 1 A, the error will be 4 mV. This error can be avoided by using two separate resistors, each half the calculated value, as shown (R1 through R4) in the typical application circuit of Figure 1. The artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the RC filter time constant is smaller than the off−time cycle duration (time during which the lower MOSFET is conducting). It is important that the series combination of R1 and R2 is high enough in resistance to avoid loading the GATE(L) pin. Also, C1 should be very small (less than a few nF) to avoid heating the part. EMI MANAGEMENT As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the Adding External Slope Compensation Today’s voltage regulators are expected to meet very stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low ESR. Low ESR at the regulator output results in low output http://onsemi.com 15 NCP5422A 6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The MOSFET gate traces to the IC must be short, straight, and wide as possible. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching MOSFET as close to the input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the COMP capacitor as close as possible to the COMP pin. 12. Connect the filter components of the following pins: ROSC, VFB, VOUT, and COMP to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 13. Place the VCC bypass capacitors as close as possible to the IC. 14. Place the ROSC resistor as close as possible to the ROSC pin. 15. Include provisions for 100−100pF capacitor across each resistor of the feedback network to improve noise immunity and add COMP. 16. Assign the output with lower duty cycle to channel 2, which has better noise immunity. board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. LAYOUT GUIDELINES When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the NCP5422A. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. 4. For high power buck regulators on double−sided PCB’s a single ground plane (usually the bottom) is recommended. 5. Even though double sided PCB’s are usually sufficient for a good layout, four−layer PCB’s are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and GND planes, the top layer for power connections and component vias, and the bottom layers for the noise sensitive traces. http://onsemi.com 16 NCP5422A PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 17 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 NCP5422A V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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