NCP5351 4 A Synchronous Buck Power MOSFET Driver The NCP5351 is a dual MOSFET gate driver optimized to drive the gates of both high−side and low−side Power MOSFETs in a Synchronous Buck converter. The NCP5351 is an excellent companion to multiphase controllers that do not have integrated gate drivers, such as ON Semiconductor’s CS5323, CS5305 or CS5307. This architecture provides a power supply designer the flexibility to locate the gate drivers close to the MOSFETs. The 4.0 A drive capability makes the NCP5351 ideal for minimizing switching losses in MOSFETs with large input capacitance. Optimized internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate MOSFET drain voltages as high as 25 V. Both gate outputs can be driven low, and supply current reduced to less than 25 A, by applying a low logic level to the Enable (EN) pin. An undervoltage lockout function ensures that both driver outputs are low when the supply voltage is low, and a thermal shutdown function provides the IC with overtemperature protection. The NCP5351 is pin−to−pin compatible with the SC1205 and is available in a standard SO−8 package and thermally enhanced QFN−10. http://onsemi.com MARKING DIAGRAMS 8 1 • • • • 4.0 A Peak Drive Current Rise and Fall Times < 15 ns Typical into 6000 pF Propagation Delay from Inputs to Outputs < 20 ns Adaptive Nonoverlap Time Optimized for Large Power MOSFETs Floating Top Driver Accommodates Applications Up to 25 V Undervoltage Lockout to Prevent Switching when the Input Voltage is Low Thermal Shutdown Protection Against Overtemperature < 1.0 mA Quiescent Current − Enabled 25 A Quiescent Current − Disabled Internal TG to DRN Pulldown Resistor Prevents HV Supply−Induced Turn On of High−Side MOSFET 5351 ALYW 1 10 QFN−10 MN SUFFIX CASE 485C 1 A L Y W Features • • • • • • SO−8 D SUFFIX CASE 751 8 5351 ALYW 1 = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS DRN 1 SO−8 8 PGND TG BST BG VS CO EN QFN−10 1 DRN TG N/C BST CO 10 GND BG N/C VS EN ORDERING INFORMATION Package Shipping† NCP5351D SO−8 98 Units/Rail NCP5351DR2 SO−8 2500 Tape & Reel QFN−10 2500 Tape & Reel Device NCP5351MNR2 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 9 1 Publication Order Number: NCP5351/D NCP5351 BST Level Shifter + − VS + − TG 4.25 V DRN Delay Nonoverlap Control + − EN 4.0 V Delay Thermal Shutdown VS BG CO PGND Figure 1. Block Diagram Table 1. Input−Output Truth Table EN CO DRN TG BG L X X L L H L < 3.0 V L H H H < 3.0 V H L H L > 5.0 V L L H H > 5.0 V H L VCO tpdlTG tpdlBG tfTG VTG−VDRN trTG tpdhTG (Nonoverlap) VBG trBG tfBG tpdhBG (Nonoverlap) VDRN 4.0 V Figure 2. Timing Diagram http://onsemi.com 2 NCP5351 PACKAGE PIN DESCRIPTION Pin Number SO−8 QFN−10 Pin Symbol Description 1 1 DRN The switching node common to the high and low−side FETs. The high−side (TG) driver and supply (BST) are referenced to this pin. 2 2 TG Driver output to the high−side MOSFET gate. 3 4 BST Bootstrap supply voltage input. In conjunction with a Schottky diode to VS, a 0.1 F to 1.0 F ceramic capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG). 4 5 CO Logic level control input produces complementary output states − no inversion at TG; inversion at BG. − 3, 8 N/C Not Connected. 5 6 EN Logic level enable input forces TG and BG low, and supply current to 10 A when EN is low. 6 7 VS Power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from this pin to PGND. 7 9 BG Driver output to the low−side (synchronous rectifier) MOSFET gate. 8 − PGND Ground. − 10 GND Ground. http://onsemi.com 3 NCP5351 MAXIMUM RATINGS Rating Value Unit Operating Junction Temperature, TJ Internally Limited °C Package Thermal Resistance: SO−8 Junction−to−Case, RJC Junction−to−Ambient, RJA 45 165 °C/W °C/W −65 to 150 °C 230 peak °C 1 − Storage Temperature Range, TS Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) MSL Rating Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. 60 seconds maximum above 183°C. MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK VS Main Supply Voltage Input 6.3 V −0.3 V NA 4.0 A Peak (< 100 s) 250 mA DC BST Bootstrap Supply Voltage Input 25 V wrt/PGND 6.3 V wrt/DRN −0.3 V wrt/DRN NA 4.0 A Peak (< 100 s) 250 mA DC DRN Switching Node (Bootstrap Supply Return) 25 V −1.0 V DC −5.0 V for 100 ns −6.0 V for 20 ns 4.0 A Peak (< 100 s) 250 mA DC NA TG High−Side Driver Output (Top Gate) 25 V wrt/PGND 6.3 V wrt/DRN −0.3 V wrt/DRN 4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC BG Low−Side Driver Output (Bottom Gate) 6.3 V −0.3 V 4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC CO TG & BG Control Input 6.3 V −0.3 V 1.0 mA 1.0 mA EN Enable Input 6.3 V −0.3 V 1.0 mA 1.0 mA PGND Ground 0V 0V 4.0 A Peak (< 100 s) 250 mA DC NA NOTE: All voltages are with respect to PGND except where noted. http://onsemi.com 4 NCP5351 ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C; VS = 5.0 V; 4.0 V < VBST < 25 V; VEN = VS; unless otherwise noted) Parameter Test Conditions Min Typ Max Unit DC OPERATING SPECIFICATIONS POWER SUPPLY VS Quiescent Current, Operating VCO = 0 V, 4.5 V; No output switching − 1.0 − mA VBST Quiescent Current, Operating VCO = 0 V, 4.5 V; No output switching − 50 − A Quiescent Current, Non−Operating VEN = 0 V; VCO = 0 V, 4.5 V − − 25 A Undervoltage Lockout Start Threshold CO = 0 V 4.05 4.25 4.48 V Hysteresis CO = 0 V − 275 − mV CO INPUT CHARACTERISTICS High Threshold − 2.0 − − V Low Threshold − − − 0.8 V − 0 1.0 A 2.0 − − V Input Bias Current 0 < VCO < VS EN INPUT CHARACTERISTICS High Threshold Both outputs respond to CO Low Threshold Both outputs are low, independent of CO − − 0.8 V Input Bias Current 0 < VEN < VS − 0 10 A THERMAL SHUTDOWN Overtemperature Trip Point − − 170 − °C Hysteresis − − 30 − °C − − 4.0 − A HIGH−SIDE DRIVER Peak Output Current Output Resistance (Sourcing) Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125°C, VBST − VDRN = 4.5 V, VTG = 4.0 V + VDRN − 0.5 − Output Resistance (Sinking) Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125°C, VBST − VDRN = 4.5 V, VTG = 0.5 V + VDRN − 0.42 − − 4.0 − A LOW−SIDE DRIVER − Peak Output Current Output Resistance (Sourcing) Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125°C, VS = 4.5 V, VBG = 4.0 V − 0.6 − Output Resistance (Sinking) Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125°C, VS = 4.5 V, VBG = 0.5 V − 0.42 − http://onsemi.com 5 NCP5351 ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C; VS = 5.0 V; 4.0 V < VBST < 25 V; VEN = VS, CLOAD = 5.7 nF; unless otherwise noted.) Parameter Symbol Test Conditions Min Typ Max Unit AC OPERATING SPECIFICATIONS HIGH−SIDE DRIVER Rise Time trTG VBST − VDRN = 5.0 V, TJ = 125°C − 8.0 16 ns Fall Time tfTG VBST − VDRN = 5.0 V, TJ = 125°C − 14 21 ns Propagation Delay Time, TG Going High (Nonoverlap Time) tpdhTG VBST − VDRN = 5.0 V, TJ = 125°C 30 45 60 ns Propagation Delay Time, TG Going Low tpdlTG VBST − VDRN = 5.0 V, TJ = 125°C − 18 37 ns LOW−SIDE DRIVER Rise Time trBG TJ = 125°C − 10 15 ns Fall Time tfBG TJ = 125°C − 12 20 ns Propagation Delay Time, BG Going High (Non−Overlap Time) tpdhBG TJ = 125°C 25 55 80 ns Propagation Delay Time, BG Going Low tpdlBG TJ = 125°C − 10 18 ns UNDERVOLTAGE LOCKOUT VS Rising tpdhUVLO EN = VS, CO = 0 V, dVS/dt > 1.0 V/s, from 4.0 V to 4.5 V, time to BG > 1.0 V, TJ = 125°C − 30 − s VS Falling tpdlUVLO EN = VS, CO = 0 V, dVS/dt < −1.0 V/s, from 4.5 V to 4.0 V, time to BG < 1.0 V, TJ = 125°C − 500 − s http://onsemi.com 6 ATX 12 V + 5.0 V 12 V 3.3 V 6 VS 4 CO 5 EN 8 BST TG DRN PGND BG NCP5351 3 4 5 6 26 27 28 29 30 25 ILIM 24 ROSC VCC GATE1 GATE2 GATE3 GATE4 GND NCP5314 SGND Near Socket VFFB Connection 23 22 21 20 19 6 VS 4 CO 5 EN 8 3 2 1 7 6 VS 4 CO 5 EN 8 3 2 1 7 6 VS 4 CO 5 EN 8 3 2 1 7 BST TG DRN PGND BG NCP5351 18 17 16 15 14 13 12 11 VCORE GND SGND VDRP VFB COMP CS4N CS4P CS3N CS3P 8 VID2 VID3 VID4 PWRLS VFFB SS PWRGD DRVON 9 PWRGD 7 VID1 VID0 VID5 ENABLE CS2N CS2P CS1N CS1P 2 10 3.3 V 1 + NCP5351 7 http://onsemi.com Figure 3. Application Diagram VID2 VID3 VID4 32 VID5 VID0 VID1 31 ENABLE 3 2 1 7 BST TG DRN PGND BG NCP5351 NTC Near Inductor BST TG DRN PGND BG NCP5351 NCP5351 APPLICATIONS INFORMATION Theory Of Operation the drain (switch node) is sampled and the BG is disabled for a fixed delay time (tpdhBG) after the drain drops below 4 V, thus eliminating the possibility of shoot−through. When the bottom MOSFET is turning off, TG is disabled for a fixed delay (tpdhTG) after BG drops below 2.0 V. (See Figure 2 for complete timing information). Enable Pin The Enable Pin (EN) is controlled by a logic level input. With a logic level high on the EN pin, the output states of the drivers are controlled by applying a logic level voltage to the CO pin. With a logic level low both gates are forced low. By bringing both gates low when disabling, the output voltage is prevented from ringing below ground, which could potentially cause damage to the microprocessor or the device being powered. Layout Guidelines When designing any switching regulator, the layout is very important for proper operation. The designer should follow some simple layout guidelines when incorporating gate drivers in their designs. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. The use of a ground plane is a desirable way to return ground signals. Also, component location will make a difference. The boost and the VS capacitor are the most critical and should be placed as close as possible to the driver IC pins, as shown in Figure 4(a), C21 and C17. Undervoltage Lockout The TG and BG are held low until VS reaches 4.25 V during startup. The CO pin takes control of the gates’ states when the VS threshold is exceeded. If VS decreases 300 mV below threshold, the output gate will be forced low and remain low until VS rises above startup threshold. Adaptive Nonoverlap The Adaptive Nonoverlap prevents a condition where the top and bottom MOSFETs conduct at the same time and short the input supply. When the top MOSFET is turning off, 5V 12 V D32 BAT54 C21 1.0 F U3 Gate Driver 4 CO 3 BST 2 TG 1 DRN GATE1 Q7 80NO2 5 EN 6 VS 7 BG 8 PGND NCP5351 DRVON R33 C17 2.2 1.0 F (a) (b) Figure 4. Proper Layout (a), Component Selection (b) http://onsemi.com 8 Q9 80NO2 NCP5351 Measurement TYPICAL PERFORMANCE CHARACTERISTICS R1 1.0 k COM EN CO HOT BST NCP5351 VS R2* 0.108 TG BG C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF PGND DRN −5.0 V *Applied after power up and input. Conditions: BST − DRN = 5.0 V; Room Temperature; Oscilloscope referenced to VS (5.0 V). Figure 5. Top Gate Sinking Current from 0.108 Input Pulse 50 ns 0V −5.0 V 0V TG −5.0 V CO 0V −5.0 V R3 50 COM HOT VS EN BST C2 1.0 F Figure 7. Bottom Gate Sinking Current from 0.108 Input Pulse 50 ns −3.5 V −4.5 V http://onsemi.com 9 R2* 0.108 C1 1.0 F *Applied after power up and input. Conditions: VS = 5.0 V; Room Temperature; CO = 0 V. Figure 8. Bottom Gate Sinking TG BG DRN PGND CO −5.0 V DRN −3.5 V −4.5 V 0V BG −0.5 V NCP5351 R1 1.0 k Measurement Figure 6. Top Gate Sinking NCP5351 TYPICAL PERFORMANCE CHARACTERISTICS +5.0 V EN CO BST NCP5351 VS TG BG PGND DRN + − C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF Measurement R1 1.0 k R2* 0.108 *Applied after power up and input. Conditions: VS = 5.0 V; Room Temperature; DRN = 0 V. Figure 9. Bottom Gate Sourcing Current into 0.108 Input Pulse 50 ns CO 0 BG +5.0 V 0V 0 Figure 10. Bottom Gate Sourcing +5.0 V EN CO BST NCP5351 VS TG BG PGND DRN + − C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF Measurement R1 1.0 k R2* 0.108 *Applied after power up and input. Conditions: BST − DRN = 5.0 V; Room Temperature; DRN = 0 V. Figure 11. Top Gate Sourcing Current into 0.108 Input Pulse 50 ns CO 0 TG +5.0 V 0V 0 Figure 12. Top Gate Sourcing http://onsemi.com 10 NCP5351 TYPICAL PERFORMANCE CHARACTERISTICS +5.0 V EN CO PGND BST TG DRN BG C4 100 nF Measurements Gated Pulse Burst (2) R2 50 VS NCP5351 R1 1.0 k + − Input Pulse C2 10 F C1 10 F C3 100 nF + − tpdlBG tpdlTG 4.0 V DRN CO TG BG tpdhTG (non−overlap) tpdhBG (non−overlap) Figure 13. Nonoverlap Test Configuration Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature. Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature. Figure 14. Top Gate Rise Time Figure 15. Top Gate Fall Time http://onsemi.com 11 NCP5351 TYPICAL PERFORMANCE CHARACTERISTICS Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature. Conditions: VS = 5.0 V; BST − DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature. Figure 16. Bottom Gate Fall Time Figure 17. Bottom Gate Rise Time +5.0 V + − TG BG PGND DRN C3 5.7 nF Measurements +5.0 V 0V EN CO BST NCP5351 VS Input Pulse 60 ns C4 5.7 nF C1 100 nF Figure 18. Bottom Gate and Top Gate Rise/Fall Time Test http://onsemi.com 12 C2 100 nF NCP5351 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 http://onsemi.com 13 mm inches MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCP5351 PACKAGE DIMENSIONS QFN−10 CASE 485C−01 ISSUE O −X− A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. −Y− N B 2 PL 0.25 (0.010) T 2 PL 0.25 (0.010) T J R C −T− K SEATING PLANE E DIM A B C D E F G H J K L M N P R MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.20 0.30 2.45 2.55 1.75 1.85 0.50 BSC 1.23 1.28 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.88 0.93 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.008 0.012 0.096 0.100 0.069 0.073 0.020 BSC 0.048 0.050 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.035 0.037 0.024 0.031 H L G 10 F P 1 10 PL D NOTE 3 0.10 (0.004) M T X Y ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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