ONSEMI NCP1651

NCP1651
Single Stage Power Factor
Controller
The NCP1651 is an active, power factor correction controller that
can operate over a wide range of input voltages. It is designed for
50/60 Hz power systems. It is a fixed frequency controller that can
operate in continuous or discontinuous conduction modes.
The NCP1651 provides a low cost, low component count solution
for isolated AC--DC converters with mid--high output voltage
requirements. The NCP1651 eases the task of meeting the
IEC1000--3--2 harmonic requirements for converters in the range of
50 W -- 250 W.
The NCP1651 drives a flyback converter topology to operate in
continuous/discontinuous mode and programs the average input
current to follow the line voltage in order to provide unity power
factor. By using average current mode control CCM algorithm, the
NCP1651 can help provide excellent power factor while limiting the
peak primary current. Also, the fixed frequency operation eases the
input filter design.
The NCP1651 uses a proprietary multiplier design that allows for
much more accurate operation than with conventional analog
multipliers.
Features











Fixed Frequency Operation
Average Current Mode PWM
Internal High Voltage Startup Circuit
Continuous or Discontinuous Mode Operation
High Accuracy Multiplier
Overtemperature Shutdown
External Shutdown
Undervoltage Lockout
Low Cost/Parts Count Solution
Ramp Compensation Does Not Affect Oscillator Accuracy
This is a Pb--Free Device
 High Current Battery Chargers
 Front Ends for Distributed Power Systems
December, 2010 -- Rev. 9
MARKING
DIAGRAM
SOIC--16
D SUFFIX
CASE 751B
16
1
A
WL
Y
WW
G
NCP1651G
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
PIN CONNECTIONS
OUT 1
16 STARTUP
GND 2
15 NC
CT 3
14 NC
RAMP COMP 4
13 VCC
IS+ 5
12 Vref
Iavg--fltr 6
11 AC COMP
10 AC REF
Iavg 7
9 AC INPUT
FB/SD 8
(Top View)
ORDERING INFORMATION
Device
NCP1651DR2G
Typical Applications
 Semiconductor Components Industries, LLC, 2010
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Package
Shipping†
SOIC--16
(Pb--Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP1651/D
NCP1651
PIN FUNCTION DESCRIPTION
Pin No.
Function
1
Output
Drive output for power FET or IGBT. Capable of driving small devices, or can be connected to an
external driver for larger transistors.
Description
2
Ground
Ground reference for the circuit.
3
CT
4
Ramp
Compensation
Timing capacitor for the internal oscillator. This capacitor adjusts the oscillator frequency.
5
IS+
6
Iavg--fltr
A capacitor connected to this pin filters the high frequency component from the instantaneous current
waveform, to create a waveform that resembles the average line current.
7
Iavg
An external resistor with a low temperature coefficient is connected from this terminal to ground, to set
and stabilize the gain of the Current Sense Amplifier output that drives the AC error amplifier.
8
Feedback/
Shutdown
The error signal from the error amplifier circuit is fed via an optocoupler or other isolation circuit, to this
pin. A shutdown circuit is also connected to this pin which will put the unit into a low power shutdown
mode if this voltage is reduced to less than 0.6 volts.
9
AC Input
The fullwave rectified sinewave input is connected to this pin. This information is used for the reference
comparator and the average current compensation circuit.
10
AC Reference
A capacitor is connected to this pin to filter the modulated output of the reference multiplier.
11
AC
Compensation
Provides pole for the AC Reference Amplifier. This amplifier compares the sum of the AC input voltage
and the low frequency component of the input current to the reference signal. The response must be
slow enough to filter out most of the high frequency content of the current signal that is injected from the
current sense amplifier, but fast enough to cause minimal distortion to the line frequency information.
12
Vref
6.5 volt regulated reference output.
13
VCC
Provides power to the device. This pin is monitored for undervoltage and the unit will not operate if the
VCC voltage is not within the UVLO range. Initial power is supplied to this pin via the high voltage startup
network.
14
No Connection
This pin is not available due to spacing considerations of the startup pin.
15
No Connection
This pin is not available due to spacing considerations of the startup pin.
16
Startup
This pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to
the current signal for stability purposes.
Positive current sense input. Designed to connect to the positive side of the current shunt.
This pin connects to the rectified input signal and provides current to the internal bias circuitry for the
startup period of operation.
NOTE: Pins 14 and 15 have not been used for clearance considerations due to the potential voltages present on pin 16. In order to
maintain proper spacing between the high voltage and low voltage pins, traces should not be placed on the circuit board between
pins 16 and 13.
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NCP1651
MAXIMUM RATINGS (Maximum ratings are those that, if exceeded, may cause damage to the device. Electrical Characteristics are
not guaranteed over this range.)
Symbol
Value
Unit
VCC
--0.3 to 18
V
Current Sense Amplifier Input (Pin 5)
V(IS+)
--0.3 to 1.0
V
FB/SD Input (Pin 8)
VFB/SD
--0.3 to 11
V
VCT
--0.3 to 4.5
V
Vstartup
--0.3 to 500
V
Rating
Power Supply Voltage (Operating)
Output (Pin 1)
CT Input (Pin 3)
Line Voltage
All Other Pins
--0.3 to 6.5
V
Thermal Resistance, Junction--to--Air
0.1 in2 Copper
0.5 in2 Copper
θJA
Thermal Resistance, Junction--to--Lead
θJL
50
C/W
Pmax
0.77
W
Operating Temperature Range
Tj
--40 to 125
C
Non--operating Temperature Range
Tj
--55 to 150
C
Maximum Power Dissipation @ TA = 25C
130
110
C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
A. This device series contains ESD protection and exceeds the following tests:
Pins 1--6: Human Body Model 2000 V per MIL--STD--883, Method 3015.
Pins 1--6: Machine Model Method 200 V.
Pin 8 is the HV startup to the device and is rated to the maximum rating of the part, or 500 V.
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NCP1651
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 mF, Tj = 25C for typical
values. For min/max values Tj is the applicable junction temperature.)
Symbol
Min
Typ
Max
Unit
Fosc
90
100
110
kHz
--
25
--
250
kHz
Max Duty Cycle
dmax
0.95
--
--
--
Ramp Peak (Note 1)
VRpeak
--
4.0
--
V
Ramp Valley (Note 1)
VRvalley
--
0.100
--
V
Ramp Compensation Peak Voltage (Pin 4) (Note 1)
--
--
4.0
--
V
Ramp Compensation Current (Pin 4) (Note 1)
--
--
150
--
mA
Input Offset Voltage
VIO
--
20
--
mV
Transconductance
gm
75
100
150
umho
IOsource
25
70
--
mA
IOsink
--25
--70
--
mA
Input Bias Current (Pin 5)
Ibias
40
60
80
mA
Input Offset Voltage (Vcomp = 2.0) Tj = --40C to +85C
Tj = --40C to +125C
VIO
0
0
3.0
3.0
10
20
mV
ILIMthr
0.715
--
0.79
V
Output Gain (150 mA/0.150 V) (Voltage Loop Outputs)
--
--
1000
--
umho
Output Gain (150 mA/0.150 V) (AC E/A Output) (R10 = 15 kΩ)
--
--
1000
--
umho
tLEB
--
200
--
ns
--
--
1.5
--
MHz
PWM Output Voltage Gain (k = VPWM+ / (Vsense+ -- Vsense-- ))
(Vpin 3 = Vpin 13 = 0)
Av
4.0
5.0
6.0
V/V
Current Limit Voltage Gain
(k = Vace/a -- / (Vsense+ -- Vsense-- )) (Vpin59 = 0) (R7 = 15 k)
Av
8.0
10
12
V/V
Av
--
0.75
--
V/V
---
3.50
1.0
---
--
7.5
--
--
0.01
--
Characteristic
OSCILLATOR
Frequency
Tj = --40C to +125C
Frequency Range (Note 1)
AC ERROR AMPLIFIER (Vcomp = 2.0 V)
Output Source
Output Sink
CURRENT AMPLIFIER
Current Limit Threshold
Leading Edge Blanking Pulse (Note 1)
Bandwidth (Note 1)
AVERAGE CURRENT COMPENSATION AMPLIFIER
Voltage Gain
REFERENCE MULTIPLIER
Dynamic Input Voltage Range
Ac Input (p--input) (Note 1)
Offset Voltage (a--input)
Multiplier Gain
k=
(Note 1)
Vmax
V
k
Vmult out
--
(VAC∕Vramp pk) × (VLOOPcomp − Voffset)
AC INPUT (Pin 5)
Input Bias Current (Total bias current for reference multiplier and current
compensation amplifier) (Note 1)
1. Verified by design.
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4
IINbias
mA
NCP1651
ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C12 = 0.1 mF, Tj = 25C for
typical values. For min/max values Tj is the applicable junction temperature.)
Symbol
Min
Typ
Max
Unit
Rsource
--
8.0
15
Ω
Rsink
--
8.0
15
Ω
Rise Time (CL = 1.0 nF)
tr
--
50
--
ns
Fall Time (CL = 1.0 nF)
tf
--
50
--
ns
VO(UV)
--
1.0
10
mV
VrefOUT
6.24
6.50
6.76
V
DVrefOUT
0
--
40
mV
IOPTO
0.8
1.1
1.4
mA
Opto Current Source (Shutdown, VFB = 0.1 V)
--
15
20
25
mA
Input Voltage for 0 Duty Cycle (Note 2)
--
1.5
--
--
--
Input Voltage for 95% Duty Cycle (Note 2)
--
--
--
4.0
V
Characteristic
DRIVE OUTPUT
Source Resistance (1.0 Volt Drop)
Sink Resistance (1.0 Volt Drop)
Output Voltage in UVLO Condition (Drive out = 100 mA in, 1 nF load)
VOLTAGE REFERENCE
Buffered Output (Iload = 0 mA, VCC = 12 VDC, Temperature)
Load Regulation (Buffered Output, Io = 0 to 10 mA, VCC > 10 V)
FB/SD PIN
Opto Current Source (Unit Operational, VFB = 0.5 V)
Open Circuit Voltage (Device Operational) (Note 2)
VOC
--
--
12
V
Clamp Voltage (Device in Shutdown Mode) (Note 2)
VCL
0.9
1.5
1.6
V
Shutdown Start Up Threshold (Pin 8) (Vout Increasing)
VSD
0.40
0.60
0.70
V
Shutdown Hysteresis (Pin 8)
VH
30
75
130
mV
UVLO Startup Threshold (VCC Increasing)
VSU
10
10.75
11.5
V
UVLO Hysteresis (Shutdown Voltage = VSU – VH)
VH
0.8
1.0
1.2
V
Overtemperature Trip Point (Note 2)
TSD
140
160
180
C
Overtemperature Hysteresis (Note 2)
--
--
30
--
C
ISU
3.0
5.5
8.0
mA
5.0
8.5
12
mA
--
17
20
V
---
25
15
40
80
IBIAS
--
4.0
5.0
mA
IBshutdown
--
0.75
1.2
mA
STARTUP/UVLO
HIGH VOLTAGE STARTUP (Pin 16 = 50 V)
Startup Current (out of pin 13) (VCC = UVLO -- 0.2 V)
Startup Current (out of pin 13) (VCC = 0 V)
Min. Startup Voltage (pin 16, pin 13 current = 1 mA)
VSU
Line Pin Leakage (pin 16, Startup Circuit Inhibited)
(VDS = 400 V, TA = +25C)
TA = +125C
Ileak
mA
TOTAL DEVICE
Operational Bias Current (CL(Driver) = 1.0 nF, fosc = 100 kHz)
Bias Current in Undervoltage Mode
2. Verified by design.
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NCP1651
16
STARTUP
13
VCC
6.5 V
4V
6.5 V
Vref
REFERENCE
REGULATOR
20 mA
3.8 k
12
UVLO
FB/SD
+
--
8
0.50 V
V--I
CONVERTER
8 COUNTER
SHUTDOWN
R
Q
Clk
OVER-TEMPERATURE
SENSOR
A
AC INPUT
9
REFERENCE
MULTIPLIER
AC REFERENCE
BUFFER
0.75 Vline + k  Iin = Vref
+
P
--
AC REF
10
25 k
4V
V--I
AC ERROR
AMP
16 k
S
PWM
Q
R
SET
4.5 V
DOMINANT
DRIVER
AC COMP
RAMP
COMPENSATION
11
+
--
LEB
+
OSCILLATOR
AVERAGE
CURRENT
COMPENSATION
CURRENT
SENSE
AMPLIFIER
--
2
RAMP COMP
4
3
CT
Figure 1. Block Diagram
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6
OUT
1
20 k
60 k
GND
-+
Iavg 7 6 Iavg--fltr
IS+
5
NCP1651
DRIVE
LATCH Q
AC Error Amp + Ramp Comp + Inductor Current
PWM
4V
GND
FB/SD
0.5 V
GND
OSCILLATOR
RAMP
OSCILLATOR
BLANKING PULSE
Figure 2. Switching Timing Diagram
7
7
VCC
8
1
2
3
7
8
7
7
10.8 V
9.8 V
STARTUP OFF
ENABLE
ON
OUTPUT MAX
CURRENT
0
FB/SD
0.5 V
0
SHUTDOWN
STARTUP
CURRENT LIMIT
Figure 3. Divide--by--Eight Counter Timing Diagram
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7
SHUTDOWN
7
8
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
5
12
10
PIN 6
PIN 7
8
3
Vpin 8 (V)
Vout (V)
4
2
4
1
0
2
0
100
200
300
400
0
500
0
200
400
600
800
1000 1200 1400 1600
IS+ (mV)
Isink (mA)
Figure 4. Current Sense Amplifier Gain
Figure 5. FB/SD V--I Characteristics
0.9
5.0
--40C
0.8
VCC = 14 V
BIAS CURRENT (mA)
0C
0.7
CURRENT (mA)
6
25C
80C
0.6
0.5
125C
0.4
0.3
0.2
4.5
4.0
3.5
3.0
0.1
0
2
4
6
8
2.5
--50
12
25
50
75
100
125
Figure 6. Bias Current in Shutdown Mode
Figure 7. Bias Current in Operating Mode
25C
6
125C
5
80C
4
3
2
1
10
100
150
39
--40C
0C
7
1
0
TEMPERATURE (C)
8
0
--25
VCC (V)
9
STARTUP CURRENT, PIN 16 (mA)
10
LEAKAGE CURRENT, PIN 16 (mA)
0
34
29
24
19
14
9.0
--50
1000
--25
0
25
50
75
100
125
150
STARTUP PIN VOLTAGE (V)
TEMPERATURE (C)
Figure 8. Startup Current versus High Voltage
Figure 9. Startup Leakage versus Temperature
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NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
11.2
1.5
CLAMP VOLTAGE, PIN 8 (V)
TURN--ON
THRESHOLD (V)
10.8
10.5
10.2
TURN--OFF
9.8
9.5
--50
--25
0
25
50
75
100
0
125
0
2
4
6
8
10
12
VCC (V)
Figure 10. UVLO versus Temperature
Figure 11. FB/SD Clamp Voltage versus VCC
1000
2.5 V
FB/SD = 3.0 V
4
2.0 V
VCC, CAPACITANCE (mF)
4.5
3.5
AC REF (V)
0.5
TEMPERATURE (C)
5
3
2.5
1.8 V
2
1.5
1
0.5
0
1.0
100
10
1.6 V
0
1
2
3
4
1
5
1
10
100
1000
10,000
AC INPUT (V)
CHARGE TIME (ms)
Figure 12. Reference Multiplier Gain
Figure 13. VCC Cap Charge Time
100 k
4.40
NOTE: Ramp Valley
Voltage is Zero for
All Frequencies
4.35
4.30
CT (pF)
RAMP PEAK
10 k
1000
4.25
4.20
4.15
4.10
4.05
4.00
100
1
10
100
3.95
1000
0
50
100
150
200
250
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. CT versus Frequency
Figure 15. Ramp Peak versus Frequency
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300
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
10,000
FALL TIME
RISE TIME
CAPACITANCE
98
97
96
95
1000
94
93
0
50
100
150
200
250
100
300
0
50
100
150
200
250
300
FREQUENCY (kHz)
10% TO 90% DRIVE RISE AND FALL TIMES
Figure 16. Maximum Duty Cycle versus
Frequency
Figure 17. Capacitance versus 10% to 90%
Drive Rise and Fall Times
350
110
Vref
50 mV/div
10 mA
Vref Load
0 mA
FREQUENCY (kHz)
MAXIMUM DUTY CYCLE
99
105
100
95
90
--50
--25
0
25
50
75
100
125
TEMPERATURE (C)
2.0 ms/div
Figure 18. Transient Response for 6.5 Volt
Reference
Figure 19. Frequency versus Temperature
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10
150
NCP1651
Typical Performance Characteristics
(Test circuits are located in the document TND308/D)
6.52
NOTE: Valley
Voltage is Zero
25C
4.10
Vref (V)
6.50
4.08
4.06
4.04
--50
--40C
6.48
6.46
--25
0
25
50
75
100
6.44
125
125C
0
4
2
6
8
TEMPERATURE (C)
Vref LOAD (mA)
Figure 20. Peak Ramp Voltage versus
Temperature
Figure 21. Vref Load Regulation
1
0.8
NO LOAD
Vref (V)
PEAK RAMP VOLTAGE (V)
4.12
0.6
10 kΩ
0.4
3.3 kΩ
0.2
0
--50
--25
0
25
50
75
100
TEMPERATURE (C)
Figure 22. Vref in Shutdown Condition
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125
10
NCP1651
6.5 V
3.8 k
FB/SD
9
SHUT
DOWN
680
V--I
CONVERTER
5
A
REFERENCE
MULTIPLIER
AC INPUT
(Allows external converters to be synchronized to the switching frequency of this unit.)
Figure 23. External Shutdown Circuit
Vref
12
33 k
BAS16LT1
AC COMP
11
MMBT2907AL
R11
0.33 mF
C11
Figure 24. Soft--Start Circuit
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NCP1651
NCP1651
THEORY OF OPERATION
Introduction
Optimizing the power factor of units operating off of AC
lines is becoming more and more important. There are a
number of reasons for this.
There are a growing number of government regulations
requiring Power Factor Correction PFC. Many of these are
originating in Europe. Regulations such as IEC1000--3--2
are forcing equipment to utilize input stages with topologies
other than a simple off--line front end which contains a
bridge rectifier and capacitor.
There are also system requirements that dictate the use of
PFC. In order to obtain the maximum power from an
existing circuit in a building, the power factor is very critical.
The real power available from such a circuit is:
there are two causes of power factor degradation – phase
shift and distortion. Phase shift is normally caused by
reactive loads such as motors which are inductive, or
electroluminescent lighting which is highly capacitive. In
such a case the power factor is relatively simple to analyze,
and is determined by the phase shift.
PF = cos θ
Where θ is the phase angle between the voltage and the
current.
Reduced power factor due to distortion is more
complicated to analyze and is normally measured with AC
analyzers, although most circuit simulation programs can
also calculate power factor. One of the major causes of
distortion is rectification of the line into a capacitive filter.
This causes current spikes that do not follow the input
voltage waveform. An example of this type of waveform is
shown in the upper diagram in Figure 25.
A power converter with PFC forces the current to follow
the input waveform. This reduces the peak current, the rms
current and eliminates any phase shift.
In most modern PFC circuits, to lower the input current
harmonics, and improve the input power factor, designers
have historically used a boost topology. The boost topology
can operate in the Continuous (CCM), Discontinuous
(DCM), or Critical Conduction Mode.
Most PFC applications using the boost topology are
designed to use the universal input ac power 85--265 Vac, 50
or 60 Hz, and provide a regulated DC bus (typically
400 Vdc). In most applications, the load can not operate off
the high voltage DC bus, so a DC--DC converter is used to
provide isolation between the AC source and load, and
provide a low voltage output. The advantages to this system
configuration are, low THD, a power factor close to unity,
excellent voltage regulation, and transient response on the
isolated DC output. The major disadvantage of the boost
topology is that two power stages are required which lowers
the systems efficiency, increases components count, cost,
and increases the size of the power supply.
ON Semiconductor’s NCP1651 offers a unique
alternative for Power Factor Correction designs, where the
NCP1651 has been designed to control a PFC circuit
operating in a flyback topology. There are several major
advantages to using the flyback topology. First, the user can
create a low voltage isolated secondary output, with a single
power stage, and still achieve a low input current distortion,
and a power factor close to unity. A second advantage,
compared to the boost topology with a DC--DC converter, is
a lower component count which reduces the size and the cost
of the power supply.
The NCP1651 can operate in either the Continuous or
Discontinuous Mode of operation, the following analysis
will help to highlight the advantages of Continuous versus
Discontinuous Mode of operation.
Preal = Vrms × Irms × PF
A typical off--line converter will have a power factor of
0.5 to 0.6, which means that for a given circuit breaker rating
only 50% to 60% of the maximum power is available. If the
power factor is increased to unity, the maximum available
power can be obtained.
There is a similar situation in aircraft systems, where a
limited supply of power is available from the on--board
generators. Increasing the power factor will increase the
load on the aircraft without the need for a larger generator.
V
I
v, i
t
OFF--LINE CONVERTER
V
I
v, i
t
PFC CONVERTER
Figure 25. Voltage and Current Waveforms
Unity power factor is defined as the current waveform
being in phase with the voltage, and undistorted. Therefore,
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NCP1651
one half the peak current of a flyback converter operating in
the Discontinuous Conduction Mode.
If we look at a single application and compare the results.
PO = 90 watts
Vin = 85--265 Vrms (analyzed at 85 Vrms input)
Efficiency = 80%
Pin = 108 W
VO = 48 Vdc
Freq = 100 kHz
Transformer turns ration N = 4
Continuous Conduction Mode
A second result of running in DCM can be higher input
current distortion, EMI, and a lower Power Factor, in
comparison to CCM. While the higher peak current can be
filtered to produce the same performance result, it will
require a larger filter.
A simple Fast Fourier Transform (FFT) was run in Spice
to provide a comparison between the harmonic current
levels for CCM and DCM. The harmonic current levels will
affect the size of the input EMI filter which in some
applications are required to meet the levels of C.I.S.P.R. In
the SPICE FFT model we did not add any front end filtering
so the result of the analysis could be compared directly.
Continuous Mode (CCM)
To force the inductor current to be continuous over the
majority of the input voltage range (85--265 Vac), LP needs
to be at least 1 mH. Figure 26 shows the typical current
through the windings of the flyback transformer. During
switch on period, this current flows in the primary and
during the switch off time it flows in the secondary.
300
250
IPK
Iavg
(mA)
200
150
100
TIME
Figure 26.
50
The peak current is:
IPK = Iavg + ((1.414  Vin sin θ  ton  2)/LP)
0
0.2
where Iavg = 1.414  Pin/Vin sin θ
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0
FREQUENCY (MHz)
Ton = T/((NS/NP  1.414  Vin sin θ /VO) +1)
Figure 28. Continuous Conduction Mode
Ton = 6.19 ms
At the 100 kHz switching frequency, the rms value from
the FFT is 260 mA, and the 2nd harmonic (200 kHz) is
55 mA rms.
IPK = (1.414  113)/85 sin θ + (1.414  85  6.15 ms  2) /1 mH
= 3.35 A
Discontinuous Mode (DCM)
In the discontinuous mode of operation, the inductor
current falls to zero prior to the end of the switching period
as shown in Figure 27.
2.8
2.4
2.0
IPK
(A)
1.6
Iavg
1.2
0.8
TIME
0.4
Figure 27.
0
To ensure DCM, LP needs to be reduced to approximately
100 mH.
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 2.0
FREQUENCY (MHz)
Figure 29. Discontinuous Conduction Mode
IPK = (Vin sin θ  1.414  ton)/LP
At 100 kHz the rms value from the FFT are 2.8 A, and the
2nd harmonic (200 kHz) is 500 mA rms.
IPK = 1.414  85 sin 90  5.18 ms/100 mH = 6.23 A
The results show that the peak current for a flyback
converter operating in the Continuous Conduction Mode is
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NCP1651
Results
It is clear from the result of our analysis that a flyback PFC
converter operating in CCM has half the peak current and
one tenth the fundamental (100 kHz) harmonic current
compared to a flyback PFC converter operating in DCM.
The results are lower conduction losses in the MOSFET, and
secondary rectifying diode, and a smaller input EMI filter if
the designer needs to meet the requirements C.I.S.P.R.
conducted emission levels. On the down side to CCM
operation, the flyback transformer will be larger because of
the required higher primary inductance.
The advantages to operating in DCM include lower
switching losses because the current falls to zero prior to the
next switching cycle, and smaller transformer size.
It will ultimately be up to the designer to perform a
trade--off study to determine which topology, Boost versus
Flyback, Continuous versus Discontinuous Mode of
operation will meet all the system performance
requirements. But the recent introduction of the NCP1651
allows the system designer one additional option.
For an average current mode flyback topology based PFC
converter, determining the transformer parameters (primary
inductance and turns ratio) involves several trade--offs.
These include peak--to--average current ratio (higher
inductance or turns ratio result in lower peak current),
switching losses (higher turns ratio leads to higher peak
voltage and higher switching losses), CCM vs. DCM
operation (lower values of turns ratio or higher values of
inductance extend the CCM range) and range of duty cycles
over the operational line and load range. ON Semiconductor
has designed an Excel--based spreadsheet to help design
with the NCP1651 and balance these trade--offs. The design
aid is downloadable free--of--charge from our website
(www.onsemi.com).
The ideal solution depends on the specific application
requirements and the relative priority between factors such
as THD performance, cost, size and efficiency. The design
aid allows the designer to consider different scenarios and
settle on the best solution foe a given application. Following
guidelines will help in settling towards the most feasible
solution.
1. Turns Ratio Limitations: While higher turns ratio
can limit the reflected primary voltage and current,
it is constrained by the inherent limitations of the
flyback topology. A turns ratio of higher than 20:1
will result in very high leakage inductance and
lead to high leakage spikes on the primary switch.
Thus, practical application of this approach is
restricted to output voltages 12 V and above.
2. CCM Operation: The NCP1651 is designed to
operate in both CCM and DCM modes. However,
the CCM operation results in much better THD
than the DCM operation. Thus, it is recommended
that the circuit be designed to operate in CCM at
the specified test condition for harmonics
compliance (typically at 230 V, full load). Please
keep in mind that at or near zero crossing
(<10 deg angle), it is neither necessary nor feasible
to maintain CCM operation.
3. Following key governing equations have been
incorporated in the design aid:
PFC Operation
The basic PWM function of the NCP1651 is controlled by
a small block of circuitry, which comprises the DC
regulation loop and the PFC circuit. These components are
shown in Figure 30.
There are three inputs to this loop. They are the fullwave
rectified sinewave, the instantaneous input current and the
error signal at the FB/SD pin.
The input current is forced to maintain a near unity power
factor due to the control of the AC error amplifier. This
amplifier uses information from the AC input voltage and
the AC input current to control the power switch in a manner
that gives good DC regulation as well as excellent power
factor.
The reference multiplier sets a reference level for the input
fullwave rectified sinewave. One of its inputs is connected
to a scaled down fullwave rectified sinewave, and the other
receives the error signal which has been converted to a
current. The error signal adjusts the level of the fullwave
rectified sinewave on the multiplier’s output without
distorting it. To accomplish this, it is necessary for the
bandwidth of the DC error amp to be less than twice the
lowest line frequency. Typically it is set at a factor of ten less
than the rectified frequency (e.g. for a 60 Hz input, the
bandwidth would be 12 Hz).
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680
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9
AC INPUT
8
FB/SD
REFERENCE
MULTIPLIER
20 mA
AVERAGE CURRENT
COMPENSATION
Vline
+
.75
--
V--I
CONVERTER
3.8 k
6.5 V
Vref
10
.75 Vline +
k  Iin = Vref
--
AC ERROR
AMP
+
4V
V--I
PWM
Verror(ac)
Verror(ac)
PWM
Logic
REF FILTER
AC REFERENCE
BUFFER
+
--
CURRENT
SENSE
AMPLIFIER
--
+
DRIVER
5
IS+
1
DRIVE
Rectified Line
Cout
D5
2
RDC2
RDC1
NCP1651
Figure 30. Simplified Block Diagram of Basic PFC Control Circuit
NCP1651
lower than the input current to create a reasonable DC
waveform. The DC output voltage is compared to a
reference voltage by a secondary side error amplifier, and
the error signal out of the secondary side amplifier is fed
back into the Feedback input through an optocoupler.
The switch is turned on by the oscillator, which makes this
a fixed frequency controller. Under normal operation, the
switch will remain on until the instantaneous value of
Verror(ac) reaches the 4.0 volt reference level, at which time
the switch will turn off.
The key to understanding how the input current is shaped
into a high quality sine wave is the operation of the AC error
amplifier. The inputs of an operational amplifier operating
in its linear range, must be equal. There are several
secondary effects, that create small differences between the
inverting and non--inverting inputs, but for the purpose of
this analysis they can be considered to be equal.
The fullwave rectified sinewave output of the reference
multiplier is fed into the non--inverting input of the AC error
amplifier. The inverting input to the AC error amplifier
receives a signal that is comprised of the input fullwave
rectified sinewave (which is not modified by the reference
multiplier), and summed with the filtered input current.
Since the two inputs to this amplifier will be at the same
potential, the complex signal at the non--inverting input will
have the same waveshape as the AC reference signal. The
AC reference signal (Vref) is a fullwave rectified sinewave,
and the AC input signal (Vline) is also a fullwave rectified
sinewave, therefore, the AC current signal (Iin), must also be
a fullwave rectified sinewave. This relationship gives the
formula:
AC Input
Vref
Vline
Vref = .75 ⋅ Vref + (k × Iin)
OSC
The Iin signal has a wide bandwidth, and its instantaneous
value will not follow the low frequency fullwave rectified
sinewave exactly, however, the output of the AC error
amplifier has a low frequency pole that allows the average
value of the .75 Vline + (k x Iin) to follow Vref. Since the AC
error amplifier is a transconductance amplifier, it is followed
by an inverting unity gain buffer stage with a low impedance
output so that the signal can be summed with the
instantaneous input switching current (Iin). The output of the
buffer is still Verror(ac).
The difference between Verror(ac) and the 4.0 volt
reference, sets the window that the instantaneous current
will modulate in, to determine when to turn the power switch
off.
Since the input current has a fundamental frequency that
is twice that of the line, the output filter must have poles
k  Iin
Vref
.75  Vline + k  Iin
4 V ref
Verror(ac)
GND
4 V ref
Verror(ac)
Verror(ac)
GND
Figure 31. Typical Signals for PFC Circuit
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NCP1651
OPERATING DESCRIPTION
DC Reference and Buffer
The internal DC reference is a precision bandgap design
with a nominal output voltage of 4.0 volts. It is temperature
compensated, and trimmed for a 1% tolerance of its
nominal voltage, with an overall tolerance of 2%. To
assure maximum stability, this is only used as a reference so
there is minimal loading on this source.
The DC reference is fed into a buffer with a gain of 1.625
which creates a 6.5 volt supply. This is used as an internal
voltage to power many of the blocks inside of the NCP1651
and is also available for external use. The 6.5 volt reference
is designed to be terminated with at 0.1 mF capacitor for
stability reasons.
There is no buffer between the internal and external
6.5 volt supply, so care should be used when connecting
external loads. A short or overload on this voltage output
will inhibit the operation of the chip.
FB/SD
A
V to I
CONVERTER
INPUT P
RAMP
+
--
Inverting Input
OUTPUT
Figure 32. Simplified Multiplier Schematic
Undervoltage Lockout
An Undervoltage Lockout circuit (UVLO) is provided to
assure that the unit does not exhibit undesirable behavior at
low VCC levels. It also reduces power consumption to a level
that allows rapid charging of the VCC cap.
When the VCC cap is initially charging, the UVLO will
hold the unit off, and in a low bias current mode until the VCC
voltage reaches a nominal 10.8 volt level. At this point the
unit will begin operation, and the UVLO will no longer be
active. If the VCC voltage falls to a level that is 1.0 volts
below the turn--on point, the UVLO circuit will again
become active.
When in the active (shutdown) state, the UVLO circuit
removes power from all internal circuitry by shutting off the
6.5 volt supply. The 4.0 volt reference remains active, and
the UVLO and Shutdown comparators are also active.
The multiplier ramp is generated by the internal oscillator,
and is the same signal as is used in the PWM. It will therefore
have the same frequency as the power stage.
It is not necessary for Input P (into the PWM comparator)
to be a DC signal, low frequency AC signals (relative to the
ramp frequency) work well also.
The gain of the multiplier is determined by the
current--to--voltage ratio of the V--I converter, the load
resistor of the output filter and the peak and valley points of
the sawtooth ramp. When the P input signal is at the peak of
the ramp waveform, the comparator will allow the A input
signal to pass without chopping it at all. This gives an output
voltage of the A current multiplied by the output filter
resistance. When the P input signal is at the ramp valley
voltage, the comparator is held low and no current is passed
into the output filter. In between these two extremes, the duty
cycle (and therefore, the output signal) is proportional to the
level of the P input signal.
The output filter is a parallel RC network. The pole for this
network needs to be greater than twice the highest line
frequency (120 Hz for a 60 Hz line), and less than the
switching frequency. A recommended starting point is a
factor of 20 to 50 less than the switching frequency.
The pole is calculated by the formula:
Multiplier
The NCP1651 uses a new proprietary concept for its
Reference multiplier. This innovative design allows greatly
improved accuracy compared to a conventional linear
analog multiplier. The multiplier uses a PWM switching
circuit to create a scalable output signal, with a very well
defined gain.
One input (A) to the multiplier is a voltage--to--current
(V--I) converter. By converting the input voltage into a
current, an overall multiplier gain can be accomplished. In
addition, there will be no error in the output signal due to the
series rectifier.
The other signal (Input P) is input into the PWM
comparator. This selects a pulse width for the comparator
output. The current signal from the V--I converter is factored
by the duty cycle of the PWM comparator, and then filtered
by the RC network on the output. This network creates a low
pass filter, and removes the high frequency content from the
original waveform.
fo =
1
2×π×R×C
So, for a 60 Hz line, and a 100 kHz switching frequency,
a 2.0 kHz pole is a good starting point. This would be a factor
of 50 below the switching frequency, and is still far enough
above the 120 Hz rectified line frequency that it won’t cause
undesirable distortion.
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NCP1651
Feedback/Shutdown
The FB/SD pin is a multiple function pin. Its primary
function is to port the error signal to the voltage--to--current
converter that feeds the reference multiplier. The operating
range for the feedback signal is from 1.0 to 4.0 volts. Below
an input level of 1.5 volts, the PWM duty cycle is reduced
to zero. At 4.0 volts the PWM is operating at its maximum
duty cycle.
The signal at this pin is also sensed by an internal
comparator that will shutdown the unit if the voltage falls
below 0.60 volts. Under normal operating conditions the
signal at this input will be 1.5 volts or greater, and the
shutdown circuit will be inactive. This circuit is designed
such that a 680 Ohm resistor in series with the optocoupler
will assure that the converter will go to zero duty cycle when
the opto is on full, but will not go low enough to put the unit
into its shutdown mode.
The shutdown function can be used for multiple purposes
including overvoltage, undervoltage or hot--swap control.
An external transistor, open collector or open drain gate,
connected to this pin can be used to pull it low, which will
inhibit the operation of the chip, and change the operating
state to a low power standby mode. An example of a
shutdown circuit is shown in Figure 23.
The reference multiplier contains an internal loading
resistor, with a nominal value of 25 kΩ. This is because the
resistor that converts the A input voltage into a current is
internal. Making both of these resistors internal, allows for
good accuracy and good temperature performance. Only a
capacitor needs to added externally to properly compensate
this multiplier. It is not recommended that an external
parallel resistor be used at the “Ref Gain” pin, due to
tolerance variations of the internal resistor.
There is an offset in the compensation (A--input) to the
reference multiplier. It is due to the V--I converter that feeds
the input.
The FB/SD signal is buffered by a voltage--to--current
converter for the appropriate signal into the multiplier. The
schematic for that converter follows.
CURRENT
MIRROR
3.8 k
FB/SD
8
Vfb
i1
6 X i1
imult
+
--
Reference Multiplier
Ramp Compensation
The Ramp Compensation pin allows the amount of ramp
compensation to be adjusted for optimum performance.
Ramp compensation is necessary in a current mode
converter to stabilize the units operation when the duty cycle
is greater than 50%.
The amount of compensation required is dependant on
several variables, including the boost inductor value, and the
desires of the designer. The value should be based on the
falling di/dt of the inductor current. For a boost inductor with
a variable input voltage, this will vary over the AC input
cycle, and with changes in the input line. A di/dt chart is
included in the design spreadsheet that is available for the
NCP1651.
For optimum load transient performance, the ramp
compensation should equal the falling di/dt at 100% duty
cycle. For optimum line transient response, it should equal
one half of the falling di/dt at 100% duty cycle.
This pin is a buffered output of the oscillator, which
provides a voltage equal to the ramp on the oscillator CT pin.
A resistor from this pin to ground, programs a current that
is transformed via a current mirror to the non--inverting
input of the PWM comparator.
The ramp voltage due to the inductor di/dt at the input to
the PWM comparator is the current shunt voltage at pin 5
multiplied by 10, which is the gain of the current amplifier
output that feeds the PWM.
20 k
1.5 V
Figure 33. Multiplier V--I Converter
The output current for this stage is:
imult =
6 (Vfb − 1.5 V)
20 k
Multiplier
1k
AC Ref
+
--
10
25 k
4.5 V
AC Error
Amplifier
Figure 34. Reference Multiplier Clamp Circuit
There is a 1 k resistor between the AC Ref pin and the AC
Error Amplifier for ESD protection. Due to this resistor, the
voltage on pin 10 (AC Ref) will exceed 4.5 volts under some
conditions, but the maximum voltage at the non--inverting
AC Error Amplifier input will be clamped at 4.5 volts.
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NCP1651
Current
Sense
Amp
i
AC Ref
Buffer
1.6i
+
--
4
Average Current Compensation
The input signal to this amplifier is the input fullwave
rectified sinewave. The amplifier is a unity gain amplifier,
with a voltage divider on the output that attenuates the signal
by a factor of 0.75. This scaled down fullwave rectified
sinewave is summed with the low frequency current signal
out of the current sense amplifier.
The sum of these signals must equal the signal at the
non--inverting input to the AC error amplifier, which is the
output of the reference multiplier. Since there is a hard limit
of 4.5 volts at the non--inverting input, the sum of the line
voltage plus the current cannot exceed this level.
A typical universal input design operates from 85 to
265 vac, which is a range of 3.1:1. The output of the Current
Compensation amplifier will change by this amount to allow
the maximum current to vary inversely to the line voltage.
+
-16 k
Oscillator
Due to the required accuracy of the peak and valley ramp
voltages, the NCP1651 is not designed to be synchronized
to the frequency of another oscillator.
PWM
Comparator
Ramp Compensation
RRC
Figure 35. Ramp Compensation Circuit
The current mirror is designed with a 1:1.6 current ratio.
The ramp signal injected can be calculated by the following
formula:
Vramp =
1.6 Voscpk 16 k
RRC
102, 400
=
RRC
AC Error Amplifier
The AC error amplifier is a transconductance amplifier.
This amplifier forces a signal which is the sum of the current
and input voltage to equal the AC reference signal from the
reference multiplier.
Transconductance amplifiers differ from voltage
amplifiers in that the output is a high impedance with a
controlled voltage--to--current gain. This amplifier has a
nominal gain of 100 umhos (or 0.0001 amps/volt). This
means that an input voltage differential of 10 mv would
cause the output current to change by 1.0 mA. Its maximum
output current is 30 mA.
(eq. 1)
Where:
Vramp = Peak injected current signal (4 V)
RRC = Ramp compensation resistor (kΩ)
Oscillator
The oscillator generates the sawtooth ramp signal that sets
the switching frequency, as well as sets the gain for the
multipliers. Both the frequency and the peak--to--peak
amplitude are important parameters.
The oscillator uses a current source for charging the
capacitor on the CT pin. The charge rate is approximately
200 mA and is trimmed to maintain an accurate, repeatable
frequency. Discharge is accomplished by grounding the CT
pin with a saturated transistor. A hysteretic comparator
monitors that ramp signal and is used to switch between the
current source and discharge transistor. While the cap is
charging, the comparator has a reference voltage of
4.0 volts. When the ramp reaches that voltage, the
comparator switches from the charging circuit to the
discharge circuit, and its reference changes from 4.0 to ~0.5
volts (overshoot and delays will allow the valley voltage to
reach 0 volts).
The relationship between the frequency and timing
capacitor is:
Current Sense Amplifier
The current sense amplifier is a wide bandwidth amplifier
with a differential input. It consists of a differential input
stage, a high frequency current mirror (PWM output) and a
low frequency current mirror (AC error amp output).
CURRENT
MIRROR
i1
3k
3k
i1
CURRENT
MIRROR
i1
30 k
LEB
PWM
i2
AC
Error
Amp
+
--
CT = 47, 000∕f
Where CT is in pF and f is in kHz.
It is important not to load the capacitor on this pin, since
this could affect the accuracy of the frequency as well as that
of the multipliers which use the ramp signal. Any use of this
signal should incorporate a high impedance buffer.
5
IS+
6
Iavg fltr
7
Iavg
Figure 36. Current Sense Amplifier
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i2
NCP1651
waveform only, since the secondary current will not conduct
across the shunt resistor.
The input to the current sense amplifier is a common base
configuration. The voltage developed across the current
shunt is sensed at the Is+ input. The amplifier input is
designed for positive going voltages only; the power stage
should resemble the configuration of the application circuit
in Figure 38.
Caution should be exercised when designing a filter
between the shunt resistor and this input, due to the low
impedance of this amplifier. Any series resistance due to a
filter, will create an offset of:
PWM Logic
The PWM and logic circuits are comprised of a PWM
comparator, an RS flip--flop (latch) and an OR gate. The
latch is Set dominant which means that if both R and S are
high the S signal will dominate and Q will be high, which
will hold the power switch off.
The NCP1651 uses a voltage mode Pulse Width
Modulation scheme based on a fixed frequency oscillator.
The oscillator outputs a ramp waveform as well as a pulse
which is coincident with the falling edge of the ramp. The
pulse is fed into the PWM latch and OR gate that follows.
During the pulse, the latch is reset, and the output drive is in
its low state.
On the falling edge of the pulse, the output drive goes high
and the power switch begins conduction. The instantaneous
inductor current is summed with the AC error amplifier
voltage and the ramp compensation signal to create a
complex waveform that is compared to the 4.0 volt reference
signal on the inverting input to the PWM comparator. When
the signal at the non--inverting input to the PWM comparator
exceeds 4.0 volts, the output of the PWM comparator
changes to a high state which drives one of the Set inputs to
the latch and turns the power switch off until the next
oscillator cycle.
The OR gate that follows the PWM is used to inhibit the
drive signal to the power switch. In addition to the oscillator
pulse, this gate receives a signal from the shutdown OR gate,
which can inhibit operation due to an overtemperature
condition, shutdown signal, or insufficient VCC.
VOS = 50 mA × Rexternal
which will add a positive offset to the current signal. The effect
of this is that the AC error amplifier will try to compensate for
the average output current which appears never to go to zero,
and cause additional zero crossing distortion.
The voltage across the current shunt resistor is converted
into a current (i1), which drives a current mirror. The output
of the i1 current mirror is a high frequency signal that is a
replica of the instantaneous current in the switch. The
conversion of the current sense signal to current i1 is:
i1 = Vis+∕3 k
The PWM output sends that information directly to the
PWM input where it is added to the AC error amp signal and
the ramp compensation signal.
The Leading Edge Blanking circuit (LEB) interrupts the
current signal to the PWM comparator for the first 200 ns of
the switching pulse. This blanks out any spike that might
occur at turn on, which could cause false triggering of the
PWM comparator.
The other output of the i1 mirror provides a voltage signal
to a buffer amplifier. This signal is the result of i1 dropped
across an internal 30 kΩ resistor, and filtered by a capacitor
at pin 6. This signal, when properly filtered, will be the 2x
line frequency fullwave rectified sinewave. The filter pole
on pin 6 should be far enough below the switching frequency
to remove most of the high frequency component, but high
enough above the line frequency so as not to cause
significant distortion to the input fullwave rectified
sinewave waveform.
For a 100 kHz switching frequency and a 60 Hz line
frequency, a 10 kHz pole will normally work well. The
capacitor at pin 6 can be calculated knowing the desired pole
frequency by the equation:
C6 =
Driver
The output driver can be used to directly drive a FET, for
low and medium power applications, or a larger driver for
high power applications.
It is a complementary MOS, totem pole design, and is
capable of sourcing and sinking over 1.5 amps, with typical
rise and fall times of 50 ns with a 1.0 nF load. The totem pole
output has been optimized to minimize cross conduction
current during high speed operation.
Additional internal circuitry has been added to keep the
Driver in its low state whenever the Undervoltage Lockout
is active. This characteristic eliminates the need for an
external gate pulldown resistor.
1
2 π f30k
Shutdown Modes and Logic
Overtemperature A temperature sensor and reference is
provided to monitor the junction temperature of the chip.
The chip will operate to a nominal temperature of 160C at
which time the output of the temperature sensor will change
to a low state. This will set the output of the shutdown
NAND gate high, which in turn will set the output of the
PWM OR gate high, and force the driver into a low state.
Where:
C6 = Pin 6 capacitance (nF)
f = pole frequency (kHz)
or, for a 10 kHz pole, C6 would be 0.5 nF.
The gain of the low frequency current buffer is set by the
value of the resistor at pin 7. The value of R7 determines the
scale factor between the peak current and the average
current. The average current will be that of the primary
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NCP1651
There is a hysteresis of 30C on this circuit, which will allow
the chip to cool down to 130C before resuming operation.
While in the overtemperature shutdown mode, the startup
circuit will be operational and the VCC will cycle between
10.8 and 9.8 volts.
Insufficient VCC If the level of the VCC voltage is not
sufficient to maintain operation, the drive of the chip will be
inhibited and the divide--by--eight timer will be invoked.
This will normally occur when the output is overloaded.
Under this condition, the divide--by--eight counter will count
for 8 VCC cycles. At the end of the eighth cycle the driver
will be enabled and the circuit will attempt to start. If the
failure has been corrected, the output will come up and the
circuit will resume normal operation. If not, another cycle
will begin. The waveforms for overload timeout are shown
in Figure 3.
Shutdown The NCP1651 has a shutdown circuit that
can be used to inhibit the operation of the chip by reducing
the FB/SD pin voltage to less than 0.6 volts. When a
shutdown signal is issued, the output of the shutdown
comparator goes low. This immediately ceases the operation
of the unit by OR’ing that signal to the output of the PWM
logic, and holding the driver in its low state.
The inverted output of the shutdown comparator is fed in
to the reset pin of the divide--by--eight counter. The counter
reset pin sets its count to seven. As long as the reset pin is
low, the counter will remain at seven. When the shutdown
signal is removed, the reset pin will go high, and the counter
will continue to count to eight. The counter is triggered on
the negative edge of the startup enable signal. This means
that a shutdown signal that is removed on the upward VCC
slope will be in the 7 count for the remaining rise and fall of
that VCC cycle and will change to 8 on the next cycle.
This system assures that the unit will not be enabled until
the VCC voltage has a full discharge cycle available, and it
also insures that the unit will commence operation in less
than two VCC cycles. A timing diagram of this mode of
operation is shown in Figure 3. The count for the
divide--by–eight counter is shown as 7, 7, 7, 8 which
illustrates the operation of the reset function.
If the shutdown signal is terminated before the VCC voltage
reaches the lower UVLO limit (i.e. 9.8 volts), the unit will
resume operation on the following VCC down slope, and if the
shutdown signal is terminated on the VCC upward slope, the
unit will resume operation on the second VCC down slope.
CURRENT
MIRROR
2.9 V
AC
Comp
3
AC
ERROR
AMP
+
--
+
--
i1
i1
6.7 k
16 k
PWM,
Ramp
Comp
Current
Sense
Amp
Unity Gain Amplifier
Figure 37. AC Reference Buffer Schematic
The buffer’s transfer function is:
iout = (2.9 V − Vac(ea))∕6.7 k
The buffer amplifier, converts the input voltage to a
current by creating a current equal to the voltage difference
between the AC error amplifier output and the 2.9 volt
reference dropped across the 6.7 kΩ resistor. The bipolar
transistor level shifts the voltage and maintains the proper
current into the current mirror. The current mirror has a
1:1 ratio and delivers its output current to the PWM input.
This current is summed with the currents of the ramp
compensation signal and the instantaneous current signal to
determine the turn--off point in the switching cycle.
Startup Circuit
The startup circuit serves several functions. In addition to
providing the initial charge on the VCC capacitor, it serves
as a timer for the startup, overcurrent, and shutdown modes
of operation. Due to the nature of this circuit, this chip must
be biased using the startup circuit and an auxiliary winding
on the power transformer. Attempting to operate this chip
off of a fixed voltage supply will cause the chip to latch up
in some modes of operation.
A high voltage FET is biased as a current source to provide
current for startup power. On the application of input voltage,
the high voltage startup circuit is enabled and current is drawn
from the rectified AC line to charge the VCC cap.
When the voltage on the VCC cap reaches the turn on point
for the UVLO circuit (10.8 volts typical), the startup circuit
is disabled, and the PWM circuit is enabled. With the
NCP1651 enabled, the bias current increases from its
standby level to the operational level. The divide--by--eight
counter is preset to the count of 7, so that on startup the chip
will not be operational on the first cycle. The second VCC
cycle will be number 8, and the chip will be allowed to start
at this time. In the shutdown mode, the VCC cycle is held in
the 7 count state until the shutdown signal is removed. This
AC Reference Buffer
The AC reference buffer converts the voltage generated
by the AC error amplifier to be converted into a current to
be summed with the ramp compensation signal and the
instantaneous current signal.
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NCP1651
Soft--Start Circuit
The AC error amplifier has been configured such that a
low output level will cause the output duty cycle to go to
zero. This will have the effect of soft--starting the unit at
turn--on, since the output is coupled to ground through a
capacitor.
There will be an initial offset of the output voltage due to
the output current and the resistor at pin 11. For example, if
the output is saturated in the high state at turn on, it will
source 50 mA. If pin 11 is terminated with a 2.2 kΩ resistor
and a 0.01 F capacitor, the initial step will be:
allows for a repeatable, fast restart. See Figure 3 for timing
diagram.
The unit will remain operational as long as the VCC
voltage remains above the UVLO undervoltage trip point. If
the VCC voltage is reduced to the undervoltage trip point,
operation of the unit will be disabled, the startup circuit will
again be enabled, and will charge the VCC cap up to the turn
on voltage level. At this point the startup circuit will turn off
and the unit will remain in the shutdown mode. This will
continue for the next seven cycles. On the eighth cycle, the
NPC1651 will again become operational. If the VCC voltage
remains above the undervoltage trip point the unit will
continue to operate, if not the unit will begin another
divide--by--eight cycle.
The purpose of the divide--by--eight counter is to reduce
the power dissipation of the chip under overload conditions
and allow it to recycle indefinitely without overheating the
chip.
It is critical that the output voltage reaches a level that allows
the auxiliary voltage to remain above the UVLO turn--off level
before the VCC cap has discharged to that level. If the bias
voltage generated by the inductor winding fails to exceed the
shutdown voltage before the capacitor reduces to the UVLO
undervoltage turn--off level, the unit will shut down and go into
a divide--by--eight cycle, and will never start. If this occurs, the
VCC capacitor value should be increased.
50 mA × 2.2 k = 0.11 volts
and the rate of rise will be:
50 mA∕0.01 mF = 5 mV∕ms
or, 560 ms until the output is at 2.8 volts, which corresponds
to full duty cycle.
There is also a clamp on pin 8 that will keep the
capacitance on that pin discharged to 1.5 volts so that the
FB/SD signal will also slew up from a low power level to a
high power level. When the unit is in standby mode, the
clamp will be enabled. At the same time as the unit is
enabled, the clamp will be disabled to allow the feedback
signal to control the loop.
An external soft--start circuit can be added, as shown in
Figure 24, if additional time is desired.
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Vin
680
24
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C4
Figure 38. Typical Application Schematic
2
GND
C3
R3
11
AC COMP
10
9
AC REF
AC INPUT
8
FB/SD
1 mF
Rac1
Cin
20 mA
25 k
20 k
4.5 V
60 k
AVERAGE CURRENT
COMPENSATION
+
--
p
a
REFERENCE
MULTIPLIER
V--I
CONVERTER
0.022 mF
3.8 k
6.5 V
-+
RAMP
COMP
4
-+
R13
16 k
V--I
3
Ctiming
CT
OSCILLATOR
RAMP
COMPENSATION
0.75 Vline +
k  Iin = Vref
AC ERROR AMP
AC
REFERENCE
BUFFER
4V
-+
LEB
PWM
R
S
4V
Q
R10
Iavg
7
6
CURRENT
SENSE
AMPLIFIER
SET
DOMINANT
 8 COUNTER
UVLO
REFERENCE
REGULATOR
SHUTDOWN
VCC 13
OVERTEMPERATURE
SENSOR
0.6 V
STARTUP 16
C12
Iavg fltr
--
+
DRIVER
6.5 V
5
L1
Rshunt
IS+
1
OUT
Vref
12
Q1
Cref
Cout
0.47 mF
2
5.23 k
422
453
9.31 k
4.7 k
MC3303
5.23 k
4.02 k
OVERVOLTAGE
COMPARATOR
-+
ERROR
AMPLIFIER
-+
UNDERVOLTAGE
COMPARATOR
+
--
0.01 mF
TL431
7.5 k
NOTE: This is a theoretical design, and it is
not implied that a circuit designed by this
procedure will operate properly without
normal troubleshooting and adjustments as
are common with any power conversion
circuit. ON Semiconductor provides a
spread sheet that incorporates the relevant
equations, and will calculate the bias
components for a circuit using the
schematic shown.
Cac
Rac2
D4
D3
D2
D1
Rtn
12 V
NCP1651
DESIGN GUIDELINES
NCP1651
Basic Specifications
The design of any power converter begins with a basic set
of specifications. The following parameters should be
known before you begin:
Pomax
(Maximum rated output power)
Vrmsmin (Minimum operational line voltage)
Vrmsmax (Maximum operational line voltage)
fswitch
(Nominal switching frequency)
Vout
(Nominal regulated output voltage)
Most of these parameters will be dictated by system
requirements.
Using the available spreadsheet, with the following
parameters, a primary inductance of 330 mH and a turns ratio
of 10:1 would be a good choice.
Limits
Pomax = 100 W
Vinmax = 265 Vrms
Vinmin = 85 Vrms
VO = 12 V
LP = 330 mH
fswitch = 100 kHz
Np/Ns = 10
Transformer
For an average current mode, fixed frequency PFC
converter, there is no magic formula to determine the
optimum value of the transformer’s primary inductance.
There are several trade--offs that should be considered.
These include peak current vs. average current, switching
losses vs. core losses and range of duty cycles over the
operational line and load range. All of these are a function
of inductance, line and load. These parameters determine
when the converter is operating in the continuous
conduction mode and when it is operating in the
discontinuous conduction mode.
If you are designing your own transformer, the
ON Semiconductor spreadsheet (NCP1651_Design.xls)
that is available as a design aid for this part can be of help.
Enter various values of inductance as well as the turns ratio
and observe the variation in duty cycle and peak current vs.
average current.
The transformer’s duty cycle is an important parameter.
There are two main limitations for the duty cycle. The first
is the output voltage reflected back to the primary, which is
scaled by the turns ratio. This means that with a 10:1
(pri:sec) turns ratio, and a 12 volt output, the power switch
will see the input voltage plus 120 volts (10 x 12 volts) plus
leakage inductance spike. This reflected voltage determines
the maximum voltage rating of the power switch.
The second, there are practical limits to the turns ratio.
Given the flyback converter transfer function, continuous
conduction mode,
6
PEAK CURRENT
CURRENT (A)
5
4
PEDESTAL
CURRENT
3
2
1
0
0
45
90
PHASE ANGLE ()
135
180
Figure 39. Switching Current versus Phase Angle
100
DUTY CYCLE (%)
100% = Discontinuous
50% = Continuous
75
50
25
0
VO = Vin n (D∕1 − D)
It is evident that there is a direct relationship between duty
cycle and the turns ratio. In general, 10:1 is about the
maximum, although some transformer manufacturers go as
high as 12:1 or even 15:1. Turns ratios of 20:1 and above are
not normally practical as they result in very high values of
leakage inductance, which creates large spikes on the power
switch. They also have a very large reflectovoltage
associated with them.
The other option is to contact a transformer manufacturer
such as Coiltronics (www.cooperet.com/) or Coilcraft
(www.coilcraft.com/). These companies will design and
manufacture transformers to your requirements.
MODE
DUTY CYCLE
0
45
90
DEGREES ()
135
180
Figure 40. Continuous/Discontinuous and Duty Cycle
If an auxiliary winding is desired to provide a bias supply,
it should provide a minimum of 12.1 volts (to exceed the
UVLO spec) and a maximum of 18 volts. The auxiliary
winding should be connected such that it conducts when the
power switch is off. Near the zero crossings of the line
frequency, the voltage will have a peak voltage equal to the
regulated output voltage divided by the turns ratio. The filter
cap on the VCC pin needs to be of sufficient size to hold the
voltage up over between the zero crossings.
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NCP1651
Error Amplifier
The error amplifier resides on the secondary side of the
circuit, and therefore is not part of the chip. A minimal
solution would include either a discrete amplifier and
reference, or an integrated circuit that combines both, such
as the TL431 series of regulators.
12 V
9.31 k
Rout
453
+
-Undervoltage
Capacitor
422
-+
Error Amplifier
Cout
3.6 k
Ropto
Vout
FB/SD
Ropto
-+
Rdc1
Rfb
Cfb
5.23 k
Overvoltage
Comparator
4.02 k
V
Vref2
Rdc2
-+
7.5 k
Rbias
MC3303
Error
Amp
5.23 k
0.01 mF
TL431
Rtn
Figure 41. Error Amplifier Circuit
Figure 42. Error Amp with Over/Undershoot
Protection
This configuration for the error amplifier will result in a
low cost regulator, however, due to the slow loop response
of a PFC regulator it will not protect against overvoltage
conditions (e.g. load removal) or droop when a transient
load is added.
The primary side circuit has been designed such that the
PFC controller will operate at maximum duty cycle with the
optocouple in a non--conducting state. This is necessary to
allow the unit to bring up the output when the system is
initially energized. At this time there is not output voltage
available to drive the LED in the optocoupler.
In the circuit of Figure 41, the amplifier and reference
need to be rated at the maximum voltage that the output will
experience, including transient conditions. Resistors Rdc1
and Rdc2 need to be chosen such that the voltage at V is
equal to Vref2 when Vout is at its regulated voltage. Ropto is
a current limiting resistor that protects the optocoupler from
current transients due to output surges.
This design also includes inherent compensation from
transients. Since the bandwidth of the error amplifier is very
low, its output can not respond rapidly to changes in the
output voltage. A transient change in the output voltage will
change the current through Ropto. Since the output of the
error amplifier does not change immediately, if the output
voltage increases, the voltage across Ropto will increase.
This drives more current through the optocoupler, which in
turn reduces the output of the converter.
An alternate regulator is recommended, which is only
slightly more expensive, and offers excellent protection
from positive transients, and quick recovery from negative
transients.
The configuration shown in Figure 42, incorporates an
error amplifier with slow loop response, plus overvoltage
and undervoltage comparators. Under normal operation the
outputs of the Undervoltage and Overvoltage Comparators
are high. The Undervoltage Comparator provides drive for
the optocoupler, while the Overvoltage Comparator reverse
biases the diode on its output and is out of the loop.
This circuit is designed with 8% trip points both above and
below the regulation limit. If an overvoltage condition
exists, the Overvoltage comparator will respond very
quickly. When its output goes low, it will provide maximum
drive to the optocoupler, which will shut off the output of the
converter.
If the output voltage drops 8% or more below its regulated
level, the Undervoltage Comparator will go low. This will
remove the drive from the optocoupler, which will allow the
regulator to increase the duty cycle and return the output to
its regulation range much faster than the error amplifier
could.
This configuration will work over a range of 5 to 30 volts,
with the appropriate changes in Rout, Rbias and Ropto.
Rout (kΩ) = (Vout -- 4.753) / 0.7785
Rbias (kΩ) = (Vout -- 4.4)
Ropto (kΩ) = (Vout -- 3) / 2
The value for Ropto will allow a maximum of 2 mA to
drive the optocoupler. If additional current is needed, change
the 2 in the denominator of that equation to the current
(in mA) that is desired.
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NCP1651
AC Voltage Divider
The voltage divider from the input rectifiers to ground is
a simple but important calculation. For this calculation it is
necessary to know the maximum line that the unit can
operate at. The peak input voltage will be:
Vinpeak = 1.414 x Vrmsmax
The maximum voltage at the AC input (pin 5) is 3.75 volts
(this is true for both multipliers).
If the maximum line voltage is 265 Vac, the peak input
voltage is:
Vinpeak = 1.414 x 265 Vrms = 375 Vpk
To keep the power dissipation reasonable for a 1/2 watt
resistor (Rac1), it should dissipate no more than 1/4 watt. The
power in this resistor is:
PRac1 = (375 V -- 3.75 V)2 / Rac1 = 0.25 watts
Simplifies to:
VO/LP  NP/NS  T/2
di/dt primary = di/dt secondary
Vin/LP  T/2 = VO/LP  NP/NS  T/2
Vin/LP = VO/LP  NP/NS
Equation 2)
For proper slope compensation, the relationship between
RS and RRC is:
di/dt (primary)  T  RS  High Frequency Current Gain =
VRcomp
VO/LP  T  NP/NS  RS  16 k/3 k = 102.4 k/RRC
RS = (19,200/RRC  T)  (LP/VO)  (NS/NP)
Equation 3)
ton = T/(NS/NP  (2  VLL/VO)) + 1
For maximum output current, when the error amplifier is
saturated in a low state, the ramp compensation signal plus
the current signal must equal 4.0 volts (3.8 volts is used to
avoid over driving the amplifier), which is the reference
level for the PWM comparator. So:
Equation 4) VrefPWM = VinST + VRcomp
3.8 V = IPK  RS  16 k/3 k + 102.4 k/RRC  ton/T
so: Rac1 = 551 kΩ
To minimize dissipation, use the next largest standard value,
or 560 kΩ.
Typically, two 1/4 resistors are used in series to handle the
power.
Then, Rac2 = 3.75 V / ((375 V -- 3.75 V) / 560 k) = 5.6 kΩ
Current Sense Resistor/Ramp Compensation
The combination of the voltage developed across the
current sense resistor and ramp compensation signal, will
determine the peak instantaneous current that the power
switch will be allowed to conduct before it is turned off.
The vector sum of the three signals that combine to create
the signal at the non--inverting input to the PWM comparator
must add up to 4.0 volts in order to terminate the switch
cycle. These signals are the error signal from the AC error
amp, the ramp compensation signal, and the instantaneous
current. For a worst case condition, the output of the AC
error amp could be zero (current), which would require that
the sum of the ramp compensation signal and current signal
be 4.0 volts. This must be evaluated under full load and low
line conditions.
For proper ramp compensation, the ramp signal should
match the falling di/dt (which has been converted to a dv/dt)
of the inductor at 50% duty cycle. 50% duty cycle will occur
when the input voltage is 50% of the output voltage. Both the
falling di/dt and output voltage need to be reflected by the
transformer turns ratio to the primary side. Thus the
following equations for RS and RRC must be satisfied:
di/dt primary = Vin/LP  T/2
di/dt secondary = VO/LS  T/2
 
NS
LS =
NP
RRC =
RS = N
3.8
+ 5.33 Ipk
P tonVO
NS 0.1875 LP
Where:
RS is the current shunt resistor (Ohms)
RRC is the ramp compensation resistor (Ohms)
ton is the on time for the conditions given (ms)
T is the period for the switching frequency (ms)
LP is the primary inductance of the transformer (mH)
Vout is the output voltage (VDC)
Vrms is the rms line voltage at low line (Vrms)
Pout is the output power at full load (watts)
Iavg (T) is the average current for one switching cycle (A)
Ipk is the instantaneous peak primary side current (A)
V(t) is the peak line voltage (volts)
NP/NS is the transformer turns ratio (dimensionless)
2
2
(3.8 − 5.3 IPK RS)
Combining equations 2 and 4 gives:
LP
di/dt reflected to the primary:
VLOP NNPS
102.4 k ton
N
⋅T⋅ S
2 NP
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NCP1651
AC Error Amplifier
The AC error amplifier is a transconductance amplifier
that is terminated with a series RC impedance. This creates
a pole--zero pair.
To determine the values of R3 and C3, it is necessary to
look at the two signals that reach the PWM inputs. The
non--inverting input is a slow loop using the averaged
current signal. It’s gain is:
Current Scaling Resistor & Filter Capacitor
R7 sets the gain of the averaged current signal out of the
current sense amplifier which is fed into the AC error
amplifier. R7 is used to scale the current to the appropriate
level for protection purposes in the AC error amplifier
circuit.
R7 should be calculated to limit the maximum current
signal at the input to the AC error amplifier to less than
4.5 volts at low line and full load. 4.5 volts is the clamp
voltage at the output of the reference amplifier and limits the
maximum averaged current that the unit can process. The
equation for R7 is:
R7 =
30 k 15 k
AIf =
⋅
⋅ (gm ⋅ R11) ⋅ 2.3
R7
3k
Where the first two terms are the gains in the current sense
amplifier averaging circuit. The next term is the gain of the
transconductance amplifier and the constant is the gain of
the AC Reference Buffer.
The high frequency path is that of the instantaneous
current signal to the PWM non--inverting input. This gain is
16 k/3 k = 5.33, since the input signal is converted to a
current through a 3 k resistor in the current sense amplifier,
and then terminated by the 16 k resistor at the PWM input.
For stability, the gain of the low frequency path must be
less than the gain of the high frequency path. This can be
written as:
212 k ⋅ RS ⋅ Pin
VinLL 4.5 − (0.75 ⋅ ACratio ⋅ VinLL ⋅ 2 )
Where: Pin = rated input power (W)
Where: RS = Shunt resistance (W)
Where: VinLL = min. operating rms input voltage (W)
Where: ACratio = AC attenuation factor at pin 9
This equation does not allow for tolerances, and it would
be advisable to increase the input power to assure operation
at maximum power over production tolerance variations.
The current sense filter capacitor should be selected to set
its pole about a factor of 10 below the switching frequency.
345, 000 ⋅ gm ⋅ R11
R7
C6 = 5.3
f
The suggested resistor and capacitor values are:
Where: C6 = Pin 6 capacitance (nF)
Where: f = pole frequency (kHz)
so, for a 100 kHz switching frequency, a 10 kHz pole is
desirable, and C6 would be 0.5 nF.
R11 =
R7
130,000 gm
and for a zero at 1/10th of the switching frequency
C11 =
Reference Multiplier
The output of the reference multiplier is a pulse width
modulated representation of the analog input. The multiplier
is internally loaded with a resistor to ground which will set
the DC gain. An external capacitor is required to filter the
signal back into one that resembles the input fullwave
rectified sinewave. The pole for this circuit should be greater
than the line frequency and lower than the switching
frequency.
1/15th of the switching frequency is a recommended
starting value for a 60 Hz line frequency. The filter capacitor
for pin 10 can be determined by the following equation:
C10 =
< 5.3
Where:
Where:
Where:
Where:
1
= 6.366E--6
fpole
2 3.14 25 k fpole
Where: C10 = Pin 10 capacitance (F)
Where: fpole = Ref gain pole freq (Hz)
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1.59
fSW R11
R7 & R11 are in units of Ohms
gm is in units of mhos
C11 is in Farads
fsw is in Hz
NCP1651
Loop Compensation
Rdc1
Ropto
Vline
Rac1
Vac
6.5 V
Np : Ns
Vo
Rac2
3.8 k
Vfb FB/SD
8
Vref
REFERENCE
MULTIPLIER
C
AC
ERROR
AMP
-+
Q1
4V
-+
RL
OUT
LOGIC
PWM
1
25 k
Rfb
V
Vref2
Vea
-+
Rdc2
5
C.S. Amp
Cfb
C8
Ref Fltr
ERROR
AMP
Iavg
10
0.022 mF
C10
ERROR AMP
OPTO TRANSFER
REFERENCE SIGNAL
Rdc2
V′
=
Vo
Rdc1 + Rdc2
1
fz =
2 π Cfb Rfb
3.8 k CTR
ΔVfb
=
ΔVea
Ropto
ΔVref
= 2.66 Vac
ΔVfb
Av = Rfb∕Rdc1
for f < fz:
Av =
Vac =
7
RS
R7
DIVIDER
for f > fz:
Iin
IS+
MODULATOR AND OUTPUT STAGE
ΔIin
R7
=
ΔVref RS 75, 000
Vline Rac2
Rac1 + Rac2
  
Np
ΔVout
T − ton
=
η RL
ton
ΔIin
Ns
fp =

1
2 π RL C
1
2 π f Cfb Rdc1
Figure 43. Voltage Regulation Loop
Voltage Error Amplifier
The voltage error amplifier is constrained by the two
equations. When this amplifier is compensated with a
pole--zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency fz. The corresponding
bode plot would be:
Loop Model
The model for the voltage loop has been broken down into
six sections. The voltage divider, error amplifier, and opto
Transfer are external to the chip, and the reference signal,
modulator and output stage are internal.
The modulator and output stage circuitry is greatly
simplified based on the assumption that that poles and zeros
in the current feedback loop are considerably greater than
the bandwidth of the overall loop. This should be a good
assumption, because a bandwidth in the kilohertz is
necessary for a good current waveform, and the voltage error
amplifier needs to have a bandwidth of less than the lowest
line frequency that will be used.
There are two poles in this circuit. The output filter has a
pole that varies with the load. The pole on the voltage error
amplifier will be determined by this analysis.
GAIN (dB)
20
0
Unity Gain
AV
fz
--20
Voltage Divider
The voltage divider is located on the secondary side
circuitry. It is a simple resistive divider that reduces the
output voltage to the level required by the internal reference
on the voltage error amplifier. If the amplifier circuit of
Figure 42 is used, there are four resistors instead of 2. To
determine the gain of this circuit, Rdc1 is the equivalent of
the upper two resistors, 9.31 k and 453 Ohms respectively,
and Rdc2 is the equivalent of the lower two resistors, 422 and
5.23 k respectively.
f, FREQUENCY
Figure 44. Pole--zero Bode Plot
The gain at frequencies greater than fz is determined by
Rfb. Once Rfb is determined, the value of Cfb can be easily
calculated using the formula for fz.
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NCP1651
Optocoupler Transfer
The optocoupler is used to allow for galvanic isolation for
the error signal from the secondary to primary side circuits.
The gain is based on the Current Transfer Ratio of the
device. This can change over temperature and time, but will
not result in a large change in dB.
The recommended capacitor at pin 8 is 0.022 mF. If a larger
capacitor is used, the pole may become low enough that it
will have an effect on the gain phase plots near the unity gain
crossover frequency. In this case and additional zero will be
required in the error amplifier bias circuitry.
The gain of the loop will vary as the input voltage changes.
It is recommended that the compensation for the error
amplifier be calculated under high line, full load conditions.
This should be the greatest bandwidth that the unit will see.
By necessity, the unity gain (0 dB) loop bandwidth for a
PFC unit, must be less than the line frequency. If the
bandwidth approaches or exceeds the line frequency, the
voltage error amplifier signal will have frequency
components in its output that are greater than the line
frequency. These components will cause distortion in the
output of the reference amplifier, which is used to shape the
current waveform. This in turn will cause distortion in the
current and reduce the power factor.
Typically the maximum bandwidth for a 60 Hz PFC
converter is 10 Hz, and slightly less for a 50 Hz system. This
can be adjusted to meet the particular requirements of a system.
The unity gain bandwidth is determined by the frequency at
which the loop gain passes through the 0 dB level.
For stability purposes, the gain should pass through 0 dB
with a slope of --20 dB for approximately on decade on either
side of the unity gain frequency. This assures a phase margin
of greater than 45.
The gain can be calculated graphically using the equations
of Figure 18 as follows:
Divider: Calculate V/Vo in dB, this value is constant so it
will not change with frequency.
Optocoupler Transfer: Calculate Vfb/Vea using the equation
provided. Convert this value into dB.
Reference Signal: Calculate Vref/Vfb using the peak level of
the AC input signal at high line that will be seen on pin 9.
Convert this to dB. This is also a constant value.
Modulator and Output Stage: Calculate the gain in dB for
DIo/DVref for the modulator, and also the gain in dB for the
output stage (DVout/DIin). Calculate the pole frequency. The
gain will be constant for all frequencies less than fp. Starting
at the pole frequency, this gain will drop off at a rate of
20 dB/decade.
Plot the sum of all of the calculated values. Be sure to
include the output pole. It should resemble the plot of
Figure 45. This plot shows a gain of 34 dB until the pole of
the output filter is reached at 3 Hz. After that, the gain is
reduced at a rate of 20 dB/decade.
Reference Signal
The error signal is transmitted to the primary side circuit
via. the optocoupler, is converted to a current by the V--I
converter and is then used as an input to the reference
multiplier. The gain of this block is dependent on the AC
input voltage, because of the multiplier which requires two
inputs for one output.
Modulator and Output Stage
The modulator receives an input from the reference
multiplier and forces the current to follow the shape and
amplitude. The is an internal loop within this section due to
the current sense amplifier. Based on the assumptions listed
in the introduction to this analysis, this is not analyzed
separately.
The equation for the gain is good for frequencies below
the pole. There is a single pole due to the output filter. Since
the NCP1651 is a current mode converter, the inductor is not
part of the output pole as can be seen in that equation.
The modulator and output stage transfer functions have
been split into two sets of equations. The first defines the
relationship between the input current and AC reference
signal, and the later, define the output stage gain and pole.
Due to the nature of a flyback transformer, the gain of the
output stage is dependant on the duty cycle (ton/T). For
continuous mode operation, the on--time is:
ton = N
S
NP
T
⋅
2⋅Vrms
Vout
+1
Calculating the Loop Gain
At this point in the design process, all of the parameters
involved in this calculation have been determined with the
exception of the pole--zero pair on the output of the voltage
error amplifier.
All equations give gains in absolute numbers. It is
necessary to convert these to the decibel format using the
following formula:
A(dB) = 20 Log10 (A)
For example, the voltage divider would be:
A=
5.6 k
= 0.0099
560 k + 5.6 k
A(dB) = 20 Log10 0.0099 = --40 dB
http://onsemi.com
30
NCP1651
cut in half or more and probably remain stable. This can be
tested in the circuit, or simulated with a model in SPICE or
a similar analysis program.
The gain and phase plots of the completed loop are shown
in Figures 46 and 47. These include the effects of all of the
stages shown.
40
35
30
GAIN (dB)
25
20
15
80
10
5
60
0
--5
40
0.01
0.1
1
10
FREQUENCY (Hz)
100
GAIN (dB)
--10
--15
1000
Figure 45. Forward Gain Plot
0
For a crossover frequency of 10 Hz, the error amplifier
needs a gain of --25 dB at 10 Hz, since the forward gain is
equal to 25 dB at this frequency. The high frequency gain of
the error amplifier is:
AVhf = Rfb / Rdc1
Where Rdc1 is the output voltage divider resistor that is
connected from the output of the converter to the input of the
error amplifier. If the output circuit of Figure 42 is used, Rdc1
would be 9.31 k + 453 Ω, or 9.76 kΩ. A gain of --25 dB is
equal to a divider ratio of:
AV = 10(--25/20) = 0.056
so, Rfb / Rdc1 = 0.056
--20
--40
0.01
0.1
10
1
FREQUENCY (Hz)
100
1000
Figure 46. Loop Gain Plot
--75
--90
--105
PHASE (C)
or, Rfb = 0.056 x 9.76 kΩ = 546 Ω
--120
The closest standard value resistor is 560 Ω.
To offset the 2 Hz pole of the output filter, the error
amplifier should have a zero of 2 Hz or slightly higher. For
a 2 Hz zero, the compensation capacitor, Cfb can be
calculated by:
Cfb =
20
--135
--150
--165
1
= 95 mF
2 π Rfb 3 Hz
--180
100 mF is the closest standard value capacitor and would
be a good choice. This solution will provide a phase margin
of close to 90. In practice the value of capacitance could be
0.01
0.1
10
1
FREQUENCY (Hz)
Figure 47. Loop Phase Plot
http://onsemi.com
31
100
1000
NCP1651
PACKAGE DIMENSIONS
SOIC--16
CASE 751B--05
ISSUE K
--A-16
9
1
8
--B--
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
B
M
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
--T--
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada
Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada
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32
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP1651/D
AND8124/D
90 W, Universal Input,
Single Stage, PFC
Converter
http://onsemi.com
General Description
The NCP1651 demo board uses a quad operational
amplifier on the secondary to perform multiple functions.
One section of the amplifier is used as the error amplifier. A
voltage divider comprised of R23, R24, R25 and R33 senses
the output voltage and divides it down to 2.5 V. This signal
is applied to the negative input of the error amplifier; the
2.5 V reference is applied to the non−inverting input of the
error amplifier.
The output of the error amplifier provides a current sink
that drives the LED of the optocoupler. The primary side
optocoupler circuit sinks current from pin 8. This varies the
voltage into the Voltage−to−Current converter that feeds the
reference multiplier.
The loop operation is as follows: If the output voltage is
less than its nominal value, the voltage at the output of the
voltage divider (inverting input to the error amplifier) will
be less than the reference signal at the non−inverting error
amplifier input. This will cause the output of the error
amplifier to increase. The increase in the output of the error
amplifier will cause the optocoupler LED to conduct less
current, which in turn will reduce the current in the
optocoupler photo−transistor. This will increase the voltage
at pin 8 of the chip, and in turn increase the output of the
reference multiplier, causing an increase in the NCP1651
duty cycle.
The current shaping network is comprised of the ac error
amplifier, buffer and current sense amplifier. This network
will force the average input current to maintain a scaled
replica of the current reference on pin 10. The increase of the
reference voltage will cause the current shaping network to
draw more input current, which translates into an increase in
output current as it passes through the transformer. The
increase in current will increase the output power and
therefore, the output voltage. To calculate the loop stability,
it is recommended that the On Semiconductor spread sheet
be used. This is an easy and convenient way to check the gain
and phase of the control loop.
This application note describes the implementation of a
90 W, universal input Flyback Power−Factor−Correction
(PFC) converter using On Semiconductor’s NCP1651
controller.
The NCP1651 enables a low cost single−stage (with a low
voltage isolated output) PFC converter as demonstrated in
this application circuit, which is designed for 48 Vdc, at
1.9 A of output current. The NCP1651 is designed to operate
in the fixed frequency, continuous mode (CCM), or
discontinuous (DCM) mode of operation, in a Flyback
converter topology. The converter described in this
application note has the following valuable features:
Features
• Wide Input Voltage Range (85 − 265 Vac)
• Galvanic Isolation
• Primary Side Cycle−by−Cycle and Average Current
Limit
• Secondary Side Power Limiting
• High Voltage Start−up Circuit
Detailed Circuit Description
Operational description and design equations are
contained in the NCP1651 Data Sheet. This application note
addresses specific design issues related to this converter
design. Please refer to Figure 2 for component reference
designators.
Voltage Regulation Loop
With a Flyback topology, the output is isolated from the
input by the power transformer. Output voltage regulation
can be accomplished in two ways. The first, and the simplest
method is by sensing the primary side voltage of the
auxiliary winding. This eliminates the feedback isolation
circuitry, at the expense of accuracy of voltage regulation
and current sensing. The second method is to sense the
secondary side voltage which is more complex, but provides
better voltage regulation and transient response.
 Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 4
1
Publication Order Number:
AND8124/D
J1
2
Input
C26
1.2 F
R3
180 k
2
R11
1.2 k
NCP1651
16 Start−up
11 AC cmp
5
1st
littr 8
Lavg 7
Ct 3
Ramp 4
GND 2
R35
4.7 k
R8
680
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C3
1
Out
C16
2.2 F
C6
VCC
10 ACref
12
13
Vref
.68 F
9 ACin
8 FB/SD
U1
0
R1 10
1.5kE68CA
D16
1.5kE25CA
D12
R34B
56 k
180 k
R2
D4
1N4006
D3
1N4006
D7
1N4006
Q1
C25 1 nF
R34A
56 k
C11
.001 F
02
2N2222A
100 H
L3
100 H
6
3
4
T3
o
R5
.12
2
D6
MUR160
C13
.1 F
C12
.1 F
470 pF
R7 8.66 k
470 pF
R4 35 k
C10
1 nF
C8
.022 F
1
R9
3.6 k
C9
.022 F
Figure 1. Applications Circuit Schematic
.07
R25
2k
4 U3A
1
+
−
13
12
11
+
−
4
MC3303
U3D
14
R29 2.0 k
C18 .047 F
R22
C17
392 22 F
4
10 + U3C
8
9 −
MC3303
R26
11
3.3 k
11 MC3303
−
MC3303
11
C5
470 pF
4 U5B
5
7
+
6
2
3
C23
1500 F
BAS19LT1
D10
C20
1 F
C19
1 F
0
3
BAS19LT1 2
C4
1000 pF
4
1
D9
R21
2k
R27
7.5 k
R32
R30
300
C22
1500 F
0
D13
AZ23C18
U4
R20
2k
Output
R31 .07
C24
.01 F
R24
174
D11
BAS19LT1
R23
210
R33
40.2 k
D5
14 MUR1620CT
15
11
5
10
D9
BAS19LT1
7
C21
220 F
TP2
GND
R36
12 k
2
D2
1N4006
o
o
L2
J2
TP1
Shutdown
1
F1
C27
o
D1
1N4006
AND8124/D
C28 1 F
1 2
TL431
U2
R28
3.3 k
AND8124/D
Overshoot/Undershoot Circuit
Two sections of the quad amplifier are used as
comparators. One of these monitors the output for
overvoltage condition and the other for undervoltage
condition. The voltage divider requires four resistors (R33,
R23, R24, and R25) in order to make the various ratios
available for the two comparators as well as the error
amplifier.
The undervoltage comparator provides the drive for the
opto−coupler. Its output is normally in the saturated high
state, which allows the flow of current into the opto−coupler
to be determined by the error amplifier or overvoltage
comparator. If an undervoltage condition occurs, the output
of the UV comparator goes low, which reduces the drive
current to the opto−coupler LED. This causes the NCP1651
to go into a high duty cycle state, and will increase the flow
of current into the output until the output voltage is above the
UV limit.
The over−voltage comparator’s output is OR’ed with the
output of the error amplifier. During an overvoltage event
(e.g. a transient load dump), the output of this comparator
will go to ground, and cause the maximum current to flow
in the opto−coupler LED. This will pull pin 8 low and reduce
the duty cycle to zero until the output voltage is below the
OV limit. It should be noted that the purpose of the 680 resistor (R8) in series with the opto−coupler photo transistor,
is there to keep the voltage at pin 8 above the 0.5 V threshold
during such events. This keeps the control chip operational
and will allow immediate operation when the output voltage
is again in its normal operating range. Without this resistor,
the voltage on pin 8 would drop below 0.5 V, causing the
NCP1651 to enter a low power shutdown mode of operation.
in regulation the inverting input voltage is typically 2.5 V).
This causes the error amplifier signal to go low, sinking
more current through the LED in the opto−coupler. This in
turn drives more current in opto−coupler transistor collector,
pulling it low reducing the duty cycle, folding back the
output voltage.
Output Voltage Ripple
The output voltage ripple on the secondary of the
transformer has two components, the traditional high
frequency ripple associated with a flyback converter, and the
low frequency ripple associated with the line frequency
(50 Hz or 60 Hz). In this application our goal was to have the
output ripple 5% of the nominal output voltage, or 2.4 V
pk−pk.
The High Frequency Ripple can be Calculated by:
(eq. 5)
(toff 4T) (Ipk Iped )2))
(eq. 6)
irms ((3.85 10 )) (((13.382 13.38 10.27
10.272) 3) 3.85 10 4)
(13.38 10.27)2) 5.78
(eq. 7)
To meet the capacitors ripple current requirements and
lower the equivalent esr, two 1500 F capacitors were used
in parallel.
Vcap (5.78 3.85 3000 ) 0.00742
Where:
n
Ipk
Iped
CO
esr
T
(eq. 1)
(eq. 2)
(eq. 8)
=Transformer Turns Ratio (3.89)
=Peak Current Secondary (13.38)
=Pedestal Current Secondary (10.27)
=Output Capacitance (1500 each)
=Output Capacitor Equivalent Series Resistance
(0.03 Each)
=Switching Interval
Vesr Ipksec esr
The voltage to the input of the differential amplifier is:
(eq. 9)
Vesr 13.38 Apk 0.015 0.20 V
(eq. 10)
V 0.007422 0.22 0.200
(eq. 11)
The Low Frequency Portion of the Ripple:
The output voltage from the differential amplifier is:
VO 0.33 11 3.63 V
Vcap irms dt CO
irms (toff T) (((Ipk2 (Ipk Iped) Iped2) 3 ))
The fourth section of the amplifier is biased as a
differential amplifier. This section senses the DC output
current, and provides a signal that is diode OR’ed into the
feedback divider.
In the demo board the overload current limit was set to
125% of full load, or 2.375 A. Two resistors are used in
series (to limit their maximum power dissipation) to sense
the output current (R31 and R32). R29 and R30 set−the
current sense amplifier gain.
Where the gain of the amplifier is:
2.375 A 0.14 0.33 V
(eq. 4)
The RMS current at the peak of the sinewave
(phase angle 90°).
Current/Power Limit Circuit
G (R29R30) 1 3000300 1 11
V Vcap2 Vesr2
(eq. 3)
When the output load current increases, the output of the
current sense amplifier will also increase. When the
amplifiers output voltage, minus a diode drop (D11),
increases above the 2.5 V, it pulls up the feedback signal at
the inverting input of the error amplifier ( when the loop is
V Ipk t CO
(eq. 12)
IAVG PO VO
(eq. 13)
Ipk IAVG 0.637
(eq. 14)
Ipk PO VO 0.637
90 (48)(0.637) 2.95
(eq. 15)
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3
AND8124/D
If we divided the output ripple into 10° increments over one
cycle (180°) the sinusoidal ripple voltage with respect to
phase angle is:
V (PO 0.637 VO) sin()
CO 18 fline
th = One Cycle of the Line 16.67ms (60Hz)
Vmax = 48 V
Vmin = 36 V
Pout = 90 W
(eq. 16)
CO (2 90 16.67 ms) (482 362) 3000 F
In Figure 2, the low frequency output voltage ripple are
plotted with respect to phase angle.
(eq. 19)
It is a coincidence that the output capacitor calculated for
voltage ripple and hold−up time are the same value.
1.50
MOSFET Turn−off Snubber
RIPPLE (V)
1.00
The MOSFET in our design has a VDS rating of 800 V, the
peak voltage across the device at turn−off (including the
leakage inductance spike) is:
0.50
VpkTotal Vinmax 1.414 ((VO Vf)n) Vspike
0.00
(eq. 20)
−0.50
Where:
Vinmax
VO
n
Vspike
=265 Vrms
=the Output Voltage (48 V)
=the Transformer Turns Ratio (4)
=Voltage Spike Due to Transformer Leakage
Inductance
To provide a safe operating voltage for the MOSFET we
have selected Vspike to be 130 Vpeak, so when the MOSFET
turns off, the maximum Drain to Source voltage is:
−1.00
−1.50
0
45
90
DEGREES (°)
135
180
Figure 2. Calculated Output Ripple
265 1.414 48(4) 130 697 V
Figure 3. Measured Output Voltage Ripple
It can be seen from the calculations, and the scope
waveform that as long as a capacitor with a low esr is used,
that the output voltage ripple is dominated by the low
frequency (120 Hz) ripple.
E 1 le Ipk2
2
If the user would like to select CO for Hold−Up time
versus, voltage ripple:
E 1 C V2
2
(eq. 17)
Where:
C= Snubber Capacitor
V= the Voltage Across the MOSFET
Rearranging the equation:
CO 2 Pout th V max 2 V min 2
(eq. 22)
Where:
le = Leakage Inductance (9 H Measured)
Ipk = Peak Primary Current
A Second Relationship is:
Hold−Up time
Pout 1 CO V2 f
2
(eq. 21)
To minimize the effect of the leakage inductance spike,
the coupling between the primary and secondary of the
transformer needs to be as tight as possible. This can be
accomplished, if your transformer requires a primary with
multiple layers, by interleaving the primary and secondary
windings. In our 48 Vdc application the transformer primary
has 74 turns, and the secondary has 19 turns. The
manufacture of the transformer, TDK, wound one layer of
the primary with 45 turns, then the 19 turn secondary, and the
remaining 29 turns of the primary. The results were a
leakage inductance of approximately 9 H. If we compare
this to a transformer where the entire 74 turns were wound,
in two layers, then the 19 turn secondary, the leakage
inductance increased to 37 H.
The energy stored in the transformer leakage:
(eq. 18)
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4
(eq. 23)
AND8124/D
Combining Equations:
In Figure 4, the output voltage drops to 40 Vdc, and
recovers in less than 160 ms. In Figure 6 the input voltage
was increased to 230 Vac, and the load was switched from
10% to 100% load. The output voltage now drops only to 44
Vdc, and recovers in approximately 50 ms. The significant
improvement in transient response performance is attributed
to an increase in the DC gain and loop bandwidth at high
line. As the input ac line voltage increases the control loop
DC gain (Refer to www.onsemi.com for a copy of the excel
design spreadsheet for details) increases from 42 dB at
115 Vac to 62 dB at 230 Vac and the control loop bandwidth
increases from 2 Hz to 8 Hz. The result is that at high line,
there is an improvement in transient response, but because
there is less attenuation of the output 120 Hz ripple, it results
in an increase in the input Total Harmonic Distortion (THD).
The system designers will need to trade off their overall
system performance THD, Power Factor, and transient
response to optimize the control loop to meet their
requirements.
C Ipk2 le ((VO Vf)n Vpk Vspike)2
(eq. 24)
((VO Vf)n Vpk)2
Csnubber 3.82 9 H ((192 375 130)2
(eq. 25)
(192 375)2 790 pF
During the MOSFET turn−off, the capacitor C25 is charge
through the Diode D6. Prior to the next ton switching cycle
the capacitor C25 must be fully discharged, so Rsnubber is
selected to be:
Rsnubber ((VO Vf)n Vinmax 1.414 Vspike)
0.63 (Vspike * Csnubber)
(eq. 26)
((192 375 130)0.63(6.5 ) (130 * 790 pF) 28 k
(eq. 27)
The power in the snubber is:
P 1 C V2
2
(0.5)790 pF(1302) 100 kHz 0.68 W
(eq. 28)
After installing the snubber in the NCP1651 Demo Board,
and measuring the voltage spike, the snubber components
where adjusted for maximum performance, C25 was
increased to 1000 pF, and R34 was changed to 30 k. The
difference between the measured and calculated value can
be attributed to the PWB board layout, and other parasitic
components.
Evaluation Board Test Results
The results from the NCP1651 Demo Board show that
using a flyback topology for a PFC converter can provide a
low input Total Harmonic Distortion (THD), a high input
power factor, and excellent steady state output voltage
regulation.
The NCP1651 achieved a THD at 115 Vac input at full
load of 3.12% with a PF of 0.998. The input THD to 6.8%
THD at 230 Vac in, with a PF of 0.971.
The steady state output voltage regulation from 85 Vac to
230 Vac, and no load to full load is less than 0.02%, with an
output voltage ripple meeting our design goal of
2.4 Vpk−pk, measured 2.0 V pk−pk.
Figure 4.
Transient Response
Figures 4 through 7 show the output transient response for
the 90 W converter. The test conditions for each Figure are
listed below:
Table 1. Test Conditions
Vin
IO
Figure 4
115 Vac
0.19 – 1.92 A
Figure 5
115 Vac
1.92 – 0.19 A
Figure 6
230 Vac
0.19 – 1.92 A
Figure 7
230 Vac
1.92 – 0.19 A
Figure 5.
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5
AND8124/D
Power Dissipation Estimates
The NCP1651 Demo Board power dissipation (measured)
at 115 Vrms, full load, is (106.27 – 47.95 •1.92) = 14.21 W.
Following table provides the calculated and estimated
power loss spread among different power train components.
Components
Pd average
D1−D4
Input Rectifier
1.65 W
Q1
MOSFET
4.1 W
D5
Output rectifier
1.7 W
T3
Flyback transformer
3.5 W
(estimate)
R34
Snubber resistor
0.84 W
D12
Transient suppressor
2.0 W
miscellaneous
0.41 W
Figure 6.
Total
14.20 W
Demo Board Operating Instructions
Connect an Ac source, 85 − 265 Vac, 47 − 64 Hz to the
input terminals J1. Connect a load to the output terminals J2,
the PWB is market +, for the positive output, − for the return.
Turn on the ac source, and the NCP1651 will automatically
start, providing 48 Vdc to the load.
Shutdown Circuit
The shutdown circuit will inhibit the operation of the
power converter and put the NCP1651 into a low power
shutdown mode. To activate this circuit, apply 5 V to the red
test point, with the black jack being “ground”. Be aware that
the black jack is actually hot as it is connected to the output
of the input bridge rectifiers. An isolated 5 V supply should
be used.
If this circuit is not being used, it can be left open as there
is enough resistance built in to the circuit to keep the
transistor (Q2) in it’s off state.
Figure 7.
Table 2. Performance Data Regulation
Line/Load
No Load
45 W
90 W
85 Vrms
47.94
47.95
47.95
115 Vrm
47.94
47.95
47.95
230 Vrms
47.94
47.95
47.95
265 Vrms
47.94
47.94
47.95
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6
AND8124/D
Table 3. Harmonics & Distortion
115 Vac 90 W
230 Vac 90 W
V harmon
A harm. %
V harm
A harm%
2nd
0.143
0.156
0.08
0.2
3rd
0.203
1.94
0.25
4.74
5th
0.13
0.6
0.12
2.88
7th
0.08
0.28
0.07
0.22
9th
0.04
0.19
0.09
0.76
11th
0.08
0.29
0.08
0.27
13th
0.16
0.32
0.06
0.33
15th
0.28
0.41
0.14
0.68
17th
0.4
0.41
0.28
0.95
19th
0.05
0.29
0.12
0.3
PF
0.998
0.971
THD(A)
3.12
6.8
Ifund
0.918
0.468
Table 4. Efficiency
85 Vrms
115 Vrms
230 Vrms
265 Vrms
1.5
1.52
1.51
1.59
Pin
109.42
106.27
105.35
105.25
Vo
47.95
47.95
47.95
47.95
Io
1.92
1.92
1.92
1.92
Efficiency
0.841
0.866
0.874
0.875
Pin @ No Load
Table 5. Vendor Contact List
Vendor
U. S. Phone / Internet
ON Semiconductor
1−800−282−9855 www.onsemi.com/
TDK
1−847−803−6100 www.component.tdk.com/
Vishay
www.vishay.com/
Bussman (Cooper Ind.)
1−888−414−2645 www.cooperet.com/
Coiltronics (Cooper Ind.)
1−888−414−2645 www.cooperet.com/
Fairchild
www.fairchildsemi.com/
Panasonic
www.eddieray.com/panasonic/
Weidmuller
www.weidmuller.com/
Keystone
1−800−221−5510 www.keyelco.com/
HH Smith
1−888−847−6484 www.hhsmith.com/
Aavid Thermalloy
www.aavid.com/
http://onsemi.com
7
AND8124/D
Table 6. NCP1651 Application Circuit Parts List (Specifications:, 90 W, 85 vac to 265 vac Input Range, 48 V Output)
Ref Des
Description
Part Number
Manufacturer
C1
Cap, Ceramic, Chip, 1000 pF, 50 V
VJ0603Y102KXAAT
VISHAY
C3
Cap, Ceramic, Chip, 470 pF, 50 V
VJ0603Y471JXAAT
VISHAY
C5
Cap, Ceramic, Chip, 470 pF, 50 V
VJ0603Y471JXAAT
VISHAY
C6
Cap, Ceramic, Chip, 470 pF, 50 V
VJ0603Y471JXAAT
VISHAY
C8
Cap, Ceramic, Chip, .022 F, 50 V
VJ0603Y223KXXAT
VISHAY
C9
Cap, Ceramic, Chip, 0.022 F, 50 V
VJ0603Y223KXXAT
VISHAY
C10, C11
Cap, Ceramic, chip, 0.001 F, 50 V
VJ0603Y102KXAAT
VISHAY
C12, C13
Cap, Ceramic, Chip, 0.1 F, 50 V
VJ0606Y104KXXAT
VISHAY
C16
2.2 F, alum elect, 450 V (0.394dia x 0.492H)
(.394dia x .492H)
ECA−2WHG2R2
EKA00DC122P00
Panasonic (Digi – P5873)
Vishay Sprague (20)
C17
Cap, Ceramic, Chip, 22 F, 10 V
C3225X5R0J226MT
TDK
C18
Cap, Ceramic, Chip, .047 F, 50 V
VJ0603Y473KXXAT
VISHAY
C19
Cap, Ceramic, Chip, .01 F, 50 V
VJ0603Y103KXAAT
VJ0603Y103KXAAT
C20
Cap, Ceramic, Chip, 1 F, 25 V
C3216X7R1E105KT
TDK
C21
220 F, alum elect, 25 V
ECA1EM331
Panasonic
C22, 23
1800 F, alum elect, 63 V (2.2A rms min)
1500 F, alum elect, 63 V
EEU−FC1J182
EKB00JL415J00
Panasonic (Digi – P11283)
Vishay Sprague (20)
C24
Cap, Ceramic, Chip, .01 F, 50 V
VJ0603Y103KXAAT
VISHAY
C25
Cap,Ceramic, .001 F, 1 KV
ECK−03A102KBP
Panasonic
C26
1.2 F, 275 vac, X cap
F1778−512K2KCT0
VISHAY
C27
Cap, polypropylene, .68 uF, 400 VDC
MKP1841−468−405
Vishey − Sprague
C28
Cap, Ceramic, Chip, 1 F, 25 V
VJ1206V105ZXXAT
VISHAY
D1 – D4
Diode, Rectifier, 800 V, 1 A
1N4006
ON Semiconductor
D5
Diode, Ultrafast, 200 V, 16 A
MUR1620CT
ON Semiconductor
D6
Diode, Ultrafast, 600 V, 1 A
MUR160
ON Semiconductor
D7
Diode, Rectifier, 800 V, 1 A
1N4006
ON Semiconductor
D8 – D11
Diode, Switching, 120 V, 200 mA, SOT−23
BAS19LT1
ON Semiconductor
D12
TVS, 214 V, 5 W
1.5KE250A
ON Semiconductor
D13
Zener Diode, 18 V
AZ23C18
VISHAY
D16
Zener Diode, 68 V
1.5kE68CA
ON Semiconductor
F1
Fuse, 2 A, 250 Vac
1025TD2A
Bussman
L2
2.5 A sat, 100 H inductor, diff mode
TSL1315−101K2R5
TDK
L3
2.5 A sat, 100 H inductor, diff mode
TSL1315−101K2R5
TDK
Q1
FET, 11 a, 800 V, .45 , N−channel
SPA11N80C3
Infineon
Q2
Bipolar, npn, 30 V, SOT−23
MMBT2222ALT1
ON Semiconductor
R1
Resistor, SMT1206, 10
CRCW1206100JRE4
Vishey
R2
Resistor, Axial Lead, 180k, ¼ W
CMF−55−180K00FKRE
Vishey
R3
Resistor, Axial Lead, 180k, ¼ W
CMF−55−180K00FKRE
Vishey
R4
Resistor, SMT1206, 35k
CRCW120635KOJNTA
Vishey
R5
Resistor, SMT, 0.12 , 1 W
WSL2512 .12 1%
Vishey Dale
R7
Resistor, SMT1206, 8.66 k
CRCW12068661F
Vishey
R8
Resistor, SMT1206, 680
CRCW12066800F
Vishey
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8
AND8124/D
Table 6. NCP1651 Application Circuit Parts List (Specifications:, 90 W, 85 vac to 265 vac Input Range, 48 V Output)
Ref Des
Description
Part Number
Manufacturer
R9
Resistor, axial lead, 3.6k, ¼ W
CMF−55−3K600FKBF
Vishey
R11
Resistor, SMT1206, 1.2k
CRC12061K20JNTA
Vishey
R20
Resistor, SMT1206, 2.0k
CRC12062K00JNTA
Vishey
R21
Resistor, SMT1206, 2.0k
CRC12062K00JNTA
Vishey
R22
Resistor, SMT1206, 392
CRC12052K10JNTA
Vishey
R23
Resistor, SMT1206, 210, 1%
CRCW12062100F
Vishey
R24
Resistor, SMT1206, 174, 1%
CRCW12061740F
Vishey
R25
Resistor, SMT1206, 2.05k, 1%
CRCW12062051F
Vishey
R26
Resistor, SMT1206, 3.3k
CRC12063K30JNTA
Vishey
R27
Resistor, SMT1206, 7.5k
CRC12067K50JNTA
Vishey
R28
Resistor, SMT1206, 3.3k
CRC12063K30JNTA
Vishey
R29
Resistor, SMT1206, 3.01k, 1%
CRCW12063011F
Vishey
R30
Resistor, SMT1206, 301, 1%
CRCW12063010F
Vishey
R31
1w, .07 resistor
WSL251R0700FTB
Vishey
R32
1w, .07 resistor
WSL251R0700FTB
Vishey
R33
Resistor, SMT1206, 40.2k, 1%
CRCW120640022F
Vishey
R34
Resistor, axial lead, 20k, 2W
R35
Resistor, SMT1206, 4.7k
CRCW12064K70NTA
Vishey
R36
Resistor, SMT1206, 12k
CRCW120612K0JNTA
Vishey
R37
Resistor, SMT1206, 100k
CRCR1206100K0JNTA
Vishey
T1
Transformer, Flyback (Lp 1 mH)
SRW42EC−U04H14
TDK
U1
PFC Controller
NCP1651
ON Semiconductor
U2
2.5 V programmable ref, SOIC
TL431ACD
ON Semiconductor
U3
Quad Op A
MC3303D
ON Semiconductor
U4
Optocoupler, 1:1 CTR, 4 pin
SFH615AA−X007
Vishay
Hardware
H1
Printed Circuit Board
H2
Connector
171602
Weidmuller (Digi 281−1435−ND)
H3
Connector
171602
Weidmuller (Digi 281−1435−ND)
H4
Standoff, 4−40, alum, hex, .500 inches
8403
HH Smith (Newark 67F4111)
H5
Standoff, 4−40, alum, hex, .500 inches
8403
HH Smith (Newark 67F4111)
H6
Standoff, 4−40, alum, hex, .500 inches
8403
HH Smith (Newark 67F4111)
H7
Standoff, 4−40, alum, hex, .500 inches
8403
HH Smith (Newark 67F4111)
H8
Heatsink, TO−220
590302B03600
Aavid Thermalloy
H9
Heatsink, TO−220
590302B03600
Aavid Thermalloy
H10
Test point, red
5005
Keystone (Digi 5005K−ND)
H11
Test point, black
5006
Keystone (Digi 5006K−ND)
H12
Shoulder Washer
3049K−ND
Digi−Key
H13
Insulator
4672
Keystone
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9
AND8124/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
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10
For additional information, please contact your
local Sales Representative.
AND8124/D
AND8147/D
An Innovative Approach to
Achieving Single Stage PFC
and Step-Down Conversion
for Distributive Systems
http://onsemi.com
APPLICATION NOTE
INTRODUCTION
Controller Analysis
The NCP1651 can operate in either the Continuous or
Discontinuous mode of operation. The following analysis
will help to highlight the advantages of Continuous versus
Discontinuous mode of operation.
The table below defines a set of conditions from which the
comparison will be made between the two modes of
operation.
In most modern PFC circuits, to lower the input current
harmonics and improve the input power factor, designers
have historically used a boost topology. The boost topology
can operate in the Continuous Conduction Mode (CCM),
Discontinuous Conduction Mode (DCM), or Critical
Conduction Mode.
Most PFC applications using the boost topology are
designed to operate over the universal input AC voltage
range (85−265 Vac), at 50 or 60 Hz, and provide a regulated
DC bus (typically 400 Vdc). In most applications, the load
can not operate from the high voltage DC bus, so a DC−DC
converter is used to provide isolation between the AC source
and load, and provide a low voltage output. The advantages
to this system configuration are low Total Harmonic
Distortion (THD), a power factor close to unity, excellent
voltage regulation, and fast transient response on the
isolated DC output. The major disadvantage of the boost
topology is that two power stages are required which lowers
the systems efficiency, increases component count, cost, and
increases the size of the power supply.
ON Semiconductor’s NCP1651 (www.onsemi.com)
offers a unique alternative for Power Factor Correction
designs, where the NCP1651 has been designed to control
a PFC circuit operating in a flyback topology. There are
several major advantages to using the flyback topology.
First, the user can create a low voltage isolated secondary
output, with a single power stage, and still achieve a low
input current distortion, and a power factor close to unity. A
second advantage, compared to the boost topology with a
DC−DC converter, is a lower component count which
reduces the size and the cost of the power supply.
Traditionally, the flyback approach has been ignored for
PFC applications because of the perceived limitations such
as high peak currents and high switch voltage ratings. This
paper will demonstrate the novel control approach
incorporated in the NCP1651 design, coupled with advances
in discrete semiconductor technology that have made the
flyback approach very feasible for a range of applications.
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 1
Table 1.
Po = 90 W
Vin = 85−265 Vrms (analyzed at 85 Vrms input)
Efficiency = 80%
Pin = 108 W
Vo = 48 Vdc
Freq = 100 kHz
Transformer turns ratio n = 4
Continuous Mode (CCM)
To force the inductor current to be continuous over the
majority of the input voltage range (85−265 Vac) the
primary inductance, Lp needs to be at least 1.0 mH. Figure 1
shows the typical current through the primary winding of the
flyback transformer. During the switch on period, this
current flows in the primary and during the switch off−time,
it flows in the secondary.
Ipk
Iavg
TIME
Figure 1.
Therefore, the peak current can be calculated as follows:
Ipk + Iavg )
1
(1.414 · Vin sin q · ton · 2)
Lp
(eq. 1)
Publication Order Number:
AND8147/D
AND8147/D
where:
300
1.414 · Pin
Iavg +
Vin sin q
1.414 · Vin sin q
Ns
)·(
)) ) 1) (eq. 3)
Vo
Np
200
(mA)
Ton + Tń(((
(eq. 2)
For the selected operating condition:
Ton + 6.15 ms
(eq. 4)
100
1.414 · 113 1.414 · 85 · 6.15 · 2
Ipk +
)
+ 3.35 A (eq. 5)
1
85 sin q
The analysis of the converter shows that the peak current
operating in the CCM is 3.35 A.
0
0.1
0.5
1.0
1.5
2.0
FREQUENCY (MHz)
Discontinuous Mode (DCM)
Figure 3. Continuous Conduction Mode FFT
In the discontinuous mode of operation, the inductor
current falls to zero prior to the end of the switching period
as shown in Figure 2.
Referring to Figure 3, at the 100 kHz switching
frequency, the FFT is 260 mA, and the 2nd harmonic
(200 kHz) is 55 mA.
Ipk
3.0
Iavg
2.0
TIME
(A)
Figure 2.
To ensure DCM, Lp needs to be reduced to approximately
100 mH.
Ipk +
1.0
Vin sin q · 1.414 · ton
Lp
0
0.1
(eq. 6)
1.414 · 85 sin 90 · 5.18
Ipk +
+ 6.23 A
100
0.5
1.0
1.5
2.0
FREQUENCY (MHz)
Figure 4. Discontinuous Conduction Mode FFT
The results show that the peak current for a flyback
converter operating in the Continuous Conduction Mode is
about one half the peak current of a flyback converter
operating in the Discontinuous Conduction Mode.
The lower peak current as a result of operating in the CCM
lowers the conduction losses in the flyback MOSFET.
Refer to Figure 4, at 100 kHz the FFT is 2.8 A, and the
second harmonic (200 kHz) is 700 mA.
Results
From the result of our analysis it is apparent that a flyback
PFC converter operating in CCM has half the peak current,
and one tenth the fundamental (100 kHz) harmonic current
compared to a flyback PFC converter operating in DCM.
The results are lower conduction losses in the MOSFET and
secondary rectifying diode, and a smaller input EMI filter.
On the negative side to CCM operation, the flyback
transformer will be larger because of the required higher
primary inductance, and the leakage inductance will be
higher affecting efficiency because of the leakage
inductance energy that must be absorbed during the
controller off time.
Current Harmonics Analysis
A second result of running in DCM can be higher input
current distortion, Electromagnetic Interference (EMI), and
a lower Power Factor, in comparison to CCM. While the
higher peak current can be filtered to produce the same
performance result, it will require a larger input filter.
A simple Fast Fourier Transform (FFT) was run in
(ORCAD) Spice to provide a comparison between the
harmonic current levels for CCM and DCM. The harmonic
current levels will affect the size of the input EMI filter
which in some applications are required to meet the levels
of IEC1000−3−2. In the SPICE FFT model, no front end
filtering was added so the result of the analysis could be
compared directly.
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2
AND8147/D
A second transformer was wound with the entire 74
primary turns (two layers), then the 19 turn secondary, the
measured leakage inductance increased to 37 mH. The
reason for the increased leakage inductance was poor
coupling between the primary and secondary.
Once the leakage inductance is reduced, verify that the
voltage spike at turn off (Vspike) will not exceed your
MOSFET VDS.
The MOSFET in our application has a VDS rating of
800 V, to provide a safety margin of at least 100 V VDS
under worst case conditions:
Vspike:
Vspike = VDS − Vmargin − Vin max S 1.414 − (Vo + Vf)
800 − 100 − 265 S 1.414 − (48 + 0.7) 4 = 130 V
In our application the snubber circuit was designed to
limit the VDS of the MOSFET to 130 Vpk. Refer to Figure 5
for the VDS waveform. The energy stored in the transformer
leakage inductance is:
E = _ le Ipk_
Some of the advantages to operating in DCM include
lower switching losses because the current falls to zero prior
to the next switching cycle, a smaller transformer, and in
general the smaller transformer should result in a lower
leakage inductance and less energy to be absorbed in the
snubber.
Transformer Turn Ratio
The flyback transformer turns ratio affects several
operating parameters, the secondary side peak current and
the MOSFET drain to source voltage (VDS) during the
controller off time, refer to Figure 8 for the application
schematic.
The peak secondary current is:
Ipk prim S n
Where n is the transformer turns ratio, in our application
n = 4.
Using the analysis for CCM versus DCM, the peak
secondary current is:
CCM = 3.34 S 4 = 13.4 Apk
DCM = 6.23 S 4 = 24.9 Apk
It’s clear from the analysis that the higher the turns ratio,
there is a higher corresponding secondary side peak current
resulting in higher conduction losses in the output rectifier.
A second effect of the turns ratio is the MOSFET VDS.
The MOSFET VDS during the off time is:
Vpk = Vin max S 1.414 + (Vo + Vf) n + Vspike
where:
Vin max = 265 Vrms
Vo = the output voltage
Vf = the forward voltage drop across the output diode
Vspike = The voltage spike due to the transformer leakage
inductance
The turns ratio in this equation determines the output
voltage reflected back to the primary, (Vo + Vf)n.
A second effect of the turns ratio is the transformer
leakage inductance, which effects Vspike. The leakage
inductance is related to the coupling between the primary
and the secondary of the transformer. As the turns ratio
increase, there are more turns on the transformer, and unless
the designer is careful in their core geometry selection and
winding technique, the result will be a higher leakage
inductance.
To minimize leakage inductance, a core with a wide
winding window should be used; this will reduce the number
of primary and secondary layers. In addition, interleaving
the primary and secondary winding will increase the
coupling. An example will help to illustrate the point. In our
application the transformer required 74 primary turns (two
layers) and 19 secondary turns (a single layer). The
manufacturer of the transformer wound 45 primary turns,
then the 19 turn secondary, and then the remaining 29
primary turns. The result was a measured leakage
inductance of 9.0 mH.
Figure 5.
The above analysis and examples illustrate the effects of
the transformer turns ratio on the secondary side peak
currents in the PFC and the MOSFET VDS at turn off.
Careful attention should be taken when trading off turns
ratio, primary inductance and duty cycle.
Output Voltage Ripple
A second consideration when using a flyback topology for
PFC is that the output voltage ripple contains (on the
secondary of the transformer) two components, the
traditional high frequency ripple associated with a flyback
converter, and the rectified line frequency ripple (100 or
120 Hz).
The high frequency ripple can be calculated by:
DV + ǸDVcap2 ) Vesr2
http://onsemi.com
3
(eq. 7)
AND8147/D
Ioavg · dt
Co
Ip ) Iped
Ioavg +
2
DVesr + Ipk · esr
DVesr + 13.38 · 0.015 + 0.20 V
1.50
(eq. 8)
1.00
RIPPLE (V)
DVcap +
(eq. 9)
where:
n = transformer turns ratio
Ipk = peak current (secondary) (13.38 Apk)
Iped = pedestal of the secondary current (10.5 Apk)
0.50
0.00
−0.50
−1.00
−1.50
0
Co = output capacitance (3000 m total)
esr = output capacitor equivalent series resistance (0.015_)
45
90
DEGREES (°)
135
180
Figure 6. Output Ripple Envelope
dt = Toff (3.92 m)
13.38 ) 10.5
2
DV +
· 3.92
3000
Hold−Up Time
(eq. 10)
If the secondary output voltage is used for a distributed
bus, the designer may elect to size the output capacitor for
hold−up times, versus ripple. If so the output capacitors can
be calculated by:
_V + 0.0156 V
Solving eq. 7 the high frequency ripple component on the
output is:
DV + Ǹ0.01562 ) 0.202 + 0.20 V
(eq. 11)
Co +
The low frequency portion of the ripple:
DV +
(eq. 12)
90
Ipk +
+ 2.95 A
48 · 0.637
Co +
Po
0.637 · Vo sin q
482 * 362
+ 3000 mF
(eq. 16)
The NCP1651 internally provides all of the necessary
features that are typically seen in a PFC controller, plus some
features not normally found. For example the NCP1651 has
a high voltage start−up circuit, which allows the designer to
connect pin 16 of the NCP1651 directly to the high voltage
DC bus, eliminating bulky and expensive start−up circuitry.
After power is applied to the circuit, a high voltage FET
is biased as a current source to provide current for start−up
power. The high voltage start−up circuit is enabled and
current is drawn from the rectified AC line to charge the VCC
cap. When the voltage on the VCC cap reaches the turn on
point for the UVLO circuit (10.8 V nominally), the start−up
circuit is disabled, and the PWM circuit is enabled. With the
NCP1651 enabled the bias current increases from its
To calculate the total output voltage ripple:
Vripple total = eq. 7 + eq. 13.
DVripple total + ǸDVcap2 ) DVesr2
Po
0.637 · Vo sin q
2 · 90 · 16.67
NCP1651 Features
(eq. 13)
Co · 18 · fline
+
(eq. 15)
In the above calculations for output voltage ripple and
hold−up time, it is a coincidence that the same value of
output capacitance was selected in both cases.
If the output voltage ripple is divided into 10° increments
over one cycle (180°) the sinusoidal ripple voltage with
respect to phase angle is:
DV +
Vnom2 ) V min 2
where:
Pout = the maximum output power
th = the required hold−up time (we selected one cycle of the
line 60 Hz, 16.67 ms)
Vnom = the nominal 48 Vdc output
Vmin = 36 Vdc
Ipk · dt
Co
P
Iavg + o
Vo
Iavg
Ipk +
0.637
2 · Po · th
(eq. 14)
Co · 18 · fline
In Figure 6, the output voltage ripple as a function of
phase angle is plotted. The results show that as long as a
capacitor(s) with low esr are used, that the output voltage
ripple will be dominated by the low frequency ripple
(100 Hz or 120 Hz).
http://onsemi.com
4
AND8147/D
standby level to the operational level. A divide−by−eight
counter is preset to the count of 7, so that on start−up the chip
will not be operational on the first cycle. The second VCC
cycle the counter is advanced to 8, and the chip will be
allowed to start at this time. Refer to Figure 7.
7
7
VCC
8
1
2
3
7
8
7
7
7
8
10.8 V
9.8 V
STARTUP
ENABLE
OFF
ON
OUTPUT ENABLE
ENABLE
DIS
OUTPUT
CURRENT
FB/SD
MAX
0
0.5 V
0
SHUTDOWN
START−UP
CURRENT LIMIT
SHUTDOWN
START−UP
SEQUENCE
Figure 7.
The purpose of the divide−by−eight counter is to reduce
the power dissipation of the chip under overload conditions
and allow it to recycle indefinitely without overheating the
chip.
It is critical that the output voltage reaches a level that
allows the auxiliary voltage to remain above the UVLO
turn−off level before the VCC cap has discharged to 9.8 V
level. If the bias voltage generated by the inductor winding
fails to exceed the shutdown voltage before the capacitor
reduces to the UVLO under voltage turn−off level, the unit
will shut down and go into a divide−by−eight cycle, and will
never start. If this occurs, the VCC capacitor value should be
increased.
In addition to providing the initial charge on the VCC
capacitor, the start circuit also serves as a timer for the
start−up, overcurrent, and shutdown modes of operation.
Due to the nature of this circuit, this chip must be biased
using the start−up circuit and an auxiliary winding on the
power transformer. Attempting to operate this chip off of a
fixed voltage supply will not allow the chip to start.
In the shutdown mode, the VCC cycle is held in the 7 count
state until the shutdown signal is removed. This allows for
a repeatable, fast restart. See Figure 6 for the timing
diagram.
The unit will remain operational as long as the VCC
voltage remains above the UVLO under voltage trip point.
If the VCC voltage is reduced to the under voltage trip point,
operation of the unit will be disabled, the start−up circuit will
again be enabled, and will charge the VCC capacitor up to the
turn on voltage level. At this point the start−up circuit will
turn off and the unit will remain in the shutdown mode. This
will continue for the next seven cycles. On the eighth cycle,
the NPC1651 will again become operational. If the VCC
voltage remains above the undervoltage trip point the unit
will continue to operate, if not the unit will begin another
divide−by−eight cycle.
CONCLUSION
It will ultimately be up to the designer to perform a
trade−off study to determine which topology, Boost versus
flyback, Continuous versus Discontinuous Mode of
operation will meet all the system performance
requirements. But the recent introduction of the NCP1651
allows the system designer an additional option yielding a
less expensive, smaller solution.
http://onsemi.com
5
R8
680
2
1
L2
L1
1
2
J1
Input
6
R11
11 AC cmp
16 Start−up
NCP1651
VCC
10 ACref
9 ACin
5
1st
Lavg 7
Ct 3
Ramp 4
GND 2
C6
C12
0.1 mF
1
Out
littr 8
C3
12
13
Vref
0.68 mF
U1
C27
8 FB/SD
D7
1N4006
C16
2.2 mF
180 k
R2
C26
1.2 mF
D4
1N4006
D3
1N4006
D2
1N4006
C13
2.2 mF
R1 10
D6
MUR160
R34
20 k
R5
0.12
Q1
C25
0.001 mF
T3
R24
2.2 k
R33
40.4 k
D5
MUR1620CT
C21
220 mF
D8
BAS19LT1
4
1
1
+
−
R22
1k
6
5
7
U4
http://onsemi.com
470 pF
R7 11.2 k
470 pF
R4 35 k
C11
0.001 mF
C10
0.001 mF
C8
0.022 mF
C9
0.022 mF
Figure 8. CCM Application Schematic
2
1
R28
3.3 k
C17
2 mF
MC3303
U3B
C23
1500 mF
D13
AZ23CK18
C22
1500 mF
2
3
3
4
R21
2k
C19
0.01 mF
R27
7.5 k
C20
0.1 mF
TL431
U2
R20
2k
J2
R9
3.6 k
R3
180 k
F1
D1
1N4006
AND8147/D
1 2
Output
AND8147/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AND8147/D
AND8209/D
90 W, Single Stage,
Notebook Adaptor
Prepared by: Terry Allinder
ON Semiconductor
Sr. Applications Engineer
http://onsemi.com
APPLICATION NOTE
Detailed Circuit Description
General Description
The 90 W demo board demonstrates the wide range of
features found in the NCP1651. It provides an 18.5 V, 4.86 A
isolated output, foldback current limit which is ideal for
low−cost battery charger and notebook adaptor applications.
This unit will provide an isolated 18.5 V output from an
input source with a frequency range from 47 Hz to 63 Hz,
and a voltage range of 90 Vrms to 265 Vrms. It is fully
self−contained and includes an internal high voltage startup
circuit, and bias supply that operates off of the Flyback
transformer auxiliary winding.
In addition to excellent power factor, this chip offers fixed
frequency operation in continuous and discontinuous modes
of operation. It has a wide variety of protection features,
including instantaneous current limiting, average current
limiting, and an accurate secondary side power limit.
The detailed operational description and design equations
are contained in the NCP1651 data sheet and in application
note AND8124/D. This application note relates to this
18.5 Vdc 90 W adaptor design.
The 18.5 Vdc 90 W adaptor was designed using the
Excel Design Spreadsheet which can be downloaded from
the ON Semiconductor website (www.onsemi.com). The
design steps for the adaptor are listed below. The schematic
for the 90 W demo board, Figure 7, is located at the end of
the technical write up.
Design Steps
1. Specifications, refer to Table 1 (90−265 V,
18.5 Vout, 90 W).
2. Determine primary inductance.
3. Determine turns ratio.
4. Select the MOSFET.
5. Select the output rectifier.
6. Build transformer with the lowest leakage
inductance.
7. Select the output capacitor for ripple and transient
response.
8. Complete control circuit design.
9. Build and test!
Features
•
•
•
•
•
Fixed Frequency Operation
Operation Over the Universal Input Range
Multiple Protection Schemes
Single Power Stage with Isolated Output
Startup and Bias Circuits Included
Table 1. Demonstration Board Specifications
Requirements
Symbol
Min
Max
Input
Vac
90
265
Frequency
Hz
47
63
Vo (Static Regulation)
Vdc
18.4
18.6
Io
Adc
0
4.86
Output Power
W
−
90
Efficiency
%
84
−
mW
−
500
Standby Power
Vin 230 Vac
 Semiconductor Components Industries, LLC, 2005
May, 2005 − Rev. 0
Figure 1 shows a sample of the System Input parameters
from the NCP1651 Design Excel Spreadsheet. In the
“Limits” column you enter your System Requirements.
Below this is a column labeled “Evaluation”. This is where
you would like to evaluate your design. Normally this is
done at full load and with the minimum input AC line
voltage. To the right you have the spreadsheet plot with the
average input current with respect to phase angle.
1
Publication Order Number:
AND8209/D
AND8209/D
Average Current vs. Phase Angle
Limits
POmax = 90 W
Vinmax = 265 Vrms
Vinmin = 90 Vrms
Vo
= 18.5 V
Lp
= 600 H
fswitch = 100 kHz
Np/Ns = 8.43
1.8
1.6
1.4
CURRENT (A)
Limits info should not
change for a given
design. Evaluation data
may be changed as
desired for various line
and load conditions.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
45
Peek switch voltage is
approximately (V). 560.7
90
PHASE ANGLE (°)
135
180
Switching Current vs. Phase Angle
Evaluation
= 90 W
= 90 V
= 0.85
= 60 Hz
= 10 s
= 106 W
4.0
3.5
Peak Current
3.0
CURRENT (A)
Pout
Vi
Effic
fLINE
T
Pin
2.5
2.0
Pedestal Current
1.5
1.0
0.5
0.0
0
45
90
135
180
PHASE ANGLE (°)
Figure 1.
Primary Inductance Selections
For most applications ON Semiconductor recommends
CCM operation at low line and full load to minimize losses
(deciding on the boundary conditioned from CCM to DCM
depending on your magnetics size trade−offs). Using the
Design Spreadsheet we selected a primary inductance of
600 H. Using 600 H the input current is CCM at low line
and full load, and starts to go discontinuous at 230 Vac near
the zero crossing of the line. Selecting this operating mode
allows for a lower Total Harmonic Distortion (THD) and a
high Power Factor (PF), and lower peak current. A lower
primary inductance can be used to reduce the size of the
Flyback transformer, understanding that it will result in a
higher THD, lower PF, and higher peak current which results
in higher losses. Refer to the section labeled “Demo Board
Test Result” for final Demo Board performance.
To determine the required primary inductance you must
first determine if you want to operate in the continuous or
discontinuous mode.
• CCM Operation
− Lower peak and rms currents
− Smaller input filter
− Requires higher primary inductance (more turns)
• DCM Operation
− Higher peak and rms currents
− Larger input filter
− Smaller inductor size
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2
AND8209/D
Transformer Turns Ratio
RDSON Infineon SPA11N80C MOSFETs were used. In
addition to reduce the switching loses the oscillator
frequency of the NCP1651 controller is set to run at 70 kHz.
700
250
600
Max Recommended MOSFET VDS
200
500
150
400
Max Recommended
Diode VR
300
100
200
50
Area of Operation
100
0
Output Diode Selection
For this application we selected an ON Semiconductor
MBR20100CT Schottky diode. The MBR20100CT diode
has a peak inverse voltage rating of 100 V and an average
forward current rating of 10 A.
Leakage Inductance
To minimize the effect of the leakage inductance spike,
the coupling between the primary and secondary of the
transformer needs to be as high as possible. This can be
accomplished, if your transformer requires a primary with
multiple layers, by interleaving the primary secondary
windings. In our 18.5 Vdc application, the transformer
primary has fifty−nine turns, and the secondary has seven
turns. The manufacturer of the transformer, TDK, wound
one layer of the primary with thirty turns and then the seven
turn secondary (two seven turns secondary in parallel), and
the remaining twenty−nine turns of the primary. The results
were a leakage inductance of approximately 8.5 H. Refer
to application note AND8147/D where a comparison of
transformer winding techniques versus leakage inductance
was preformed.
Output Voltage Ripple
The output voltage ripple (V) on the secondary of the
transformer has two components, the traditional high
frequency ripple associated with a flyback converter, and the
low frequency ripple associated with the line frequency
(50 or 60 Hz).
VR, OUTPUT DIODE REVERSE VOLTAGE (V)
VDS, POWER SWITCH DRAIN TO SOURCE
VOLTAGE (V)
There are several tradeoffs that must be considered when
selecting the transformer turns ratio (n). The first is the peak
primary current, the second is the maximum voltage stress
on the Flyback MOSFET (for more details refer to
application note AND8124/D), and the third is the output
diode reverse voltage. Figure 2 graphical shows the
relationships, on the left axis is the MOSFET Drain to
Source voltage (VDS). The horizontal axis is the
transformer turns ratio, and the right vertical axis is the
output diode reverse voltage. For an 18.5 Vdc output the
graph shows that the transformer turns ratio can be between
4.6 and 9.4 (operating from the universal AC input).
The MOSFET in our design has a VDS rating of 800 V,
this is the peak voltage across the device at turn−off
(excluding the leakage inductance spike) is:
VDS = Vinmax 1.414 + (Vo + Vf) n
Where:
Vinmax = 265 Vac
Vo = 18.5 Vdc
To provide some margin for the leakage inductance spike,
the design goal is to keep VDS below 550 V. Based on the
above design goals and the requirement to keep the peak
current as low as possible, our turns ratio was selected to be
8.4. This will limit the MOSFET VDS to approximately
525 V (excluding the turn−off leakage inductance spike),
and the output diode reverse voltage to approximately 55 V.
V Vcap2 Vesr2
The high frequency ripple can be calculated by:
Vcap Ioavg 3
4
5
6
7
8
9 10 11
TRANSFORMER TURNS RATIO
Ipk Iped
2
Vesr Ipk · esr
If we divided the output ripple into 10° increments over
one cycle (180°) the sinusoidal ripple voltage with respect
to phase angle is:
The low frequency ripple can be calculated by:
0
2
Ioavg · dt
Co
12
Figure 2. Turns Ratio Tradeoff
V Transformer Turns Ration Summary
• Higher N leads to lower Iprim, Vsec
• Lower N allows lower Vds, lower leakage inductance,
2 · Co · VoPo· 2 · · fline · sin Where:
Ipk = Peak current (secondary)
Iped = Pedestal of the secondary current
Co = Output capacitance
esr = Output capacitor equivalent series resistance
T = Switching frequency
and capacitor ripple current
MOSFET Selection
For our application one of the primary concerns is the
system efficiency. To reduce the conduction losses two low
http://onsemi.com
3
AND8209/D
Control Loop
Using the NCP1651 Excel Design Spreadsheet the output
voltage ripple is plotted versus phase angle in Figure 3 and
is approximately 800 mV pk–pk with an output capacitance
of 15,600 F.
The control loop is set up to limit the loop bandwidth at
high line (230 Vac) to approximately 15 Hz with a minimum
phase margin of 45°. The simplest way do this is with the
Excel Design Spreadsheet. In our application the final
components selected were based on cost and standard
components values. The loop crosses 0 dB at 12 Hz at high
line with a phase margin of 50° (refer to Figures 5 and 6).
Step 5, the “Error Amplifier Loop Design”, below, is a
captured screen from the Excel Design Spreadsheet. The
spreadsheet will recommend the compensation values to
provide a stable control loop, but the user typically should
select the closest standard value. For this application, the
18.5 Vdc Demo Board, the spreadsheet recommended
values were not used so we could reduce the loop bandwidth
to provide a higher power factor and lower distortion.
Output Ripple Envelope
0.50
0.40
0.30
RIPPLE (V)
0.20
0.10
0.00
−0.10
−0.20
−0.30
−0.40
−0.50
Step 5 − Error Amplifier Loop Design
0
45
90
135
180
NCP1651 Design Spreadsheet
Provided by ON Semiconductor
DEGREES
Loop Stability
Figure 3. Excel Spreadsheet Output Voltage
Ripple
Suggested
Value
For a comparison, Figure 4 shows the measured output
voltage ripple from the NCP1651 Demo Board. The results
show that the Excel Design Spreadsheets provide very
accurate results.
CTRopto =
VCC =
Optocoupler Current
Transfer Ratio
(Icoll/Idiode)
12 V
Bias Voltage for
Secondary
Operational Amplifier
8,333
4,700 Optocoupler Series
Resistor
Rfb =
455
560 Volt Error Amp
Stability (suggested
value for 10 Hz
crossover)
Cfb =
70.6
22 F
Volt Error Amp
Stability (see bode
plots for Cfb and Rfb)
Ropto =
fz error amp =
12.92 Hz
fp output =
2.68 Hz
Figure 4. Measured Output Voltage Ripple
http://onsemi.com
4
2.5
AND8209/D
Open Loop Gain
Loop Phase
100
−75
80
−90
High Line
PHASE (°)
GAIN (dB)
60
40
20
−105
−120
−135
0
−150
−20
Low Line
−40
−60
0.01
0.1
1
10
−165
100
−180
0.01
1000
FREQUENCY (Hz)
0.1
1
10
FREQUENCY (Hz)
Figure 5. Loop Gain
Figure 6. Phase Margin
http://onsemi.com
5
100
1000
7
5
11
10
3
2
D4
1N4006
C16
2.2 F
R5
100 k
R34
100 k
R35
100 k
J2
C27
1.2 F
C26
D3
0.47 F 1N4006
4
0
D5
MUR20100CT
14
C25
6
0.01 F
0
C22
3900
F
15
C23
3900
F
R20
2k
R2
330 k
+Vccsec
R21
8.2 k
U4
SFH6155AA
12
Vref
AC in
C10
C11
R4
C3
R7
C6
0.02
F
1 nF
12 nF
33 k
470
pF
8.6 k 470
pF
1
MC3303
R22
560
6
C8
7
C12
C13
0.1
F
0.1
F
R13
0.2
F
D11
BAS19LT1
R10
0.2
C20
1 F
F
R23
2.67 K
Ilftr
Iavg
7
3
Ct
Ramp
R11
1.0 K
U38
+
−
C24
0.01 F
AC cmp
Gnd
11
5
Is+
2
C17
22 F
R26
3.3 k
C18 0.22 F
C2
1 nF
F
R27
7.5 k
C19
0.01 F
TL431
U2
R29 2 K
R30
100
0
R31
0.006
R6
0.006
12
13
+
−
+Vccsec
U3D
14
MC3303
11
0.01
F
R9
6.6 k
5
6
R1
2.7
AC ref
4
10
C9
R33
17.4 K
Q2
SPP11N80C3
1
Out
Q1
SPP11N80C3
4
D14
BAS19LT1
11
9
FB/SD
Vcc
8
Startup
16
U1
vfb
F
Figure 7. NCP1651 Applications Circuit Schematic
R28
3.3 k
C28
1 F
AND8209/D
6
http://onsemi.com
R8
680
13
vfb
4
D6
MUR160
R3
330 k
1
2
C31
C1
3900 3900
F
F
C5
2
3
F1
3
470 pF
1
Input
1
C29
0.47 F
D13
AZ23CK18
C21
2200 F
2
J1
1
2
D7
1N4006
2
D2
1N4006
L2
D8
BAS19LT1
Output
D1
1N4006
AND8209/D
DEMO BOARD TEST PROCEDURE
Table 2. Test Equipment
AC Source 85−265 Vac, 47−64 Hz
Variable Electronic Load
Digital Multimeter
Voltec Precision Power Analyzer
1. Connect the AC source to the input terminals J1.
2. Connect a variable electronic load to the output terminals J2, the PWB is marked +, for the positive output, and − for
the return.
3. Set the variable electronic load to 45 W.
4. Turn on the AC source and set it to 115 Vac at 60 Hz.
5. Verify that the NCP1651 provides 18.5 Vdc to the load.
6. Vary the load and input voltage. Verify output voltage as shown in Table 3.
Table 3. Expected Values for Varying Input Voltages and Loads
Vin (Vac)
Vo (Vdc)
@ No Load
Vo (Vdc)
@ 45 W
Vo (Vdc)
@ 90 W
THD (%)
PF
90 W
90
18.7
18.6
18.5
8.0
0.995
115
18.7
18.6
18.5
10
0.990
230
18.7
18.6
18.5
20
0.920
Table 3 shows typical values, the initial set point (18.5 Vdc may vary).
7. To verify total harmonic distortion (THD) first, shut off the AC power supply.
8. Connect the Voltec Precision Power Analyzer as shown in Figure 1.
9. Turn on the AC source to 115 Vac at 60 Hz and set the electronic load to 90 W (only measure the THD at full load).
10. Verify the voltage and current Harmonics of the circuit as shown in Table 3.
11. Shut off the power AC power supply.
12. Set the variable electronic load to 90 W.
13. Turn on the AC source and set it to 230 Vac at 60 Hz.
14. Verify the voltage and current Harmonics of the circuit as shown in Table 3.
Figure 8. NCP1651 Test Setup
http://onsemi.com
7
AND8209/D
NCP1651 DEMO BOARD TEST RESULTS
PERFORMANCE DATA
Regulation
Vin (Vac)
Pin (W)
Vo (Vdc)
IO (Adc)
PO (W)
Eff (%)
90
106.03
18.55
4.85
89.97
84.85
115
105.21
18.55
4.85
89.85
85.40
230
105.1
18.57
4.85
90.1
85.69
Standby Power
Vin (Vac)
Pin (mW)
115
372
230
455
Power Factor and THD
Vin (Vac)
PF (W)
THD (%)
PO (W)
90
0.995
8.5
90
115
0.990
9.18
90
230
0.940
19.45
90
Vendor Contact List
Vendor
U.S. Phone/Internet
ON Semiconductor
1−800−282−9855
www.onsemi.com/
TDK
1−847−803−6100
www.component.tdk.com/
Vishay
www.vishay.com/
Bussman (Cooper Ind.)
1−888−414−2645
www.cooperet.com/
Coiltronics (Cooper Ind.)
1−888−414−2645
www.cooperet.com/
Fairchild
www.fairchildsemi.com/
Panasonic
www.eddieray.com/panasonic/
Weidmuller
www.weidmuller.com/
Keystone
1−800−221−5510
www.keyelco.com/
HH Smith
1−888−847−6484 www.hhsmith.com/
Aavid Thermalloy
www.aavid.com/
http://onsemi.com
8
AND8209/D
Table 4. NCP1651 Application Circuit Parts List
Ref Des
Description
Part Number
Manufacturer
C2
Cap, Ceramic, Chip, 0.001 F, 25 V
VJ0603Y102KXXET
VISHAY
C3
Cap, Ceramic, Chip, 470 pF, 25 V
VJ0603Y471JXXET
VISHAY
C4
Cap, Aluminum Elec., 100 F, 35 V
EKB00BA310F00
VISHAY
C5
Cap, Ceramic, Chip, 470 pF, 25 V
VJ0603Y471JXXET
VISHAY
C6
Cap, Ceramic, Chip, 470 pF, 25 V
VJ0603Y471JXXET
VISHAY
C8
Cap, Ceramic, Chip, 0.022 F, 25 V
VJ0603Y223KXXET
VISHAY
C9
Cap, Ceramic, Chip, 0.01 F, 25 V
VJ0603Y103KXXET
VISHAY
C11
Cap, Ceramic, Chip, 0.012 F, 25 V
VJ0603Y123KXXET
VISHAY
C10
Cap, Ceramic, Chip, 0.001 F, 25 V
VJ0603Y102KXXET
VISHAY
C12, C13
Cap, Ceramic, Chip, 0.1 F, 25 V
VJ0606Y104KXXET
VISHAY
C16
2.2 F, Alum Elect, 450 V
(0.394 dia x 0.492H) (0.394 dia x 0.492H)
ECA−2WHG2R2
EKA00DC122P00
Panasonic (Digi–P5873)
Vishay Sprague (20)
C17
Cap, Ceramic, Chip, 22 F, 10 V
C3225X5R0J226MT
TDK
C18
Cap, Ceramic, Chip, 0.22 F, 25 V
VJ0603Y224KXXET
VISHAY
C19
Cap, Ceramic, Chip, 0.01 F, 25 V
VJ0603Y103KXXET
VJ0603Y103KXAAT
C20
Cap, Ceramic, Chip, 1.0 F, 25 V
C3216X7R1E105KT
TDK
C21
220 F, Alum Elect, 25 V
ECA1EM331
Panasonic
C1, C22, C23, C31
Cap, Alum, 3900 F, 25 V
25YXH3900M16X35.5
UHE1E392MHD
Rubycon
Nichicon
C24
Cap, Ceramic, Chip, 0.01 F, 50 V
VJ0603Y103KXAAT
VISHAY
C25
Cap, Ceramic, 0.01 F, 1.0 KV
225261148036
Vishay
C27
Cap, 1.2 F, 275 Vac
F1778−512K2KCT0
Vishay
C26, C29
Cap, Polypropylene, 0.47 F, 400 VDC
MKP1841−447−3000
Vishay−Sprague
C28
Cap, Ceramic, Chip, 1.0 F, 25 V
C3216X7R1E105KT
TDK
D1–D4
Diode, Rectifier, 800 V, 1.0 A
1N4006
ON Semiconductor
D5
Diode, Ultrafast, 200 V, 16 A
MUR20100CT
ON Semiconductor
D6
Diode, Ultrafast, 600 V, 1.0 A
MUR160
ON Semiconductor
D7
Diode, Rectifier, 800 V, 1.0 A
1N4006
ON Semiconductor
D8, D11, D14
Diode, Switching, 120 V, 200 mA, SOT−23
BAS19LT1
ON Semiconductor
D13
Zener Diode, 18 V
AZ23C18
VISHAY
F1
Fuse, 2.0 A, 250 Vac
1025TD2A
Bussman
L2
5.0 A Sat, 3.0 mH Inductor, Common Mode
Q4007−A
Coilcraft
Q1, Q2
FET, 11 A, 800 V, 0.45 ?, N−channel
SPA11N80C3
Infineon
R1
Resistor, SMT1206, 2.7
CRCW1206270JRE4
Vishey
R2
Resistor, Axial Lead, 270 k, 1/4 W
CMF−55−270K00FKRE
Vishey
R3
Resistor, Axial Lead, 270 k, 1/4 W
CMF−55−270K00FKRE
Vishey
R5
Resistor, 100 k, 3.0 W, 5%
CFP−3104JT−00K
VISHAY
R4
Resistor, SMT1206, 33 k
CRCW120633KOJNTA
Vishey
R7
Resistor, SMT1206, 8.66 k
CRCW12068661F
Vishey
R8
Resistor, SMT1206, 680
CRCW12066800F
Vishey
R10
Resistor, SMT, 0.2, 1.0 W
WSL2512 .20 1%
Vishey Dale
http://onsemi.com
9
AND8209/D
Table 4. NCP1651 Application Circuit Parts List (continued)
Ref Des
Description
Part Number
Manufacturer
R9
Resistor, Axial Lead, 5.4 k, 1/4 W
CMF−55−5K400FKBF
Vishey
R11
Resistor, SMT1206, 1.0 k
CRC12061K00JNTA
Vishey
R12
Resistor, 100 k, 3.0 W, 5%
CFP−3104JT−00K
VISHAY
R13
Resistor, SMT, 0.2, 1.0 W
WSL2512 .20 1%
Vishey Dale
R14
Resistor, SMT1206, 100
CRC12062K100JNTA
Vishey
R20
Resistor, SMT1206, 2.0 k
CRC12062K00JNTA
Vishey
R21
Resistor, SMT1206, 8.2 k
CRC12068K20JNTA
Vishey
R22
Resistor, SMT1206, 2.0 k
CRC12062K00JNTA
Vishey
R23
Resistor, SMT1206, 2.67 K, 1%
CRCW12062670F
Vishey
R26
Resistor, SMT1206, 3.3 k
CRC12063K30JNTA
Vishey
R27
Resistor, SMT1206, 7.5 k
CRC12067K50JNTA
Vishey
R28
Resistor, SMT1206, 3.3 k
CRC12063K30JNTA
Vishey
R29
Resistor, SMT1206, 2.0 k
CRC12062K00JNTA
Vishey
R30
Resistor, SMT1206, 100, 1%
CRCW12061000F
Vishey
R31
1.0 W, 0.006 Resistor
WSL251R006FTB
Vishey
R6
1.0 W, 0.006 Resistor
WSL251R006FTB
Vishey
R33
Resistor, SMT1206, 17.4 k, 1%
CRCW120617400F
Vishey
R34
Resistor, 100 k, 3.0 W, 5%
CFP−3104JT−00K
VISHAY
R35
Resistor, 100 k, 3.0 W, 5%
CFP−3104JT−00K
VISHAY
T1
Transformer, Flyback (Lp 600 H)
SRW42EC−U10H014
TDK
U1
PFC Controller
NCP1651
ON Semiconductor
U2
2.5 V Programmable Ref, SOIC
TL431ACD
ON Semiconductor
U3
Quad Op A
MC3303D
ON Semiconductor
U4
Optocoupler, 1:1 CTR, 4 Pin
SFH615AA−X007
Vishay
Part Number
Manufacturer
Hardware
Ref Des
Description
H1
Printed Circuit Board
H2
Connector
171602
Weidmuller
(Digi 281−1435−ND)
H3
Connector
171602
Weidmuller
(Digi 281−1435−ND)
4672
Keystone
4.1″ X 1.0″ X 0.05″
Manufactured
Insulator
H8, H9
Aluminum Heatsinks
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
10
For additional information, please contact your
local Sales Representative.
AND8209/D
TND317/D
Rev. 4, Jul-06
90 W Notebook AC-DC Adapter
Reference Design Documentation
Package
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
1
TND317/D
© 2006 ON Semiconductor.
Disclaimer: ON Semiconductor is providing this reference design documentation package
“AS IS” and the recipient assumes all risk associated with the use and/or
commercialization of this design package. No licenses to ON Semiconductor’s or any
third party’s Intellectual Property is conveyed by the transfer of this documentation. This
reference design documentation package is provided only to assist the customers in
evaluation and feasibility assessment of the reference design. It is expected that users
may make further refinements to meet specific performance goals.
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
2
TND317/D
Overview
This reference document describes a built-and-tested, GreenPointTM solution for
a Notebook Ac-Dc adapter.
The reference design circuit consists of one single-sided printed circuit board
designed to fit into a standard notebook adapter plastic case.
As shown in Figure 1, the reference design offers a simplified notebook adapter
power supply solution, where by judicious choice of design tradeoffs, optimum
performance is achieved at minimum cost.
Figure 1
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
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TND317/D
1 Introduction
In a not too distant past, the power requirements of notebooks adapters were in
the 50-70 W range but lately they have risen over the 100 W levels. One can
see a two-fold growth in power requirements:
• Notebook computers functionality becomes richer, so the power demand
scales up.
• Battery capacity (or density) increases, thus the charging requirements
also go up.
Crossing the threshold of 75 W input has significant consequences. In effect, 75
W is the power threshold beyond which the regulation (IEC1000-3-2) for the
reduction of harmonic currents applies to class D electrical equipments.
Notebook adapters are classified under the class D. This regulation stipulates the
maximum level of harmonic currents that class D equipment can inject on the
mains AC line. The IEC1000-3-2 regulation is currently mandatory in Europe and
Japan. In a sense, the mobile/global nature of the notebook adapters make them
the first mass market power supply to fall under the IEC1000-3-2 target.
IEC1000-3-2
Class C
Class B
YES
Lighting
Equipment ?
YES
NO
NO
Portable
Tool?
Three Phase
Equipment ?
NO
YES
Special
Waveform
P<=600W ?
YES
Motor
Equipment ?
YES
Class A
NO
NO
Class D
Figure 2
Furthermore, additional regulatory requirements addressing low standby power
consumption and efficiency in active mode for external power supply (EPS) add
extra constraints in the design of the notebook adapter.
These requirements target two issues:
• Get rid of the losses in a no load situation (e.g.: when the notebook
adapter is plugged in even when it is not connected to the computer).
• Achieve a good average efficiency during various active mode load
conditions (25%, 50%, 75% and 100%).
Semiconductor Components Industries, LLC, 2006
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TND317/D
Many regulations have been proposed around the world. Hereafter is the list of
some of the most important ones:
• Energy Star: applicable in the US and international partners
o Energy Efficiency Criteria for active mode
Nameplate Output Power
Minimum Average Efficiency in Active Mode
(Pno)
(expressed as decimal)
0 to < 1 Watt
≥ 0.49 * Pno
>1 and ≤49 Watts
≥ [0.09 * Ln(Pno)] + 0.49
> 49 Watts
≥ 0.84
o Energy Consumption Criteria for No Load
Nameplate Output Power
Maximum Energy Consumption in No-Load
(Pno)
Mode
0 to <10 Watts
≤ 0.5 Watt
≥10 to ≤ 250 Watts
≤ 0.75 Watt
• California Energy Commission:
o Effective January 1, 2007
Nameplate Output
0 to < 1 Watt
>1 and ≤49 Watts
> 49 Watts
Minimum Efficiency in Active Mode
0.49 * Nameplate Output
[0.09 * Ln(Nameplate Output)] + 0.49
0.84
Maximum Energy Consumption in No-Load
Mode
0 to <10 Watts
0.5 Watt
≥10 to ≤ 250 Watts
0.75 Watt
Where Ln (Nameplate Output) = Natural Logarithm of the nameplate output
expressed in Watts
o Effective July 1, 2008
Nameplate Output
0 to < 1 Watt
>1 and ≤51 Watts
> 51 Watts
Minimum Efficiency in Active Mode
0.5 * Nameplate Output
[0.09 * Ln(Nameplate Output)] + 0.5
0.85
Maximum Energy Consumption in No-Load
Mode
Any output
0.5 Watt
Where Ln (Nameplate Output) = Natural Logarithm of the nameplate output
expressed in Watts
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
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TND317/D
• European Union’s Code of Conduct
o No-load Power Consumption
No-load power consumption
Phase 1
Phase 2
1.1.2005
1.1.2007
0.30 W
0.30 W
0.50 W
0.30 W
0.75 W
0.30 W
1.00 W
0.50 W
Rated Output Power
> 0.3 W and < 15 W
> 15 W and < 50 W
> 50 W and < 60 W
> 60 W and < 150 W
o Energy-Efficiency Criteria for Active Mode for Phase 1 (for the
period 1.1.2005 to 31.12.2006)
Minimum Four Point
Rated Output Power
Average (see Annex) or
100 % Load Efficiency
in Active Mode
0 < W < 1.5
30
1.5 < W < 2.5
40
2.5 < W < 4.5
50
4.5 < W < 6.0
60
6.0 < W < 10.0
70
10.0 < W < 25.0
75
25.0 < W < 150.0
80
o Energy-Efficiency Criteria for Active Mode for Phase 2 (valid after
1.1.2007)
Nameplate Output Power (Pno) Minimum Four Point Average
(see Annex) or 100 % Load
Efficiency in Active Mode
(expressed as a decimal)2
0<W<1
≥ 0.49 * Pno
1 < W < 49
≥ [0.09 * Ln(Pno)] + 0.49
49 < W < 150
≥ 0.843
Notes:
2
: “Ln” refers to the natural logarithm. The algebraic order of operations requires
that the natural logarithm calculation be performed first and then multiplied by
0.09, with the resulting output added to 0.49.
An efficiency of 0.84 in decimal form corresponds to the more familiar value of
84% when expressed as a percentage.
3
: Power supplies that have a power factor correction (PFC) to comply with
EN61000-3-2 (above 75 W input power) have a 0.04 (4%) allowance, accordingly
the minimum on mode load efficiency (100% or averaged) is relaxed to 0.80
(80%).
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
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TND317/D
• Korea:
o External Power Supply -No load: 0.8 W
o Battery Charger - No load: 0.8 W
This reference design document provides a solution to address the design
challenges brought about by these regulations: compliance with IEC1000-3-2,
with requirements for standby power reduction and active mode energy efficiency
increase at a reasonable cost.
2 Notebook AC-DC adapter requirements
For Notebook OEMs, the AC-DC adapter is a commodity. So, they impose their
own stringent specifications and derating guidelines while requiring low costs.
The key performance criteria for adapters are:
• Power density (driven by package size requirements)
• Safety
• Low case temperature.
Also, since business travelers carry their notebooks around the world, all of the
AC-DC adapters for Notebooks are designed to cope with universal mains
voltage: 90 Vac to 265 Vac, 47-63 Hz.
The output power of notebook adapters varies between 50 and 125 W while the
output voltage is between 18 and 21 V.
As discussed in section 1, the IEC1000-3-2 regulation specifies the maximum
harmonic currents for class D equipments. The harmonics of the input current
shall not exceed the values given in Table 2.
Harmonic order
N
3
5
7
9
11
etc…
Maximum permissible
harmonic per watt
mA/W
3.4
1.9
1
0.5
0.35
Maximum permissible
harmonic current
A
2.30
1.114
0.77
0.40
0.33
Table 2
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
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TND317/D
3 Limitations of the existing two-stage architecture
For many years, the most effective solution (economically and technically) for
notebook adapters has been a flyback topology. If the power level of the adapter
is below 75 W, no additional power stage is needed to comply with the IEC10003-2 regulation.
For notebook adapters with >75 W power requirements, the notebook
manufacturers face the following choice. They can either design the adapters for
universal AC line voltage and include a power factor correction (PFC) stage or
they can implement separate design for markets that require PFC (Europe and
Japan). Addition of the PFC stage adds complexity and cost, thus making the
design more challenging.
A classical two-stage approach is represented in Figure 3: the Power Factor
Correction stage is followed by the Flyback stage.
Figure 3
Furthermore, while we all want maximum functionality and more crunching power
from our laptops, we also get weary of the weight and the size of the machines.
We would like to keep at least the same form factor for the adapter while more
power is needed. Size is the limitation of the classical two-stage approach as the
main elements have to be used twice: 2 magnetic elements, 2 controllers, 2
FETs.
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
8
TND317/D
4 Overcoming limitations with the NCP1651-based
single-stage flyback architecture
How to eliminate the burden of two power processing stages? Achieving an
efficient and cost effective single stage power conversion has been the quest of
the designers for a long time.
While many single stage solutions exist, they all have some limitations. These
are:
1. The output voltage ripple contains a low frequency component which can
not be inherently eliminated without using additional energy storage
capacitance.
2. Many schemes try to use current steering to achieve a better trade-off
between low output voltage ripple and low THD (Total Harmonic
Distortion). These tradeoffs require extra engineering effort for each
design.
3. Certain specifications such as output ripple, transient response and holdup time are harder to meet than the two-stage architecture.
The current reference design presents a proprietary innovative single-stage
architecture that addresses the above mentioned limitations. The enabling device
for the reference design is the NCP1651, an active power factor correction
controller designed for operation over the universal input range (85 Vac- 265
Vac) in 50/60 Hz power systems. It provides a low cost, low component count
solution for isolated AC-DC converters with mid-high output voltage requirements
and eases the task of meeting the IEC1000-3-2 harmonic requirements. The
NCP1651 uses a proprietary multiplier design that gives significantly more
accurate operation than conventional analog multipliers
To reduce output ripple and maintain harmonic currents within the class D
requirements as specified by IEC1000-3-2, the reference design utilizes a dual
loop ripple/power-factor optimization technique developed by Energy Recovery
Systems Corporation – a technology and product development company ON
Semiconductor worked with on the adapter reference design.
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
9
TND317/D
Figure 4 represents the NCP1651-based single stage solution:
Figure 4
When compared to the traditional two-stage architecture, the key advantage of
the NCP1651-based single stage architecture is the substantial cost reduction of
over 20% and the drastic component count reduction while still complying with
the IEC1000-3-2 regulation.
This architecture also brings an increase of the efficiency of about 3%. It is
important to note that the main issue is not the efficiency per se but the whether
or not this architecture meet the skin temperature rise requirements for OEMs.
These requirements as well as their test methodologies change from OEM to
OEM. This reference design complies with all of them. This reference design
also meets the leakage current OEM requirements of < 100 micro-amperes (µA).
5 Specifications
Input Voltage: Universal input 90 Vac to 265 Vac, 47-63 Hz
Output: +19.5 V, 4.62 A max (90 W) regulated
Protections:
• Short-circuit,
• Latching over-power
• Latching over-voltage
Standby Power: Pin = 390 mW @ Pout = 0 and Vin = 230 Vac
Power Factor Correction / Current Harmonics: Compliant with IEC1000-3-2
for class D
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
10
TND317/D
6 Reference design performance summary
6.1 Efficiency
% Efficien cy
92.0%
91.0%
90.0%
89.0%
88.0%
1.5 A
2.5 A
3.5 A
4.5 A
90 Vac
89.6%
90.0%
89.7%
88.8%
115 Vac
89.7%
90.5%
90.7%
90.2%
230 Vac
89.3%
90.7%
91.3%
91.3%
264 Vac
88.2%
90.0%
91.0%
91.0%
Output Current (A)
6.2 Standby Power
Pin = 390 mW @ Pout = 0 and Vin = 230 Vac
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
11
TND317/D
6.3 Power Factor Correction / Current Harmonics
Current Harmonics @ 230 Vac, 3 A
IEC1000-3-2 specification for Class D
Results
Current Harmonics @ 230 Vac, 4.6 A
IEC1000-3-2 specification for Class D
Results
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
12
TND317/D
Current Harmonics @ 100 Vac, 3 A
IEC1000-3-2 specification for Class
Result
Current Harmonics @ 100 Vac, 4.6 A
IEC1000-3-2 specification for Class D
Results
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
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TND317/D
7 Board Picture
Bottom view
Top view
8 Schematic, Board Layout, Bill-of-Materials
Complete Electrical schematics with board layout and bill-of-materials are
available from ON Semiconductor and/or from Energy Recovery Systems
Corporation.
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
14
TND317/D
9
Appendix
References:
• Draft Commission Communication on Policy Instruments to Reduce
Stand-by Losses of Consumer Electronic Equipment (19 February 1999)
o http://energyefficiency.jrc.cec.eu.int/pdf/consumer_electronics_com
munication.pdf
• European Information & Communications Technology Industry Association
o http://www.eicta.org/
• http://standby.lbl.gov/ACEEE/StandbyPaper.pdf
CECP (China):
• http://www.cecp.org.cn/englishhtml/index.asp
Energy Saving (Korea)
• http://weng.kemco.or.kr/efficiency/english/main.html#
Top Runner (Japan):
• http://www.eccj.or.jp/top_runner/index.html
EU Eco-label (Europe):
• http://europa.eu.int/comm/environment/ecolabel/index_en.htm
• http://europa.eu.int/comm/environment/ecolabel/product/pg_television_en.
htm
EU Code of Conduct (Europe):
• http://energyefficiency.jrc.cec.eu.int/html/standby_initiative.htm
GEEA (Europe):
• http://www.efficient-appliances.org/
• http://www.efficient-appliances.org/Criteria.htm
Energy Star:
• http://www.energystar.gov/
• http://www.energystar.gov/index.cfm?c=product_specs.pt_product_specs
1 Watt Executive Order:
• http://oahu.lbl.gov/
• http://oahu.lbl.gov/level_summary.html
Additional collateral from ON Semiconductor:
• AND8209/D: 90 W / 18.5 Vout, Single Stage, Notebook Adaptor
• AND8124/D: 90 W / 48 Vout, Universal Input, Single Stage, PFC Converter
• AND8147/D: An Innovative Approach to Achieving Single Stage PFC and
Step-Down Conversion for Distributive Systems.
• NCP1651: Product page for the NCP1651 on onsemi.com
• TL431
• LM358
• LM393
• MBR20H100
Semiconductor Components Industries, LLC, 2006
July, 2006 – Rev 4
15
TND317/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
TND317/D