Elantec EL5185CS 4ns high-speed comparator Datasheet

4ns High-Speed Comparator
Features
General Description
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The EL5185C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between VS+ and VS-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.
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4ns typ. propagation delay
5V to 12V input supply
+2.7V to +5V output supply
True-to-ground input
Rail-to-rail outputs
Separate analog and digital
supplies
Active low latch
Dual available (EL5285C)
Window comparator (EL5287C)
Quad available (EL5485C &
EL5486C)
Pin-compatible 6ns family
available (EL5x81C, EL5283C &
EL5482C)
EL5185C - Preliminary
EL5185C - Preliminary
The output side of the comparator can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5185C can be used to hold the comparator
output value by applying a low logic level to the pin.
The EL5185C is available in the 8-pin SO package and is specified for
operation over the -40°C to +85°C temperature range. Also available
are dual (EL5285C), window comparator (EL5287C), and quad
(EL5485C and EL5486C) versions.
Applications
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Threshold detection
High speed sampling circuits
High speed triggers
Line receivers
PWM circuits
High speed V/F converters
Pin Configuration
Ordering Information
Package
Tape & Reel
Outline #
EL5185CS
Part No.
8-Pin SO
-
MDP0027
EL5185CS-T7
8-Pin SO
7”
MDP0027
EL5185CS-T13
8-Pin SO
13”
MDP0027
VS+ 1
IN+ 2
IN- 3
8 VSD
+
-
L
A
T
C
H
VS- 4
7 OUT
6 GND
5 LATCH
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2001 Elantec Semiconductor, Inc.
September 6, 2001
EL5185CS
(8-Pin SO)
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
Absolute Maximum Ratings (T
A
= 25°C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.
Analog Supply Voltage (VS+ to VS-)
+12.6V
Digital Supply Voltage (VSD to GND)
+7V
Differential Input Voltage
[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage
[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage
Storage Temperature Range
Ambient operating Temperature
Operating Junction Temperature
Power Dissipation
ESD Voltage
-0.2V to [VSD+0.2V]
-65°C to +150°C
-40°C to +85°C
+125°C
TBDmW
2kV
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VS = ±5V, VSD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified.
Parameter
Description
Typ
Max
Unit
2
4
mV
Input Bias Current
8
15
µA
CIN
Input Capacitance
5
IOS
Input Offset Current
500
nA
VOS
Input Offset Voltage
IB
Condition
Min
VCM = 0V, VO = 2.5V
VCM = 0V, VO = 2.5V
VCM
Input Voltage Range
AVO
Large Signal Voltage Gain
CMRR
Common-mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
VLH
Latch Input Voltage High
VLL
Latch Input Voltage Low
ILH
Latch Input Current High
VLH = 3.0V
VLL = 0.3V
100
(VS-) - 0.1
-5V < VCM < +2.75V, VO = 2.5V
VSD - 0.5V
pF
(VS+) - 2V
V
5000
V/V
80
dB
60
dB
VSD - 0.4V
GND + 0.4V
V
GND + 0.5V
V
2.0
V
1
20
µA
40
80
0.8
V
ILL
Latch Input Current Low
IS +
Positive Analog Supply Current
10.5
mA
IS -
Negative Analog Supply Current
7.5
mA
IDD
Digital Supply Current
td+
Positive Going Delay Time
VOD = 5mV, CL = 15pF, IO = 2mA
4
6
ns
td-
Negative Going Delay Time
VOD = 5mV, CL = 15pF, IO = 2mA
4
6
ns
tpd+
Latch Disable to High Delay
6
ns
tpd-
Latch Disable to Low Delay
8
ns
ts
Minimum Setup Time
2
ns
th
Minimum Hold Time
1
ns
tpw(D)
Minimum Latch Disable Pulse Width
5
ns
6
2
µA
mA
4ns High-Speed Comparator
Typical Performance Curves
10
Supply Current vs Supply Voltage
(per comparator)
VIN=50mV
RL=2.2k
Output High Voltage vs Temperature
4.832
4.83
IS+
8
VOH (V)
IS (mA)
4.828
6
I S-
4
4.826
4.824
4.822
2
4.82
4.818
-50
0
0
1
2
3
4
5
6
-30
-10
10
30
50
70
90
50
70
90
50
70
90
Temperature (°C)
±VS (V)
Input Bias Current vs Temperature
Offset Voltage vs Temperature
3
8
7
2.5
6
5
IB (µA)
VOS (mV)
2
1.5
4
3
1
2
0.5
1
0
-50
-30
-10
10
30
50
70
0
-50
90
-30
-10
Temperature (°C)
Output Low Voltage vs Temperature
0.285
12
Supply Current (mA)
VOL (V)
30
Supply Current vs Temperature
(per comparator)
11
0.275
0.265
0.255
0.245
0.235
-50
10
Temperature (°C)
I S+
10
9
8
IS-
7
-30
-10
10
30
50
70
6
-50
90
Temperature (°C)
-30
-10
10
30
Temperature (°C)
3
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
Typical Performance Curves
7.8
Propagation Delay vs Overdrive
VIN=5VSTEP
15
VS=±5V
VSD=5V
RL=2.2k
7.6
TPD-
Propagation Delay vs Source Resistance
VIN=1VSTEP
VS=±5V
VSD=5V
VOD=50mV
RL=2.2k
13
Delay Time (ns)
Delay Time (ns)
7.4
7.2
TPD+
7
11
TPD9
TPD+
6.8
7
6.6
5
6.4
0.2
0.6
1
1.4
1.8
2.2
2.6
0.4
0
Propagation Delay vs Supply Voltage
6.8
25
VSD=VS+
VOD=50mV
RL=2.2k
6.6
1.2
1.6
2
Digital Supply Current vs Switching Frequency
(per comparator)
VS=±5V
TA=25°C
20
6.4
6.2
ISD (mA)
Delay Time (ns)
0.8
Source Resistance (kΩ)
VOD (V)
TPD-
15
VSD=5V
10
VSD=3V
6
5.8
5.6
5
TPD+
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
0
6
10
0
Propagation Delay vs Overdrive
VIN=1VSTEP
8
VS=±5V
VSD=5V
RL=2.2k
6
5.9
5.8
50
Propagation Delay vs Overdrive
VIN=3VSTEP
VS=±5V
VSD=5V
RL=2.2k
7.5
TPD-
5.7
5.6
5.5
TPD-
7
6.5
TPD+
6
TPD+
5.4
5.5
5.3
5.2
50
40
Frequency (MHz)
Delay Time (ns)
6.1
30
20
±VS (V)
Delay Time (ns)
EL5185C - Preliminary
EL5185C - Preliminary
5
0.2
100 150 200 250 300 350 400 450 500 550 600
VOD (mV)
0.4
0.6
0.8
1
1.2
VOD (mV)
4
1.4
1.6
1.8
2
4ns High-Speed Comparator
Typical Performance Curves
Propagation Delay vs Load Capacitance
VIN=1VSTEP
VS=±5V
VSD=5V
VOD=50mV
RL=2.2k
8.5
8
Delay Time (ns)
0.7
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
0.6
7.5
Power Dissipation (W)
9
TPD-
7
6.5
TPD+
6
625mW
0.5
16
0°
C
0.4
SO
8
/W
0.3
0.2
0.1
5.5
5
0
10
20
30
40
50
60
70
80
90
0
100
CLOAD (pF)
0
25
50
75 85
100
Ambient Temperature (°C)
Output with 50MHz Input
VIN=3VP-P
Output with 50MHz Input
VIN=1VP-P
Output
(5ns/div,
2V/div)
Output
(5ns/div,
2V/div)
Input
(5ns/div,
0.5V/div)
Input
(5ns/div,
2V/div)
5
125
150
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Differential
Input
Voltage
ts
Latch
th
tpw(D)
VIN
VOS
VOD
tpd-
td+
Comparator
Output
2.4V
Definition of Terms
Term
Definition
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
tpd+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
tpd-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
td+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
td-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
ts
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
th
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
tpw (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
6
4ns High-Speed Comparator
Pin Descriptions
Pin Number
Pin Name
1
VS+
Positive supply voltage
Function
2
IN+
Positive input
Equivalent Circuit
VS+
IN-
IN+
VSCircuit 1
3
IN-
Negative input
4
VS-
Negative supply voltage
5
LATCH
(Reference Circuit 1)
Latch input
VS+
VSD
LATCH
VSCircuit 2
6
GND
Digital ground
7
OUT
Output
VSD
V S+
OUT
VSCircuit 3
8
VSD
Digital Supply
7
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
Applications Information
Power Supplies and Circuit Layout
may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5185C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
The EL5185C comparator operates with single and dual
supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply
from 2.7V to 5V. The rail to rail output swing enables
direct connection of the comparator to both CMOS and
TTL logic circuits. As with many high speed devices,
the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance stability of the comparators.
Latch Pin Dynamics
The EL5185C contains a “transparent” latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
remains latched to its value just before the latch’s highto-low transition. To guarantee data retention, the input
signal must remain the same state at least 1ns (hold time)
after the latch goes low and at least 2ns (setup time)
before the latch goes low. When the latch goes high, the
new data will appear at the output in approximately 6ns
(latch propagation delay).
Input Voltage Considerations
The EL5185C input range is specified from 0.1V below
V S- to 2.25V below VS+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage.
Hysteresis
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
VREF
R3
R2
R1
Input Slew Rate
VIN
+
-
R3 adds a portion of the output to the threshold set by R 1
and R2 . The calculation of the resistor values are as
follows:
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain minimum slew rate requirements. In some applications, it
Select the threshold voltage VTH and calculate R1 and
R2. The current through R1/R2 bias string must be many
8
4ns High-Speed Comparator
The above two methods will generate hysteresis of up to
a few hundred millivolts. Beyond that, the impedance of
R3 is low enough to affect the bias string and adjustment
of R1 may be required.
times greater than the input bias current of the
comparator:
R1
V T H = V REF × ------------------R1 + R2
Power Dissipation
Let the hysteresis be VH, and calculate R3:
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
TJMAX (125°C).
VO
- × ( R 1 || R 2 )
R 3 = ------VH
where:
An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the
load is very small:
VO=VSD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:
 V TH V T H – 0.5V SD 
R 2 1 = ( V REF – V T H ) ÷  ----------+ ------------------------------------- 
R3
 R1

P DISS = ( V S × I S + V SD × I SD )
Non inverting comparator with hysteresis:
where:
VS is the analog supply voltage from VS+ to VS-
R3
VIN
R1
VREF
IS is the analog quiescent supply current per comparator
+
-
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation, the maximum junction temperature can be
determined as follows:
R3 adds a portion of the output to the positive input.
Note that the current through R3 should be much greater
than the input bias current in order to minimize errors.
The calculation of the resistor values as follows:
Pick the value of R1. R1 should be small (less than 1kΩ)
in order to minimize the propagation delay time.
T JMAX = T MAX + Θ JA × P DISS
Choose the hysteresis VH and calculate R3:
where:
R
R 3 = ( V SD – 0.8 ) × -------1V
TMAX is the maximum ambient temperature
H
θJA is the thermal resistance of the package
Check the current through R3 and make sure that it is
much greater than the input bias current as follows:
Threshold Detector
The inverting input is connected to a reference voltage
and the non-inverting input is connected to the input. As
the input passes the VREF threshold, the comparator's
0.5VSD – V REF
I = ---------------------------------------R3
9
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
output changes state. The non-inverting and inverting
inputs may be reversed.
VIN
VREF
+
-
VOUT
Crystal Oscillator
A simple crystal oscillator using one comparator of an
EL5185C is shown below. The resistors R1 and R2 set
the bias point at the comparator's non-inverting input.
Resistors R3, R4, and C1 set the inverting input node at
an appropriate DC average voltage based on the output.
The crystal's path provides resonant positive feedback
and stable oscillation occurs. Although the EL5185C
will give the correct logic output when an input is outside the common mode range, additional delays may
occur when it is so operated. Therefore, the DC bias
voltages at the inputs are set about 500mV below the
center of the common mode range and the 200Ω resistor
attenuates the feedback to the non-inverting input. The
circuit will operate with most AT-cut crystal from 1MHz
to 8MHz over a 2V to 7V supply range. The output duty
cycle for this circuit is roughly 50% at 5V VCC, but it is
affected by the tolerances of the resistors. The duty cycle
can be adjusted by changing VCC value.
5V
200Ω
R1
5kΩ
R2
1.5kΩ
+
-
1MHz to
8MHz
VOUT
R3
C1
R4
0.01µF
2kΩ
2kΩ
10
EL5185C - Preliminary
EL5185C - Preliminary
4ns High-Speed Comparator
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
September 6, 2001
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
11
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