TI BQ24740RHDT Host-controlled multi-chemistry battery charger with low input power detect Datasheet

bq24740
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SLUS736 – DECEMBER 2006
Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
LODRV
PGND
REGN
HIDRV
PH
DPMDET
ACN
2
20
CELLS
ACP
3
bq24740
19
SRP
LPMD
4
28 LD QFN
18
SRN
ACDET
5
TOP VIEW
17
BAT
ACSET
6
16
SRSET
LPREF
7
15
IADAPT
9
10 11 12 13 14
EXTPWR
8
ISYNSET
•
21
VADJ
•
CHGEN
VREF
•
28 27 26 25 24 23 22
1
VDAC
•
•
•
The bq24740 charges two, three, or four series Li+
cells, supporting up to 10 A of charge current, and is
available in a 28-pin, 5x5-mm thin QFN package.
BTST
•
The bq24740 is a high-efficiency, synchronous
battery charger with integrated compensation and
system power selector logic, offering low component
count for space-constrained multi-chemistry battery
charging applications. Ratiometric charge current
and voltage programming allows very high regulation
accuracies, and can be either hardwired with
resistors
or
programmed
by
the
system
power-management microcontroller using a DAC or
GPIOs.
AGND
•
DESCRIPTION
PVCC
•
Notebook and Ultra-Mobile Computers
Portable Data-Capture Terminals
Portable Printers
Medical Diagnostics Equipment
Battery Bay Chargers
Battery Back-up Systems
IADSLP
•
NMOS-NMOS Synchronous Buck Converter
with 300 kHz Frequency and >95% Efficiency
30-ns Minimum Driver Dead-time and 99.5%
Maximum Effective Duty Cycle
High-Accuracy Voltage and Current
Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy
Integration
– Internal Loop Compensation
– Internal Soft Start
Safety
– Input Overvoltage Protection (OVP)
– Dynamic Power Management (DPM) with
Status Indicator
– Reverse-Conduction Protection Input FET
Supports Two, Three, or Four Li+ Cells
5 – 24 V AC/DC-Adapter Operating Range
Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO Host Control
– Charge Voltage (4-4.512 V/cell)
– Charge Current (up to 10 A, with 10-mΩ
sense resistor)
– Adapter Current Limit (DPM)
Status and Monitoring Outputs
– AC/DC Adapter Present with
Programmable Voltage Threshold
– Low Input-Power Detect with Adjustable
Threshold and Hysteresis
– DPM Loop Active
– Current Drawn from Input Source
Battery Discharge Current Sense with No
Adapter, or Selectable Low-Iq mode
Supports Any Battery Chemistry: Li+, NiCd,
NiMH, Lead Acid, etc.
Charge Enable
10-µA Off-State Current
28-pin, 5x5-mm QFN package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq24740
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SLUS736 – DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adapter when
supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables
precise measurement of input current from the AC adapter to monitor the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
power performance according to what is available from the adapter.
TYPICAL APPLICATION
C16
10 mF
C17
10 mF
C18
10 mF
SYSTEM
ADAPTER+
ADAPTER-
C1
10 mF
RAC
P
P
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
C2
HOST
R1
0.1 mF
432 kW
1%
C6
C7
10 mF 10 mF
0.010 W
C3
0.1 mF
ACN
PVCC
C8
1 mF
ACP
ACDET
bq24740
R3
10 kW
PH
BTST
EXTPWR
EXTPWR
D1
BAT54
C9
L1
0.1 mF
8.2 mH
C10
1 mF
DAC
ACSET
LODRV
VREF
R5
10 kW
N
R4
10 kW
C4
1 mF
BAT
VREF
CELLS
R7
200 kW
CHGEN
LPREF
VDAC
ISYNSET
VADJ
IADAPT
C5
C14
0.1 mF
SRN
LPMD
ADC
C13
0.1 mF
Q5
FDS6680A
SRP
DPMDET
DAC
PACK+
C12
10 mF
PGND
IADSLP
HOST
R SR
0.010 W
C11
10 mF
REGN
SRSET
P
Q4
FDS6680A
HIDRV
AGND
VREF
N
R2
66.5 kW
1%
PowerPad
R6
33 kW
C15
0.1 mF
R8
24.9 kW
100 pF
R9 1.8 MW
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers .
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC
2
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Q3(BATFET)
SI4435
Controlled by
HOST
PACK-
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SLUS736 – DECEMBER 2006
C16
10 mF
C17
10 mF
C18
10 mF
SYSTEM
ADAPTER+
ADAPTER-
RAC
C1
10 mF
P
P
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
C2
HOST
R1
0.1 mF
432 kW
1%
C6
C7
10 mF 10 mF
0.010 W
C3
0.1 mF
ACN
PVCC
C8
1 mF
ACP
ACDET
bq24740
R3
10 kW
PH
BTST
EXTPWR
EXTPWR
D1
R9
42 kW
R11
66.5 kW
SRSET
ACSET
R4
10 kW
R5
10 kW
GPIO
8.2 mH
R SR
0.010 W
PACK+
C12
10 mF
C11
10 mF
LODRV
C13
0.1 mF
Q5
FDS6680A
PACK-
C14
0.1 mF
PGND
C4
1 mF
IADSLP
SRP
DPMDET
SRN
LPMD
BAT
CHGEN
VREF
R7
200 kW
LPREF
ISYNSET
VDAC
R6
33 kW
VADJ
IADAPT
C5
0.1 mF
C10
1 mF
CELLS
ADC
L1
N
VREF
HOST
C9
REGN
R10
100 kW
R12 100 kW
BAT54
P
Q4
FDS6680A
HIDRV
AGND
VREF
N
R2
66.5 kW
1%
Q3(BATFET)
SI4435
Controlled by
HOST
C15
0.1 mF
R8
24.9 kW
PowerPad
100 pF
R9 1.8 MW
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers.
A.
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor
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C17
10 mF
C18
10 mF
C19
10 mF
ADAPTER +
ADAPTER -
SYSTEM
C1
10 mF
R1
P
RAC
0.010 W
P
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
HOST
C2
0.1 mF
432 kW
1%
C6
10 mF
C7
10 mF
C3
ACN
0.1 mF
PVCC
C8
ACP
1 mF
Q3(BATFET)
SI4435
Controlled by
HOST
ACDET
VREF
R3
bq24740
10 kW
PH
BTST
EXTPWR
/EXTPWR
N
R2
D1
BAT54
C10
1 mF
L1
C9
0.1 mF
DAC
PACK+
C13
0.1 mF
Q5
FDS6680A
LODRV
10 kW R5
10 kW
1 mF
PGND
IADSLP
HOST
BAT
VREF
CELLS
CHGEN
ISYNSET
R6
33 kW
VADJ
IADAPT
C15
0.1 mF
R7
200 kW
LPREF
VDAC
C5
0.1 mF
SRN
LPMD
ADC
C14
SRP
DPMDET
DAC
PACK-
N
R4
C4
C12
10 mF
C11
10 mF
ACSET
VREF
RSR
0.010 W
8.2 mH
REGN
SRSET
P
Q4
FDS6680A
HIDRV
AGND
66.5 kW
1%
R8
24.9 kW
PowerPad
100 pF
R9
(1) Pull-up rail could be either VREF or other system rail
1.8 MW
.
(2) SRSET/ACSET could come from either DAC or resistor dividers .
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 3. Typical System Schematic: Sensing Battery Discharge Current, When Adapter Removed. (Set
IADSLP at logic high)
ORDERING INFORMATION
Part number
Package
bq24740
28-PIN 5 x 5 mm QFN
Ordering Number
(Tape and Reel)
Quantity
bq24740RHDR
3000
bq24740RHDT
250
PACKAGE THERMAL DATA
(1)
(2)
4
PACKAGE
θJA
TA = 70°C POWER RATING
DERATING FACTOR ABOVE TA = 25°C
QFN – RHD (1) (2)
39°C/W
2.36 W
0.028 W/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN
TERMINAL
NAME
NO.
DESCRIPTION
CHGEN
1
Charge enable active-low logic input. LO enables charge. HI disables charge.
ACN
2
Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering.
ACP
3
Adapter current sense resistor, positive input. (See comments with ACN description)
4
Low power mode detect active-high open-drain logic output. Place a 10-kΩ pullup resistor from LPMD pin to the
pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see
design example for calculation). The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The
output is LO when IADAPT pin voltage is higher than LPREF pin voltage.
5
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The
IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV,
disables charge and ACDRV when ACDET > 3.1 V. ACOV does not latch
6
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply
to the VDAC pin.
7
Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference for
the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is given
on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs the
hysteresis.
IADSLP
8
Enable IADAPT to enter sleep mode; active-low logic input. Allows low Iq sleep mode when adapter not detected.
Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is <0.6
V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not
detected and ACDET pin is <0.6 V - this allows measuring battery discharge current.
AGND
9
Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power
pad underneath the IC.
VREF
10
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation.
VDAC
11
Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery
voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,
SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins
to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output
to VADJ, SRSET, or ACSET.
VADJ
12
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the
default of 4.2 V per cell.
EXTPWR
13
Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed
threshold, OR input current is greater than 1.25 A with 10-mΩ sense resistor. Connect a 10-kΩ pullup resistor from
EXTPWR pin to pullup supply rail.
ISYNSET
14
Synchronous mode voltage set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent
threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor
current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).
IADAPT
15
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
SRSET
16
Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current
regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.
BAT
17
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter
high-frequency noise.
SRN
18
Charge current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering.
SRP
19
Charge current sense resistor, positive input. (See comments for SRN.)
CELLS
20
2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
LPMD
ACDET
ACSET
LPREF
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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)
TERMINAL
NAME
NO.
DESCRIPTION
DPMDET
21
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a
different pullup-supply rail.
PGND
22
Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input
and output capacitors of the charger. Only connect to AGND through the power pad underneath the IC.
LODRV
23
PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
REGN
24
PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
PH
25
PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from from PH to
BTST.
HIDRV
26
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST
27
PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a
small bootstrap Schottky diode from REGN to BTST.
PVCC
28
IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse-blocking power P-channel MOSFET. Place a 1-µF ceramic capacitor from PVCC to PGND pin
close to the IC.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
VALUE
PVCC, ACP, ACN, SRP, SRN, BAT
Voltage range
Maximum difference voltage
–1 to 30
REGN, LODRV, VADJ, ACSET, SRSET, ACDET, ISYNSET, LPMD,
LPREF, CHGEN, CELLS, EXTPWR, DPMDET
–0.3 to 7
VDAC
–0.3 to 5.5
VREF
–0.3 to 3.6
BTST, HIDRV with respect to AGND and PGND, IADAPT
–0.3 to 36
ACP–ACN, SRP–SRN, AGND–PGND
–0.5 to 0.5
–40 to 155
Storage temperature range
–55 to 155
(2)
6
–0.3 to 30
PH
Junction temperature range
(1)
UNIT
V
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
PH
NOM
MAX
–1
24
PVCC, ACP, ACN, SRP, SRN, BAT
0
24
REGN, LODRV
0
6.5
VREF
0
3.3
VDAC, IADAPT
0
3.6
ACSET, SRSET, ACDET, ISYNSET, LPMD, LPREF, CHGEN, CELLS,
EXTPWR, DPMDET
0
5.5
VADJ
0
6.5
BTST, HIDRV with respect to AGND and PGND
0
30
–0.3
0.3
Junction temperature range
–40
125
Storage temperature range
–55
150
Voltage range
AGND, PGND
Maximum difference voltage: ACP–ACN, SRP–SRN
UNIT
V
5.5
°C
PACKAGE THERMAL DATA
θJA
TA = 70°C POWER RATING
DERATING FACTOR ABOVE TA = 25°C
39°C/W
2.36W
0.028 W/°C
PACKAGE
QFN–
(1)
RHD (1)
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
ELECTRICAL CHARACTERISTICS
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
24.0
V
OPERATING CONDITIONS
VPVCC_OP
PVCC Input voltage operating range
5.0
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG
BAT voltage regulation range
VVDAC_OP
VDAC reference voltage range
VADJ_OP
VADJ voltage range
4V-4.512V per cell, times 2,3,4 cell
Charge voltage regulation accuracy
Charge voltage regulation set to default to
4.2 V per cell
8
18
V
2.6
3.6
V
V
0
REGN
8 V, 8.4 V, 9.024 V
–0.5
0.5
12 V, 12.6 V, 13.536 V
–0.5
0.5
16 V, 16.8 V, 18.048 V
–0.5
0.5
VADJ connected to REGN, 8.4 V,
12.6 V, 16.8 V
–0.5
0.5
0
100
0
VDAC
VIREG_CHG = 40–100 mV
–3
3
VIREG_CHG = 20 mV
–5
5
VIREG_CHG = 5 mV
–25
25
VIREG_CHG = 1.5 mV
–33
33
%
%
CHARGE CURRENT REGULATION
VIREG_CHG
Charge current regulation differential
voltage range
VSRSET_OP
SRSET voltage range
Charge current regulation accuracy
VIREG_CHG = VSRP– VSRN
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V
%
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
INPUT CURRENT REGULATION
VIREG_DPM
Adapter current regulation differential
voltage range
VACSET_OP
ACSET voltage range
Input current regulation accuracy
VIREG_DPM = VACP– VACN
0
200
0
2
VIREG_DPM = 40–100 mV
–3
3
VIREG_DPM = 20 mV
–5
5
VIREG_DPM = 5 mV
–25
25
VIREG_DPM = 1.5 mV
–33
33
V
%
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VACDET > 0.6 V, 0-30 mA
3.267
IVREF_LIM
VREF current limit
VVREF = 0 V, VACDET > 0.6 V
35
3.3
3.333
V
75
mA
6.2
V
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VACDET > 0.6 V, 0-75 mA, PVCC > 10
V
5.6
5.9
IREGN_LIM
REGN current limit
VREGN = 0 V, VACDET > 0.6 V
90
135
mA
0
24
V
ADAPTER CURRENT SENSE AMPLIFIER
VACP/N_OP
Input common mode range
Voltage on ACP/SRN
VIADAPT
IADAPT output voltage range
0
2
V
IIADAPT
IADAPT output current
0
1
mA
AIADAPT
Current sense amplifier voltage gain
Adapter current sense accuracy
AIADAPT = VIADAPT / VIREG_DPM
20
V/V
VIREG_DPM = 40–100 mV
–2
VIREG_DPM = 20 mV
–3
3
VIREG_DPM = 5 mV
–25
25
VIREG_DPM = 1.5 mV
–30
30
IIADAPT_LIM
Output current limit
VIADAPT = 0 V
CIADAPT_MAX
Maximum output load capacitance
For stability with 0 mA to 1 mA load
2
1
%
mA
100
pF
24
V
2.424
V
ACDET COMPARATOR
VPVCC-BAT_OP
Differential Voltage from PVCC to BAT
VACDET_CHG
ACDET adapter-detect rising threshold
VACDET_CHG_HYS ACDET falling hysteresis
VACDET_BIAS
–20
Min voltage to enable charging,
VACDET rising
2.40
518
700
VACDET falling
ACDET rising deglitch (1)
VACDET rising
ACDET falling deglitch
VACDET falling
ACDET enable-bias rising threshold
Min voltage to enable all bias, VACDET
rising
VACDET_BIAS_HYS Adapter present falling hysteresis
ACDET rising deglitch
2.376
(1)
ACDET falling deglitch
40
mV
908
0.56
0.62
VACDET falling
20
VACDET rising
10
VACDET falling
10
ms
µs
10
0.68
V
mV
µs
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC Over-voltage rising threshold on
ACDET
(See ACDET in erminal Functions)
VACOV_HYS
AC Over-voltage rising deglitch
1.3
AC Over-voltage falling deglitch
1.3
(1)
8
Verified by design.
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3.1
3.193
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
250
300
mV
AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT)
VACIDET
Adapter current detect rising threshold
VACI = IAC× RAC× 20, falling edge
VACIDET_HYS
Adapter current detect hysteresis
Rising edge
50
mV
PVCC / BAT COMPARATOR (REVERSE DISCHARGING PROTECTION)
VPVCC-BAT_FALL
PVCC to BAT falling threshold
VPVCC-BAT__HYS
PVCC to BAT hysteresis
VPVCC– VBAT to turn off ACFET
140
185
240
50
PVCC to BAT Rising Deglitch
VPVCC– VBAT > VPVCC-BAT_RISE
10
PVCC to BAT Falling Deglitch
VPVCC– VBAT < VPVCC-BAT_FALL
6
mV
mV
µs
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO
AC Under-voltage rising threshold
Measure on PVCC
VUVLO_HYS
AC Under-voltage hysteresis, falling
3.5
4
4.5
260
V
mV
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE
VOV_FALL
Over-voltage rising threshold
(2)
Over-voltage falling threshold
(2)
104
As percentage of VBAT_REG
%
102
CHARGE OVER-CURRENT COMPARATOR
VOC
Charge over-current falling threshold
As percentage of IREG_CHG
Minimum Current Limit (SRP-SRN)
145
%
50
mV
INPUT CURRENT LOW-POWER MODE COMPARATOR
VACLP_HYS
AC low power hysteresis
VACLP_OFFSET
AC low power rising threshold
2.8
mV
1
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis, falling
Temperature Increasing
155
°C
20
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver turn-on resistance
VBTST– VPH = 5.5 V, tested at 100 mA
3
6
RDS_HI_OFF
High side driver turn-off resistance
VBTST– VPH = 5.5 V, tested at 100 mA
0.7
1.4
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST– VPH when low side refresh
pulse is requested
4
Ω
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver turn-on resistance
REGN = 6 V, tested at 100 mA
3
6
RDS_LO_OFF
Low side driver turn-off resistance
REGN = 6 V, tested at 100 mA
0.6
1.2
Ω
PWM DRIVERS TIMING
Driver Dead Time — Dead time when
switching between LODRV and HIDRV.
No load at LODRV and HIDRV
30
ns
PWM OSCILLATOR
FSW
PWM switching frequency
VRAMP_HEIGHT
PWM ramp height
(2)
240
As percentage of PVCC
360
6.6
kHz
%PVCC
Verified by design.
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 85°C
7
10
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 125°C
7
11
UNIT
QUIESCENT CURRENT
IOFF_STATE
Total off-state battery current from SRP,
SRN, BAT, VCC, BTST, PH, etc.
µA
IBAT_ON
Battery on-state quiescent current
VBAT = 16.8V, 0.6V < VACDET < 2.4V,
VPVCC > 5V
1
IBAT_LOAD_CD
Internal battery load current, charge
disbled
Charge is disabled:
VBAT = 16.8 V, VACDET > 2.4 V,
VPVCC > 5 V
3
5
mA
IBAT_LOAD_CE
Internal battery load current, charge
enabled
Charge is enabled:
VBAT = 16.8 V, VACDET > 2.4 V,
VPVCC > 5 V
10
12
mA
IAC
Adapter quiescent current
VPVCC = 20 V, charge disabled
2.8
4
mA
IAC_SWITCH
Adapter switching quiescent current
VPVCC = 20 V, Charge enabled,
converter running, total gate charge =
2 × 10 nC
25
mA
8
step
1.7
ms
6
mA
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps
Soft start step time
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected
to when the charger is allowed to turn
on
518
700
908
ms
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYSNCHRONOUS TRANSITION)
AISYNSET
Accuracy
5 mV
Gain
ISYNSET amplifier gain
–20
%
V/I
1
V
ISYNSET rising deglitch
20
µs
ISYNSET falling deglitch
640
µs
ISYNSET pin voltage
VISYNSET
20
250
LOGIC IO PIN CHARACTERISTICS (CHGEN, IADSLP )
VIN_LO
Input low threshold voltage
VIN_HI
Input high threshold voltage
VBIAS
Input bias current
0.8
V
1
µA
2.1
VCHGEN = 0 to VREGN
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
VIN_LO
Input low threshold voltage, 3 cells
CELLS voltage falling edge
VIN_MID
Input mid threshold voltage, 2 cells
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.8
0.5
VIN_HI
Input high threshold voltage, 4 cells
CELLS voltage rising
2.5
IBIAS_FLOAT
Input bias float current for 2-cell selection
V
= 0 to V
–1
1.8
1
V
µA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (EXTPWR)
VOUT_LO
Output low saturation voltage
Sink Current = 4 mA
Delay, EXTPWR falling
518
Delay, EXTPWR rising
700
0.5
V
908
ms
µs
10
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET, LPMD)
VOUT_LO
Output low saturation voltage
Sink Current = 5 mA
Delay, rising/falling
10
0.5
10
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SLUS736 – DECEMBER 2006
TYPICAL CHARACTERISTICS
Table of Graphs (1)
Y
X
FIgure
VREF Load and Line Regulation
vs Load Current
Figure 4
REGN Load and Line Regulation
vs Load Current
Figure 5
BAT Voltage
vs VADJ/VDAC Ratio
Figure 6
Charge Current
vs SRSET/VDAC Ratio
Figure 7
Input Current
vs ACSET/VDAC Ratio
Figure 8
BAT Voltage Regulation Accuracy
vs Charge Current
Figure 9
BAT Voltage Regulation Accuracy
Figure 10
Charge Current Regulation Accuracy
Figure 11
Input Current Regulation (DPM) Accuracy
Figure 12
VIADAPT Input Current Sense Amplifier Accuracy
Figure 13
Input Regulation Current (DPM), and Charge Current
vs System Current
Figure 14
Transient System Load (DPM) Response
Figure 15
Charge Current Regulation
vs BAT Voltage
Figure 16
Efficiency
vs Battery Charge Current
Figure 17
Battery Removal (from Constant Current Mode)
Figure 18
REF and REGN Startup
Figure 19
Charger on Adapter Removal
Figure 20
Charge Enable / Disable and Current Soft-Start
Figure 21
Nonsynchronous to Synchronous Transition
Figure 22
Synchronous to Nonsynchronous Transition
Figure 23
Near 100% Duty Cycle Bootstrap Recharge Pulse
Figure 24
Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation
Figure 25
Continuous Conduction Mode (CCM) Switching Waveforms
Figure 26
Discontinuous Conduction Mode (DCM) Switching Waveforms
Figure 27
Test results based on Figure 2 application schematic. VIN = 20 V, VBAT = 3-cell LiIon, ICHG = 3 A, IADAPTER_LIMIT = 4 A, TA = 25°C, unless
otherwise specified.
VREF LOAD AND LINE REGULATION
vs
Load Current
REGN LOAD AND LINE REGULATION
vs
LOAD CURRENT
0
0.50
0.40
-0.50
Regulation Error - %
Regulation Error - %
(1)
0.30
PVCC = 10 V
0.20
0.10
0
-1
-1.50
PVCC = 10 V
-2
PVCC = 20 V
-0.10
-2.50
-0.20
-3
PVCC = 20 V
0
10
20
30
VREF - Load Current - mA
40
50
0
Figure 4.
10
20
30
40
50
60
REGN - Load Current - mA
70
80
Figure 5.
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BAT VOLTAGE
vs
VADJ/VDAC RATIO
CHARGE CURRENT
vs
SRSET/VDAC RATIO
10
18.2
VADJ = 0 -VDAC,
4-Cell,
No Load
Voltage Regulation - V
17.8
SRSET Varied,
4-Cell,
Vbat = 16 V
9
Charge Current Regulation - A
18
17.6
17.4
17.2
17
16.8
16.6
16.4
8
7
6
5
4
3
2
1
16.2
0
16
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1
0.1
0.2
0.3
VADJ/VDAC Ratio
0.8
0.9
Figure 6.
Figure 7.
INPUT CURRENT
vs
ACSET/VDAC RATIO
BAT VOLTAGE REGULATION ACCURACY
vs
CHARGE CURRENT
1
0.2
10
ACSET Varied,
4-Cell,
Vbat = 16 V
8
Vreg = 16.8 V
0.1
Regulation Error - %
9
Input Current Regulation - A
0.4
0.5
0.6
0.7
SRSET/VDAC Ratio
7
6
5
4
3
0
-0.1
2
1
-0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
ACSET/VDAC Ratio
0.8
0.9
0
1
2000
Figure 8.
BAT VOLTAGE REGULATION ACCURACY
CHARGE CURRENT REGULATION ACCURACY
4-Cell, VBAT = 16 V
1
VADJ = 0 -VDAC
SRSET Varied
0
-1
0.04
Regulation Error - %
Regulation Error - %
8000
2
0.06
4-Cell, no load
0.02
0
-0.02
-0.04
-0.06
-0.10
16.5
-2
-3
-4
-5
-6
-7
-8
-0.08
-9
-10
17
17.5
18
18.5
19
0
V(BAT) - Setpoint - V
Figure 10.
12
6000
Figure 9.
0.10
0.08
4000
Charge Current - mA
2
4
I(CHRG) - Setpoint - A
Figure 11.
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SLUS736 – DECEMBER 2006
INPUT CURRENT REGULATION (DPM) ACCURACY
VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY
5
10
ACSET Varied
9
0
7
4-Cell, VBAT = 16 V
6
Percent Error
Regulation Error - %
8
5
4
3
2
VI = 20 V, CHG = EN
-5
VI = 20 V, CHG = DIS
-10
-15
1
0
-20
-1
-2
-25
Iadapt Amplifier Gain
0
1
2
3
4
Input Current Regulation Setpoint - A
5
0
6
1
2
3
4
5
6
I(ACPWR) - A
7
8
9
10
Figure 12.
Figure 13.
INPUT REGULATION CURRENT (DPM), AND CHARGE
CURRENT
vs
SYSTEM CURRENT
TRANSIENT SYSTEM LOAD (DPM) RESPONSE
5
VI = 20 V,
4-Cell,
Vbat = 16 V
4
Ichrg and Iin - A
Input Current
3
Charge Current
2
1
0
0
1
2
System Current - A
3
4
Figure 14.
Figure 15.
CHARGE CURRENT REGULATION
vs
BAT VOLTAGE
EFFICIENCY
vs
BATTERY CHARGE CURRENT
5
100
V(BAT) = 16.8 V
Efficiency - %
Charge Current - A
4
3
2
90
Vreg = 12.6 V
Vreg = 8.4 V
80
1
Ichrg_set = 4 A
70
0
0
2
4
6
8
10
12
Battery Voltage - V
14
16
18
0
Figure 16.
2000
6000
4000
Battery Charge Current - mA
8000
Figure 17.
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14
BATTERY REMOVAL
REF AND REGN STARTUP
Figure 18.
Figure 19.
CHARGER ON ADAPTER REMOVAL
CHARGE ENABLE / DISABLE AND CURRENT
SOFT-START
Figure 20.
Figure 21.
NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION
SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION
Figure 22.
Figure 23.
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SLUS736 – DECEMBER 2006
NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE
PULSE
BATTERY SHORTED CHARGER RESPONSE,
OVERCURRENT PROTECTION (OCP) AND CHARGE
CURRENT REGULATION
Figure 24.
Figure 25.
CONTINUOUS CONDUCTION MODE (CCM) SWITCHING
WAVEFORMS
DISCONTINUOUS CONDUCTION MODE (DCM)
SWITCHING WAVEFORMS
Figure 26.
Figure 27.
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FUNCTIONAL BLOCK DIAGRAM
ENA_BIAS_CMP
-
0.6V
700 ms
AC VGOOD
-
2.4V
+
ACDET
3.3V
LDO
VREF
ENA_BIAS
V(IADAPT)
EAO
EAI
EXTPWR
Delay
Rising
+
+
AC IGOOD
CHGEN
-
PVCC
250mV +-
/IADSLP
IADSLP
ACP
PVCC
FBO
+
V(ACP-ACN)
-
IIN_REG
-
IIN_ER
COMP
ERROR
AMPLIFIER
+
ACN
BTST
CHGEN
+
1V
BAT
VBAT_REG
10mA
LEVEL
SHIFTER
BAT_ER
+
20 mA
CHRG_ON
HIDRV
BAT_SHORT
ACOP
SRP
+
20X
-
IBAT_ REG +
SRN
PH
DC-DC
CONVERTER
PWM LOGIC
V(SRP-SRN)
ICH_ER
PVCC 6V LDO
20 mA
REGN
SYNCH
V(SRP - SRN)
+
SYNCH
ENA_BIAS
ISYNSET
BTST
-
REFRESH
C BTST
LODRV
+
BAT
ACSET
–
4V +
_
BAT_SHORT
PH
+
2.9 V/Cell +-
IC Tj
155°C
+
PGND
TSHUT
–
ACP
SRSET
VBATSET
IBATSET
IINSET
VADJ
–
V(IADAPT)
+
104% X VBAT_REG
–
V(SRP-SRN)
+
145% X IBAT_REG
–
ACDET
+
3.1V +-
2, 3, 4
LPREF
LPMD
IBAT_REG
RATIO
IIN_REG
PROGRAM
VDAC
CELLS
VBAT_REG
BAT
PVCC
+
BAT_OVP
ACN
+
20x
-
V(IADAPT)
CHG_OCP
ACOV
DPMDET
DPM_LOOP_ON
–
–
UVLO
+
AGND
4 V +-
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16
IADAPT
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SLUS736 – DECEMBER 2006
TYPICAL APPLICATIONS
DETAILED DESCRIPTION
BATTERY VOLTAGE REGULATION
The bq24740 uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage setting
VBATT=4.2 V × cell count. The regulation voltage is ratio-metric with respect to VADC. The ratio of VADJ and
VDAC provides extra 12.5% adjust range on VBATT regulation voltage. By limiting the adjust range to 12.5% of
the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overall
voltage accuracy as good as 0.5% is maintained, while using 1% mis-match resistors. Ratio-metric conversion
also allows compatibility with D/As or microcontrollers (µC). The battery voltage is programmed through VADJ
and VDAC using Equation 1.
V BATT + cell count
ƪ ǒ
Ǔƫ
VVADJ
V VDAC
4V ) 0.5
(1)
The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. VBATT defaults
to 4.2 V × cell count when VADJ is connected to REGN.
CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. When
charging other cell chemistries, use CELLS to select an output voltage range for the charger.
CELLS
CELL COUNT
Float
2
AGND
3
VREF
4
The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to
determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high frequency noise.
BATTERY CURRENT REGULATION
The SRSET input sets the maximum charging current. Battery current is sensed by resistor RSR connected
between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010
Ω sense resistor, the maximum charging current is 10 A. SRSET is ratio-metric with respect to VDAC using
Equation 2:
V
I CHARGE + SRSET 0.10
VVDAC
R SR
(2)
The input voltage range of SRSET is between 0 and VDAC, up to 3.6 V.
The SRP and SRN pins are used to sense across RSR with default value of 10 mΩ. However, resistors of other
values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation
accuracy; but, at the expense of higher conduction loss.
INPUT ADAPTER CURRENT REGULATION
The total input from an AC adapter or other DC sources is a function of the system supply current and the
battery charging current. System current normally fluctuates as portions of the systems are powered up or down.
Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current
and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the
charging current when the input current exceeds the input current limit set by ACSET. The current capability of
the AC adapter can be lowered, reducing system cost.
Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set ACSET, which is ratio-metric with respect to VDAC, using Equation 3.
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I ADAPTER +
VACSET
VVDAC
0.10
R AC
(3)
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values
can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation
accuracy; but, at the expense of higher conduction loss.
ADAPTER DETECT AND POWER UP
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage and lower than
the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense
the true adapter input voltage whether the ACFET is on or off. Before adapter is detected, BATFET stays on and
ACFET turns off.
If PVCC is below 5 V, the device is disabled, and both ACFET and BATFET turn off.
If ACDET is below 0.6 V but PVCC is above 5 V, part of the bias is enabled, including a crude bandgap
reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent
current is less than 10µA.
Once ACDET rises above 0.6 V and PVCC is above 5 V, all the bias circuits are enabled and REGN output
goes to 6 V and VREF goes to 3.3 V. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 500ms later, the following occurs:
• ACGOOD becomes high through external pull-up resistor to the host digital voltage rail;
• Charger turns on if all the conditions are satisfied and STAT becomes valid. (refer to Enable and Disable
Charging)
ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charge is enabled:
• CHGEN is LOW;
• Adapter is detected;
• Adapter is higher than PVCC-BAT threshold;
• Adapter is not over voltage;
• 500ms delay is complete after adapter detected;
• REGNGOOD and VREFGOOD are valid;
• Thermal Shut (TSHUT) is not valid;
One of the following conditions will stop on-going charging:
• CHGEN is HIGH;
• Adapter is removed;
• Adapter is less than 250mV above battery;
• Adapter is over voltage;
• Adapter is over current;
• TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis).
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts around 1ms, for a typical rise time of 8 ms. No external components are needed for this function.
18
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CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
fo +
Where resonant frequency, fo, is given by:
• CO = C11 + C12
• LO = L1
1
2p ǸLoC o where (from Figure 1 schematic)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 250 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and
the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.
Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low
again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of
the audible noise region. The charge current sense resistor RSR should be placed with at least half or more of
the total output capacitance placed before the sense resistor contacting both sense resistor and the output
inductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current sense accuracy. The type III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.
Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-side
power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation
low, and allows safely charging at high currents. During synchronous mode the inductor current is always
flowing and operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side n-channel power MOSFET will turn-on for around 80ns, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side
power MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap
capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is
important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a
voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between
high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value.
After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The
inductor current is blocked by the off low-side MOSFET, and the inductor current will become discontinuous.
This mode is called Discontinuous Conduction Mode (DCM).
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SLUS736 – DECEMBER 2006
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage. At very low currents during non-synchronous operation, there may be
a small amount of negative inductor current during the 80 ns recharge pulse. The charge should be low enough
to be absorbed by the input capacitance.
Whenever the converter goes into 0% duty-cycle mode, and BTST – PH < 4 V, the 80-ns recharge pulse occurs
on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 80-ns
recharge pulse), and there is no discharge from the battery.
ISYNSET CONTROL (CHARGE UNDER-CURRENT)
In bq24740, ISYN is internally set as the charge current threshold at which the charger changes from
non-synchronous operation into synchronous operation. The low side driver turns on for only 80 ns to charge the
boost cap. This is important to prevent negative inductor current, which may cause a boost effect in which the
input voltage increases as power is transferred from the battery to the input capacitors. This can lead to an
over-voltage on the PVCC node and potentially cause some damage to the system. This programmable value
allows setting the current threshold for any inductor current ripple, and avoiding negative inductor current. The
minimum synchronous threshold should be set from ½ the inductor current ripple to the full ripple current, where
the inductor current ripple is given by
I RIPPLE_MAX
v I SYN v I RIPPLE_MAX
2
ǒVIN_MAX * VBAT_MINǓ
and
I RIPPLE_MAX +
ǒ
Ǔ ǒǓ
VBAT_MIN
VIN_MAX
1
fs
LMIN
(4)
where
VIN_MAX: maximum adapter voltage
VBAT_MIN: minimum BAT voltage
fS: switching frequency
LMIN: minimum output inductor
The ISYNSET comparator, or charge under-current comparator, compares the voltage between SRP-BAT and
internal threshold on the cycle-to-cycle base. The threshold is set to 13 mV on the falling edge with 8 mV
hysteresis on the rising edge with 10% variation.
HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA)
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the
host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input
sensed voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times
the input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays at
ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT
to AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.
A 200-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, after the 200-pF capacitor, if additional filtering is desired. Note that adding filtering also
adds additional response delay.
INPUT OVER VOLTAGE PROTECTION (ACOV)
ACOV provides
when ACDET >
and the battery
resumes when
threshold.
20
protection to prevent system damage due to high input voltage. The controller enters ACOV
3.1 V. Charge is disabled, the adapter is disconnected from the system by turning off ACDRV,
is connected to the system by turning on BATDRV. ACOV is not latched—normal operation
the ACDET voltage returns below 3.1 V. ACOV threshold is 130% of the adapter-detect
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INPUT UNDER VOLTAGE LOCK OUT (UVLO)
The system must have a minimum 5V PVCC voltage to allow proper operation. This PVCC voltage could come
from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 5 V the bias
circuits REGN and VREF stay inactive, even with ACDET above 0.6 V.
INPUT CURRENT LOW-POWER MODE DETECTION
In order to optimize the system performance, the HOST keeps an eye on the adapter current. Once the adapter
current is above threshold set via LPREF, LPMD pin sends signal to HOST. The signal alarms the host that
input power has exceeded the programmed limit, allowing the host to throttle back system power by reducing
clock frequency, lowering rail voltages, or disabling certain parts of the system. The LPMD pin is an open-drain
output. Connect a pull-up resistor to LPMD. The output is logic HI when the IADAPT output voltage (IADAPT =
20 x VACP-ACN) is lower than the LPREF input voltage. The LPREF threshold is set by an external resistor divider
using VREF. A hysteresis can be programmed by a positive feedback resistor from LPMD pin to the LPREF pin.
ACDET
Comparator
ACDET
2.4 V
+
-
ACDET_DET
t_dg ACDET_DG
rising
700 ms
TO ACDET
Logic
EXT_PWR_DG
ACP
1 kW
+
LOIAC
Comparator
-
ACN
EXTPWR
Adaptor
Current Sense
Amplifier
250 mV
-
LOIAC_DET
+
20 kW
IADAPT Error
Amplifier
Disable
+
IADAPT
IADAPT
Disable
LOPWRMODE
Comparator
+
LPREF
LOPWR_DET
LPMD
Program Hysteresis of comparator
by putting a resistor in feedback
from LPMD pin to LPREF pin.
Figure 28. EXTPWR, LPREF and LPMD Logic
BATTERY OVER-VOLTAGE PROTECTION
The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will
not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This
allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is
disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the
stored output-inductor energy into the output capacitors.
CHARGE OVER-CURRENT PROTECTION
The charger has a secondary over-current protection. It monitors the charge current, and prevents the current
from exceeding 145% of regulated charge current. The high-side gate drive turns off when the over-current is
detected, and automatically resumes when the current falls below the over-current threshold.
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SLUS736 – DECEMBER 2006
THERMAL SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.
Status Outputs (EXTPWR, LPMD, DPMDET pin)
Four status outputs are available, and they all, except for LPMD, require external pull up resistors to pull the pins
to system digital rail for a high level.
EXTPWR open-drain output goes low under either of the two conditions:
1. ACDET is above 2.4 V
2. Adapter current is above 1.25 A using a 10-mΩ sense resistor (IADAPT voltage above 250 mV). Internally,
the AC current detect comparator looks between IADAPT and an internal 250-mV threshold. It indicates a
good adapter is connected because of valid voltage or current.
STAT open-drain output goes low when charging. A high level on STAT indicates the charger is not charging;
therefore, either, CHGEN pin is not low, or the charger is not able to charge because input voltage is still
powering up and the 700-ms delay has not finished, or because of a fault condition such as overcurrent, input
over voltage, or TSHUT over temperature.
LPMD push-pull output goes low when the input current is higher than the programmed threshold via LPREF
pin. Hysteresis can be programmed by putting a resistor from LPREF pin to LPMD pin.
DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current (after a
10-ms delay).
Table 2. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30V,-6A, SO-8, Vishay-Siliconix, Si4435
Q4, Q2
2
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
D1
1
Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C
RAC, RSR
2
Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 10µH, 7A, 31mΩ, Vishay-Dale, IHLP5050FD-01
C1, C6, C7, C11, C12
5
Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M
C4, C8, C10
3
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K
C2, C3, C9, C13, C14, C15
6
Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU
R3, R4, R5
4
Resistor, Chip, 10 kΩ, 1/16W, 5%, 0402
R1
1
Resistor, Chip, 432 kΩ, 1/16W, 1%, 0402
R2
1
Resistor, Chip, 66.5 kΩ, 1/16W, 1%, 0402
R6
1
Resistor, Chip, 33 kΩ, 1/16W, 1%, 0402
R7
1
Resistor, Chip, 200 kΩ, 1/16W, 1%, 0402
R8
1
Resistor, Chip, 24.9 kΩ, 1/16W, 1%, 0402
R9
1
Resistor, Chip, 1.8 MΩ, 1/16W, 1%, 0402
22
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SLUS736 – DECEMBER 2006
APPLICATION INFORMATION
Input Capacitance Calculation
During the adapter hot plug-in, the ACDRV has not been enabled. The AC switch is off and the simplified
equivalent circuit of the input is shown in Figure 29.
Ii
Li
Ri
C1
Vi
A.
C8 Ci Vc
Ri and Li are the equivalent input inductance and resistance. C1 and C8 are the input capacitance.
Figure 29. Simplified Equivalent Circuit During Adapter Insertion
The voltage on the input capacitor(s) is given by:
VC ( t ) = VC (0) +
Z0 =
where
Vi × w
Z 0 × C i × w 20
Li
w=
Ci ,
+
-
Vi
Z 0 × C i × w 02
æR
1
- çç i
L i C i è 2L i
e
Ri
t
2L i æ
ö
R
çç - i sin wt - w × cos wt ÷÷
2
L
i
è
ø
(5)
2
ö
÷÷
w0 =
ø , and
1
L iCi
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SLUS736 – DECEMBER 2006
APPLICATION INFORMATION (continued)
For a typical notebook charger application, the total stray inductance of the adapter output wire and the PCB
connections is normally 5–12 µH, and the total effective resistance of the input connections is 0.15–0.5 Ω.
Figure 30(a) demonstrates that a higher Ci helps to damp the voltage spike. Figure 30(b) demonstrates the
effect of the input stray inductance Li on the input voltage spike. The dashed curve in Figure 30(b) represents
the worst case for Ci=40 µF. Figure 30(c) shows how the resistance helps to suppress the input voltage spike.
35
35
Ci = 20 mF
Ci = 40 mF
Ri = 0.15 W,
Ci = 40 mF
30
Input Capacitor Voltage - V
Input Capacitor Voltage - V
Li = 5 mF
Ri = 0.21 W,
Li = 9.3 mH
30
25
20
15
10
5
Li = 12 mF
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
Time - ms
(a) Vc with various Ci values
4
4.5
0
5
0
0.5
1
1.5
2
2.5
3
Time - ms
3.5
4
4.5
5
(b) Vc with various Li values
35
Li = 9.3 mH,
Ci = 40 mF
Ri = 0.15 W
Input Capacitor Voltage - V
30
Ri = 0.50 W
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
Time - ms
3.5
4
4.5
5
(c) Vc with various Ri values
Figure 30. Parametric Study Of The Input Voltage
Minimizing the input stray inductance, increasing the input capacitance and using high-ESR input capacitors
helps to suppress the input voltage spike.
24
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SLUS736 – DECEMBER 2006
APPLICATION INFORMATION (continued)
Figure 31 shows the measured input voltages and currents with different input capacitances. The voltage spike
drops by about 5 V after increasing Ci from 20 µF to 40 µF. The input voltage spike has been dramatically
damped by using a 47 F electrolytic capacitor.
Ci = 20 mF
Ci = 40 mF
( c ) C i = 4 9 mF ( 4 7 mF e l e c t r o l y t i c a n d 2 x mF ceramic)
Figure 31. Adapter DC Side Hot Plug-In With Various Input Capacitances
Since the input voltage to the IC is PVCC which is 0.7 V (diode voltage drop) lower than Vc during the adapter
insertion, a 40-µF input capacitance is normally adequate to keep the PVCC voltage well below the maximum
voltage rating under normal conditions. In case of a higher input stray inductance, the input capacitance may be
increased accordingly. An electrolytic capacitor will help reduce the input voltage spike due to its high ESR.
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APPLICATION INFORMATION (continued)
PCB Layout Design Guideline
1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the
power ground are connected only at the power pad.
3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The
area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close to
the IC as possible.
4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.
The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close
to the IC as possible.
5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC
(on the bottom layer) with the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins
with the interconnections to the IC as short as possible.
7. Decoupling capacitor CX for the charger input must be placed very close to the Q4 drain and Q5 source.
Figure 32 shows the recommended component placement with trace and via locations.
(a) Top Layer
(b) Bottom Layer
Figure 32. Layout Example
26
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PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
17-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24740RHDR
RHD
28
MLA
330
12
5.3
5.3
1.5
8
12
PKGORN
T2TR-MS
P
BQ24740RHDT
RHD
28
MLA
180
12
5.3
5.3
1.5
8
12
PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
BQ24740RHDR
RHD
28
MLA
346.0
346.0
29.0
BQ24740RHDT
RHD
28
MLA
190.0
212.7
31.75
Pack Materials-Page 2
Height (mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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