ISSI IS61LV25616-12KI 256k x 16 high speed asynchronous cmos static ram with 3.3v supply Datasheet

ISSI
IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
®
AUGUST 2000
DESCRIPTION
The ISSI IS61LV25616 is a high-speed, 4,194,304-bit static
• High-speed access time:
— 7, 8, 10, 12, and 15 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
RAM organized as 262,144 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption
devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
1
ISSI
IS61LV25616
®
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
48-Pin mini BGA
1
2
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
TOP VIEW
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
44-Pin LQFP
PIN DESCRIPTIONS
2
3
4
5
6
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
A1
A2
N/C
WE
Write Enable Input
A3
A4
CE
I/O0
LB
Lower-byte Control (I/O0-I/O7)
I/O10
A5
A6
I/O1
I/O2
UB
Upper-byte Control (I/O8-I/O15)
I/O11
A17
A7
I/O3
Vcc
NC
No Connection
I/O12
NC
A16
I/O4
GND
Vcc
Power
I/O14
I/O13
A14
A15
I/O5
I/O6
GND
Ground
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A
LB
OE
A0
B
I/O8
UB
C
I/O9
D
GND
E
Vcc
F
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
ISSI
IS61LV25616
®
TRUTH TABLE
I/O PIN
I/O0-I/O7
I/O8-I/O15
WE
CE
OE
LB
UB
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
I CC
Read
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
I CC
Write
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
I CC
Mode
1
Vcc Current
2
3
4
5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
–0.5 to Vcc+0.5
V
VTERM
Terminal Voltage with Respect to GND
TBIAS
Temperature Under Bias
–45 to +90
°C
VCC
Vcc Related to GND
–0.3 to +4.0
V
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
6
7
8
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
10
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
7, 8, 10 ns
VCC
12 ns, 15 ns
VCC
0°C to +70°C
3.3V +10%, -5%
3.3V ± 10%
–40°C to +85°C
3.3V +10%, -5%
3.3V ± 10%
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
11
12
3
ISSI
IS61LV25616
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, 4
Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-7, -8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
Com.
IOUT = 0 mA, f = fMAX Ind.
—
—
260
300
—
—
260
300
—
—
240
280
—
—
220
250
mA
ISB
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
85
95
—
—
85
95
—
—
75
85
—
—
65
75
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
—
—
20
25
—
—
20
25
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
CE ≥ VCC – 0.2V,
Ind.
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
—
—
10
15
—
—
10
15
—
—
10
15
—
—
10
15
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
ISSI
IS61LV25616
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2
tLZCE(2)
tBA
tHZB(2)
tLZB(2)
tPU
tPD
Parameter
-7
Min. Max.
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
1
Unit
Read Cycle Time
7
—
8
—
10
—
12
—
15
—
ns
Address Access Time
—
7
—
8
—
10
—
12
—
15
ns
Output Hold Time
3
—
3
—
3
—
3
—
3
—
ns
CE Access Time
—
7
—
8
—
10
—
12
—
15
ns
OE Access Time
—
3.5
—
3.5
—
4
—
5
—
7
ns
OE to High-Z Output
—
2.5
—
3
—
4
—
5
0
6
ns
OE to Low-Z Output
0
—
0
—
0
—
0
—
0
—
ns
CE to High-Z Output
0
3
—
3
0
4
0
6
0
8
ns
CE to Low-Z Output
2.5
—
3
—
3
—
3
—
3
—
ns
LB, UB Access Time
—
3
—
3.5
—
4
—
5
—
7
ns
LB, UB to High-Z Output
0
2.5
0
3
0
3
0
4
0
5
ns
LB, UB to Low-Z Output
0
—
0
—
0
—
0
—
0
—
ns
Power Up Time
0
—
0
—
0
—
0
—
0
—
ns
Power Down Time
—
7
—
8
—
10
—
12
—
15
ns
2
3
4
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Shaded area product in development
6
7
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
8
See Figures 1 and 2
9
AC TEST LOADS
10
319 Ω
ZO = 50Ω
3.3V
50Ω
11
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
5 pF
Including
jig and
scope
353 Ω
12
Figure 2
5
ISSI
IS61LV25616
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CE
tACE
tHZCE
tLZCE
LB, UB
DOUT
VCC
HIGH-Z
tBA
tLZB
tHZB
tRC
DATA VALID
tPU
50%
Supply
Current
tPD
ICC
50%
ISB
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
ISSI
IS61LV25616
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-7
Min. Max.
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
tWC
Write Cycle Time
7
—
8
—
10
—
12
—
15
—
ns
tSCE
CE to Write End
5
—
5.5
—
8
—
8
—
10
—
ns
tAW
Address Setup Time
to Write End
5
—
5.5
—
8
—
8
—
10
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
5
—
5.5
—
8
—
8
—
10
—
ns
tPWE1
WE Pulse Width
5
—
5.5
—
8
—
8
—
10
—
ns
tPWE2
WE Pulse Width (OE = LOW)
7
—
5
—
10
—
12
—
12
—
ns
tSD
Data Setup to Write End
3.5
—
4
—
6
—
6
—
7
—
ns
tHD
1
Unit
Data Hold from Write End
0
—
0
—
0
—
0
—
0
—
ns
(2)
tHZWE
WE LOW to High-Z Output
—
3
—
3.5
—
5
—
6
—
7
ns
(2)
tLZWE
WE HIGH to Low-Z Output
2
—
2
—
2
—
2
—
2
—
ns
2
3
4
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Shaded area product in development
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
7
ISSI
IS61LV25616
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
ISSI
IS61LV25616
®
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
1
t WC
ADDRESS
VALID ADDRESS
2
t HA
OE
CE
3
LOW
t AW
t PWE1
WE
t SA
4
t PBW
UB, LB
t HZWE
DOUT
t LZWE
5
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
6
UB_CEWR2.eps
7
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
OE
8
VALID ADDRESS
t HA
LOW
9
CE
LOW
t AW
10
t PWE2
WE
t SA
t PBW
11
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
12
t HD
DATAIN VALID
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
9
ISSI
IS61LV25616
®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
ISSI
IS61LV25616
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns)
Industrial Range: –40°C to +85°C
Order Part No.
Package
1
IS61LV25616-8TI
IS61LV25616-8KI
IS61LV25616-8LQI
IS61LV25616-8BI
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
2
10
IS61LV25616-10TI
IS61LV25616-10KI
IS61LV25616-10LQI
IS61LV25616-10BI
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
3
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
12
IS61LV25616-12TI
IS61LV25616-12KI
IS61LV25616-12LQI
IS61LV25616-12BI
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
IS61LV25616-12T
IS61LV25616-12K
IS61LV25616-12LQ
IS61LV25616-12B
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
15
IS61LV25616-15TI
IS61LV25616-15KI
IS61LV25616-15LQI
IS61LV25616-15BI
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
IS61LV25616-15T
IS61LV25616-15K
IS61LV25616-15LQ
IS61LV25616-15B
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
Order Part No.
Package
IS61LV25616-7T
IS61LV25616-7K
IS61LV25616-7LQ
IS61LV25616-7B
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
8
8
IS61LV25616-8T
IS61LV25616-8K
IS61LV25616-8LQ
IS61LV25616-8B
TSOP (Type II)
400-mil SOJ
LQFP
Mini BGA (8mm x 10mm)
10
IS61LV25616-10T
IS61LV25616-10K
IS61LV25616-10LQ
IS61LV25616-10B
12
15
7
®
Speed
(ns)
4
5
6
Shaded area product in development
7
Shaded area product in development
8
9
®
10
Integrated Silicon Solution, Inc.
11
ISSI
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
11
12
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