www.ti.com TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE SLVS640 – OCTOBER 2007 FEATURES 1 • • • • • • • • Single-Chip ESD Solution for High-Definition Multmedia Interface (HDMI) 0.9 pF Capacitance for High-Speed Transition Minimized Directional Signaling (TMDS) Lines 0.05-pF Matching Capacitance Between Differential Signal Pair Integrated Level Shifting for Control Lines ±8-kV Contact ESD Protection on External Lines 38-Pin Thin shrink Small-Outline Package (TSSOP) Provides Seamless Layout Option With HDMI Connector Backdrive Protection Lead-Free Package DBT PACKAGE (TOP VIEW) 5V_SUPPLY LV_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 NC ESD_BYP GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT • • • Video Interfaces Consumer Electronics Displays and Digital Televisions DESCRIPTION/ORDERING INFORMATION The TPD12S520 is a single-chip ESD solution for the high-definition multmedia interface (HDMI) receiver port. In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S520 provides the desired system-level ESD protection, such as the the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike. While providing the ESD protection, the TPD12S520 adds little or no additional glitch in the high-speed differential signals (see Figure 3 and Figure 4). The high-speed transition minimized directional signaling (TMDS) lines add only 0.9 pF capacitance to the lines. In addition, the monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The low-speed control lines offer voltage level-shifting to eliminate the need for an external voltage-level shifter IC. The control line ESD clamps add 3.5pF capacitance to the control lines. The 38-pin DBT package offers seamless layout routing option to eliminate the routing glitch for the differential signal pair. DBT package pitch (0.5 mm) matches the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is designed specifically for next-generation HDMI receiver-interface protection. ORDERING INFORMATION STANDARD FINISH TA –40°C to 85°C (1) (2) (3) PACKAGE (1) (2) TSSOP-38 ORDERABLE PART NUMBER (3) TPD12S520DBTR TOP-SIDE MARKING PREVIEW LEAD-FREE FINISH ORDERABLE PART NUMBER (3) TPD12S520DBTR TOP-SIDE MARKING PREVIEW Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Parts are shipped in tape-and-reel form, unless otherwise specified. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2007, Texas Instruments Incorporated PRODUCT PREVIEW APPLICATIONS TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE www.ti.com SLVS640 – OCTOBER 2007 ELECTRICAL SCHEMATIC ESD_BYP 5V_SUPPLY TMDS_D2+ TMDS_D1+ TMDS_D0+ TMDS_CK+ TMDS_GND TMDS_GND TMDS_GND TMDS_GND TMDS_D2– TMDS_D1– TMDS_D0– TMDS_CK– LV Supply CE_REMOTE_IN LV Supply CE_REMOTE_OUT PRODUCT PREVIEW LV Supply DDC_CLK_IN DDC_DAT_OUT DDC_DAT_IN LV Supply HOTPLUG_DET_OUT DDC_CLK_OUT HOTPLUG_DET_IN 38 1 D2+ GND D2– D1+ GND D1– D0+ GND D0– CLK+ GND CLK– CE_R NC D_CK D_DT GND 5OUT HTDT TPD12S520 HDMI Core Chip 19 20 HDMI Connector A. High-speed lines Board Traces GND VIA Connected to 5V Plane Control lines VIA Connected to LV Plane 5 V out VIA Connected to GND Plane External bypass capacitors and resistor components not included Figure 1. Board Layout for HDMI Transmitter Using TPD12S520DBTR 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE www.ti.com SLVS640 – OCTOBER 2007 PIN DESCRIPTION NAME 4, 35 TMDS_D2+ 6, 33 (4) (5) TMDS 0.9-pF ESD protection (2) 8 kV (1) TMDS 0.9-pF ESD protection (2) (1) TMDS 0.9-pF ESD protection (2) 8 kV TMDS_D1+ 8 kV 9, 30 TMDS_D1– 8 kV (1) TMDS 0.9-pF ESD protection (2) TMDS_D0+ 8 kV (1) TMDS 0.9-pF ESD protection (2) (1) TMDS 0.9-pF ESD protection (2) 12, 27 TMDS_D0– 8 kV 13, 26 TMDS_CK+ 8 kV (1) TMDS 0.9-pF ESD protection (2) TMDS_CK– 8 kV (1) TMDS 0.9-pF ESD protection (2) 2 kV (3) LV_SUPPLY referenced logic level into ASIC 15, 24 (2) (3) DESCRIPTION (1) 7, 32 10, 29 (1) TMDS_D2– ESD LEVEL 16 CE_REMOTE_IN 23 CE_REMOTE_OUT 8 kV (1) 2 kV (3) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector 17 DDC_CLK_IN 22 DDC_CLK_OUT 8 kV (1) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector 18 DDC_DAT_IN 2 kV (3) LV_SUPPLY referenced logic level into ASIC 21 DDC_DAT_OUT 8 kV (1) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector 2 kV (3) LV_SUPPLY referenced logic level into ASIC 19 HOTPLUG_DET_IN 20 HOTPLUG_DET_OUT 8 kV (1) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD (4) to connector 2 LV_SUPPLY 2 kV (3) Bias for CE/DDC/HOTPLUG level shifters (3) 2 kV LV_SUPPLY referenced logic level into ASIC 1 5V_SUPPLY 37 ESD_BYP 2 kV (3) Current source for 5V_OUT 5, 34, 8, 31, 11, 28, 14, 25 TMDS_GND NA TMDS ESD and parasitic GND return (5) 3, 36 GND NA Supply GND reference 38 NC NA No connection ESD bypass. This pin must be connected to a 0.1-μF ceramic capacitor. Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V and ESD_BYP (pin 37), and HOTPLUG_DET_OUT (pin 20), each bypassed with a 0.1-μF ceramic capacitor connected to GND. These two pins must be connected together inline on the PCB. Human-Body Model (HBM) per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLYand LV_SUPPLY within recommended operating conditions, GND = 0 V and ESD_BYP (pin 37), and HOTPLUG_DET_OUT (pin 20), each bypassed with a 0.1-μF ceramic capacitor connected to GND. This output can be connected to an external 0.1-μF ceramic capacitor, resulting in an increased ESD withstand voltage rating. These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 3 PRODUCT PREVIEW PIN NO. TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE www.ti.com SLVS640 – OCTOBER 2007 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN VCC5V VCCLV Supply voltage 6 DC voltage at any channel input Tstg MAX Storage temperature range –65 UNIT V 6 V 150 °C Recommended Operating Conditions MIN NOM MAX Operating supply voltage 5V_SUPPLY GND 5 5.5 Bias supply voltage LV_SUPPLY 1 3.3 5.5 V 85 °C Operating temperature range –40 UNIT V PRODUCT PREVIEW 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE www.ti.com SLVS640 – OCTOBER 2007 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS Operating supply current 5V_SUPPLY = 5 V ICCLV Bias supply current LV_SUPPLY = 3.3 V IOFF OFF-state leakage current, level-shifting NFET LV_SUPPLY = 0 V MIN TYP MAX UNIT 110 130 μA 1 5 μA 0.1 5 μA 0.1 5 μA 75 95 140 mV Top diode 0.6 0.85 0.95 Bottom diode 0.6 0.85 0.95 TMDS_[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT IBACKDRIVE Current conducted from output pins to V_SUPPLY rails when powered down 5V_SUPPLY < VCH_OUT VON Voltage drop across level-shifting NFET when ON LV_SUPPLY = 2.5 V, VS = GND, IDS = 3 mA VF Diode forward voltage IF = 8 mA, TA = 25°C (1) VESD ESD withstand voltage Pins 4, 7,10,13, 20–24, 27, 30, 33 (1) (2) IEC ±8 Pins 1, 2, 16–19, 37 (1) (3) HBM ±2 VCL Channel clamp voltage @ 8kV HBM ESD TA = 25°C (1) (3) RDYN Dynamic resistance I = 1 A, TA = 25°C (4) ILEAK TMDS channel leakage current TA = 25°C (1) CIN, TMDS TMDS channel input capacitance ΔCIN, TMDS kV Positive transients 9 Negative transients –9 Positive transients Negative transients V V 3 Ω 1.5 0.01 1 μA 5V_SUPPLY = 5 V, Measured at 1 MHz, VBIAS = 2.5 V (1) 0.9 1.2 pF TMDS channel input capacitance matching 5V_SUPPLY = 5 V, Measured at 1 MHz, VBIAS = 2.5 V (1) (5) 0.05 pF CMUTUAL Mutual capacitance between signal pin and adjacent signal pin 5V_SUPPLY = 0 V, Measured at 1 MHz, VBIAS = 2.5 V (1) 0.07 pF CIN Level-shifting input capacitance, capacitance to GND 5V_SUPPLY = 0 V, Measured at 100 KHz, VBIAS = 2.5 V (1) (1) (2) (3) (4) (5) PRODUCT PREVIEW PARAMETER ICC5V DDC 3.5 4 CEC 3.5 4 HP 3.5 4 pF This parameter is specified by design and verified by device characterization. Standard IEC 61000-4-2, CDISCHARGE= 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V and ESD_BYP (pin 37), and HOTPLUG_DET_OUT (pin 20), each bypassed with a 0.1-μF ceramic capacitor connected to GND. Human-Body Model per MIL-STD-883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V and ESD_BYP (pin 37), and HOTPLUG_DET_OUT (pin 20), each bypassed with a 0.1-μF ceramic capacitor connected to GND. These measurements performed with no external capacitor on ESD_BYP. Intrapair matching, each TMDS pair (i.e. D+, D–) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 5 TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE www.ti.com SLVS640 – OCTOBER 2007 TYPICAL PERFORMANCE Typical Filter Performance (TA = 25°C, DC Bias = 0 V, 50-Ω Environment) –1 –2 Insertion Loss (dB) –3 –4 –5 –6 –7 PRODUCT PREVIEW –8 –9 –10 3 10 100 1000 6000 Frequency (MHz) Figure 2. Insertion Loss vs Frequency (TMDS_D1– to GND) Figure 3. Eye Diagram With TPD12S520 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 www.ti.com TPD12S520 SINGLE-CHIP HDMI RECEIVER PORT PROTECTION AND INTERFACE DEVICE SLVS640 – OCTOBER 2007 PRODUCT PREVIEW TYPICAL PERFORMANCE (continued) Figure 4. Eye Diagram Without TPD12S520 Figure 5. Test Board to Measure Eye Diagram for the TPD12S521 (Refer to Eye Diagram Figures) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPD12S520 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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