IDT IDT74LVCH162244APAG 3.3v cmos 16-bit buffer/driver with 3-state outputs, 5 volt tolerant i/o, and bus-hold Datasheet

IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162244A
3.3V CMOS 16-BIT
BUFFER/DRIVER WITH 3-STATE
OUTPUTS, 5 VOLT TOLERANT I/O,
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
μ W typ. static)
• CMOS power levels (0.4μ
• All inputs, outputs, and I/O are 5V tolerant
• Available in SSOP and TSSOP packages
The LVCH162244A 16-bit buffer/driver is built using advanced dual
metal CMOS technology. The LVCH162244A is designed specifically to
improve both the performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and transmitters. The
device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
This device provides true outputs and symmetrical active-low output-enable
(OE) inputs.
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH162244A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated threshold
levels.
The LVCH162244A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Full internal series termination
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1
1A1
47
2
1A2
46
3
1A3
44
5
1A4
43
6
2OE
48
2A1
41
8
2A2
40
9
2A3
38
11
2A4
37
12
3OE
25
1Y1
3A1
36
13
3Y1
1Y2
3A2
35
14
3Y2
1Y3
3A3
33
16
1Y4
3A4
32
17
3Y4
4OE
24
2Y1
4A1
30
19
4Y1
2Y2
4A2
29
20
4Y2
2Y3
4A3
27
22
2Y4
4A4
26
23
3Y3
4Y3
4Y4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4727/4
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
1OE
1
48
2OE
1Y1
2
47
1A1
46
1A2
Continuous Clamp Current,
VI < 0 or VO < 0
mA
3
IIK
IOK
–50
1Y2
GND
4
45
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
GND
1Y3
5
44
1A3
1Y4
6
43
1A4
VCC
7
42
VCC
2Y1
8
41
2A1
2Y2
9
40
GND
10
39
GND
2Y3
11
38
2A3
Symbol
Conditions
Typ.
Max.
2Y4
12
37
2A4
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2A2
3Y1
13
36
3A1
3Y2
14
35
3A2
GND
15
34
3Y3
16
33
GND
3A3
3Y4
17
32
3A4
VCC
18
31
VCC
4Y1
19
30
4A1
4Y2
20
29
4A2
GND
21
28
GND
4Y3
22
27
4A3
4Y4
23
26
4A4
4OE
24
25
3OE
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Unit
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
xOE
3-State Output Enable Inputs (Active LOW)
xAx
Data Inputs(1)
xYx
3-State Outputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH 4-BIT BUFFER)(1)
Inputs
SSOP/ TSSOP
TOP VIEW
xOE
xAx
xYx
L
L
L
L
H
H
H
X
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
Outputs
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
ΔICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
µA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Bus-Hold Input Sustain Current
VCC = 3V
Bus-Hold Input Sustain Current
VCC = 2.3V
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 2V
IBHL
IBHH
IBHL
IBHHO
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
±500
µA
µA
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
IOH = – 4mA
1.9
—
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
1.7
—
VCC = 2.7V
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
VCC = 3V
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
VCC = 2.7V
VCC = 3V
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Buffer/Driver Outputs enabled
CPD
Power Dissipation Capacitance per Buffer/Driver Outputs disabled
Test Conditions
Typical
Unit
CL = 0pF, f = 10Mhz
35
pF
4
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
VCC = 3.3V ± 0.3V
Parameter
Min.
Max.
Min.
Max.
Unit
tPLH
Propagation Delay
—
5.6
1.1
4.4
ns
—
6.9
1
5.5
ns
—
6.8
1.8
6.3
ns
—
—
—
500
ps
tPHL
xAx to xYx
tPZH
Output Enable Time
tPZL
xOE to xYx
tPHZ
Output Disable Time
tPLZ
xOE to xYx
tSK(o)
Output Skew(2)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
VCC(2)= 2.5V±0.2V
Unit
2 x Vcc
V
6
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
LVC Link
Propagation Delay
500Ω
Pulse (1, 2)
Generator
tPZL
GND
VOUT
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY
OPEN
HIGH
D.U.T.
500Ω
RT
CL
Test Circuit for All Outputs
VIH
VT
0V
CONTROL
INPUT
Open
VIN
DISABLE
ENABLE
VLOAD
VCC
tPLZ
VLOAD/2
VT
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
LVC Link
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Switch
Open Drain
Disable Low
Enable Low
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
OUTPUT 1
tSK (x)
tSK (x)
tPLH2
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
VT
tW
HIGH-LOW-HIGH
PULSE
VT
LVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tSU
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
OUTPUT 2
tREM
LVC Link
VIH
VT
0V
tPHL1
tPLH1
tH
TIMING
INPUT
Test
INPUT
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
LVC
X
XX
Bus-Hold
Temp. Range
XX
Family
XX
XXXX
Device Type Package
PV
PA
PAG
Shrink Small Outline Package
Thin Shrink Small Outline Package
TSSOP - Green
244A 16-Bit Buffer/Driver with 3-State Outputs
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162
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H
Bus-hold
74
-40°C to +85°C
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6
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