NSC ADC08060CIMT 8-bit, 20 msps to 60 msps, 1.3 mw/msps a/d converter with internal sample-and-hold Datasheet

ADC08060
8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
with Internal Sample-and-Hold
General Description
Features
The ADC08060 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this
product operates at conversion rates of 20 MSPS to 70 MSPS
with outstanding dynamic performance over its full operating
range while consuming just 1.3 mW per MHz of clock frequency. That's just 78 mW of power at 60 MSPS. Raising the
PD pin puts the ADC08060 into a Power Down mode where
it consumes just 1 mW.
The unique architecture achieves 7.5 Effective Bits with
25 MHz input frequency. The excellent DC and AC characteristics of this device, together with its low power consumption and single +3V supply operation, make it ideally suited
for many imaging and communications applications, including
use in portable equipment. Furthermore, the ADC08060 is
resistant to latch-up and the outputs are short-circuit proof.
The top and bottom of the ADC08060's reference ladder are
available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with
a separate output power supply pin to support interfacing with
3V or 2.5V logic. The output coding is straight binary and the
digital inputs (CLK and PD) are TTL/CMOS compatible.
The ADC08060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40°C to +85°C. An evaluation board is available to
assist in the easy evaluation of the ADC08060.
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Single-ended input
Internal sample-and-hold function
Low voltage (single +3V) operation
Small package
Power-down feature
Key Specifications
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Resolution
8 bits
Maximum sampling frequency
60 MSPS (min)
DNL
0.4 LSB (typ)
ENOB
7.5 bits (typ) at fIN = 25 MHz
THD
−60 dB (typ)
No missing codes
Guaranteed
Power Consumption
1.3 mW/MSPS (typ)
— Operating
1 mW (typ)
— Power Down Mode
Applications
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Digital imaging systems
Communication systems
Portable instrumentation
Viterbi decoders
Set-top boxes
Pin Configuration
20006201
© 2008 National Semiconductor Corporation
200062
www.national.com
ADC08060 8-Bit, 60 MSPS, 1.3 mW/MSPS A/D Converter with Internal Sample-and-Hold
January 7, 2008
ADC08060
Ordering Information
Order Number
Temperature Range
Package
ADC08060CIMT
−40°C ≤ TA ≤ +85°C
TSSOP
ADC08060CIMTX
−40°C ≤ TA ≤ +85°C
TSSOP (tape and reel)
ADC08060EVAL
Evaluation Board
Block Diagram
20006202
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
6
VIN
Analog signal input. Conversion range is VRB to VRT.
3
VRT
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
VRB inputs define the VIN conversion range. Bypass well. See
Section 2.0 for more information.
9
VRM
Mid-point of the reference ladder. This pin should be
bypassed to a clean, quiet point in the analog ground plane
with a 0.1 µF capacitor.
VRB
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See Section 2.0 for more information.
10
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Equivalent Circuit
Description
2
Symbol
23
PD
Power Down input. When this pin is high, the converter is in
the Power Down mode and the data output pins hold the last
conversion result.
24
CLK
CMOS/TTL compatible digital clock Input. VIN is sampled on
the falling edge of CLK input.
13 thru 16
and
19 thru 22
D0–D7
Conversion data digital Output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the CLK
input.
7
VIN GND
1, 4, 12
VA
18
DR VD
17
DR GND
2, 5, 8, 11
AGND
Equivalent Circuit
Description
Reference ground for the single-ended analog input, VIN.
Positive analog supply pin. Connect to a clean, quiet voltage
source of +3V. VA should be bypassed with a 0.1 µF ceramic
chip capacitor for each pin, plus one 10 µF capacitor. See
Section 3.0 for more information.
Power supply for the output drivers. If connected to VA,
decouple well from VA.
The ground return for the output driver supply.
The ground return for the analog supply.
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ADC08060
Pin No.
ADC08060
Soldering Temperature, Infrared,
10 seconds (Note 6)
Storage Temperature
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA)
Driver Supply Voltage (DR VD)
Voltage on Any Input or Output Pin
Reference Voltage (VRT, VRB)
CLK, OE Voltage Range
Digital Output Voltage (VOH, VOL)
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at TA = 25°C
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Operating Ratings
3.8V
VA + 0.3V
−0.3V to VA
VA to AGND
−0.3V to
(VA + 0.3V)
DR GND to DR VD
±25 mA
±50 mA
See (Note 4)
235°C
−65°C to +150°C
(Notes 1, 2)
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
Supply Voltage (VA)
Driver Supply Voltage (DR VD)
Ground Difference |GND - DR GND|
Upper Reference Voltage (VRT)
Lower Reference Voltage (VRB)
VIN Voltage Range
+2.7V to +3.6V
+2.4V to VA
0V to 300 mV
1.0V to (VA + 0.1V)
0V to (VRT − 1.0V)
VRB to VRT
2500V
250V
Converter Electrical Characteristics
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
DC ACCURACY
INL
Integral Non-Linearity
±0.5
±1.3
LSB (max)
DNL
Differential Non-Linearity
±0.4
+1.0
−0.9
LSB (max)
LSB (min)
0
(max)
FSE
Missing Codes
Full Scale Error
18
±28
mV (max)
ZSE
Zero Scale Offset Error
26
±35
mV (max)
VRB
V (min)
VRT
V (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
VIN
Input Voltage
1.6
3
pF
(CLK HIGH)
4
pF
CIN
VIN Input Capacitance
RIN
RIN Input Resistance
>1
MΩ
BW
Full Power Bandwidth
200
MHz
VRT
Top Reference Voltage
1.9
VRB
VIN = 0.75V +0.5 Vrms
(CLK LOW)
Bottom Reference Voltage
0.3
VRT - VRB Reference Delta
RREF
IREF
Reference Ladder Resistance
1.6
VRT to VRB
220
Reference Ladder Current
7.3
VA
V (max)
1.0
V (min)
VRT − 1.0
V (max)
0
V (min)
1.0
V (min)
2.3
V (max)
150
Ω (min)
300
Ω (max)
5.3
mA (min)
10.6
mA (max)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH
Logical High Input Voltage
DR VD = VA = 3.3V
2.0
V (min)
VIL
Logical Low Input Voltage
DR VD = VA = 2.7V
0.8
V (max)
IIH
Logical High Input Current
VIH = DR VD = VA = 3.3V
10
nA
IIL
Logical Low Input Current
VIL = 0V, DR VD = VA = 2.7V
−50
nA
CIN
Logic Input Capacitance
3
pF
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4
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
DIGITAL OUTPUT CHARACTERISTICS
VOH
High Level Output Voltage
VA = DR VD = 2.7V, IOH = −400 µA
2.6
2.4
V (min)
VOL
Low Level Output Voltage
VA = DR VD = 2.7V, IOL = 1.0 mA
0.4
0.5
V (max)
fIN = 4.4 MHz, VIN = FS − 0.25 dB
7.6
fIN = 10 MHz, VIN = FS − 0.25 dB
7.6
fIN = 25 MHz, VIN = FS − 0.25 dB
7.5
Bits
fIN = 29 MHz, VIN = FS − 0.25 dB
7.4
Bits
fIN = 4.4 MHz, VIN = FS − 0.25 dB
47
dB
fIN = 10 MHz, VIN = FS − 0.25 dB
47
fIN = 25 MHz, VIN = FS − 0.25 dB
47
dB
fIN = 29 MHz, VIN = FS − 0.25 dB
46
dB
fIN = 4.4 MHz, VIN = FS − 0.25 dB
47
dB
fIN = 10 MHz, VIN = FS − 0.25 dB
47
fIN = 25 MHz, VIN = FS − 0.25 dB
47
fIN = 29 MHz, VIN = FS − 0.25 dB
46
dB
fIN = 4.4 MHz, VIN = FS − 0.25 dB
64
dBc
fIN = 10 MHz, VIN = FS − 0.25 dB
63
dBc
fIN = 25 MHz, VIN = FS − 0.25 dB
60
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
54
dBc
fIN = 4.4 MHz, VIN = FS − 0.25 dB
−64
dBc
fIN = 10 MHz, VIN = FS − 0.25 dB
−63
dBc
fIN = 25 MHz, VIN = FS − 0.25 dB
-57
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−54
dBc
fIN = 4.4 MHz, VIN = FS − 0.25 dB
-70
dBc
fIN = 10 MHz, VIN = FS − 0.25 dB
−65
dBc
fIN = 25 MHz, VIN = FS − 0.25 dB
-64
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−54
dBc
fIN = 4.4 MHz, VIN = FS − 0.25 dB
−72
dBc
fIN = 10 MHz, VIN = FS − 0.25 dB
−70
dBc
fIN = 25 MHz, VIN = FS − 0.25 dB
-68
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−65
dBc
f1 = 11 MHz, VIN = FS − 6.25 dB
f2 = 12 MHz, VIN = FS − 6.25 dB
-55
dBc
DC Input
25
fIN = 10 MHz, VIN = FS − 3 dB
25
DC Input
0.3
DYNAMIC PERFORMANCE
ENOB
SINAD
SNR
SFDR
THD
HD2
HD3
IMD
Effective Number of Bits
Signal-to-Noise & Distortion
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Total Harmonic Distortion
2nd Harmonic Distortion
3rd Harmonic Distortion
Intermodulation Distortion
Bits
7.1
44.5
44.6
Bits (min)
dB (min)
dB (min)
dB
POWER SUPPLY CHARACTERISTICS
IA
DR ID
Analog Supply Current
Output Driver Supply Current
IA + DRID Total Operating Current
PC
Power Consumption
31
mA (max)
1
mA (max)
32
mA (max)
mA
fIN = 10 MHz, VIN = FS − 3 dB
4.4
DC Input
25.3
fIN = 10 MHz, VIN = FS − 3 dB,
PD = Low
29.4
CLK Low, PD = Hi
0.2
DC Input
76
fIN = 10 MHz, VIN = FS − 3 dB,
PD = Low
88
mW
CLK Low, PD = Hi
0.6
mW
5
mA
mA (max)
96
mW (max)
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ADC08060
Symbol
ADC08060
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
PSRR1
Power Supply Rejection Ratio
FSE change with 2.7V to 3.3V change in
VA
54
dB
PSRR2
Power Supply Rejection Ratio
SNR change with 200 mV at 200 kHz on
supply
45
dB
AC ELECTRICAL CHARACTERISTICS
fC1
Maximum Conversion Rate
70
fC2
Minimum Conversion Rate
20
tCL
Minimum Clock Low Time
tCH
Minimum Clock High Time
tOH
Output Hold Time
CLK Rise to Data Invalid
4.4
tOD
Output Delay
CLK Rise to Data Valid
8.2
Pipeline Delay (Latency)
tAD
Sampling (Aperture) Delay
tAJ
Aperture Jitter
2.5
CLK Fall to Acquisition of Data
60
MHz (min)
6.7
ns (min)
6.7
ns (min)
MHz
ns
ns (max)
12
Clock Cycles
1.5
ns
2
ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. In the 24pin TSSOP, θJA is 92°C/W, so PDMAX = 1,358 mW at 25°C and 435 mW at the maximum operating ambient temperature of 85°C. Note that the power consumption
of this device under normal operation will typically be about 180 mW (88 mW quiescent power +12 mW reference ladder power). The values for maximum power
dissipation listed above will be reached only when the ADC08060 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale
input voltage must be ≤2.6VDC to ensure accurate conversions.
20006207
Note 8: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
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6
VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise
INL
INL vs. Temperature
20006208
20006214
INL vs. Supply Voltage
INL vs. Sample Rate
20006210
20006215
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ADC08060
Typical Performance Characteristics
stated
ADC08060
DNL
DNL vs. Temperature
20006209
20006217
DNL vs. Supply Voltage
DNL vs. Sample Rate
20006211
20006218
SNR vs. Temperature
SNR vs. Supply Voltage
20006220
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20006221
8
ADC08060
SNR vs. Sample Rate
SNR vs. Input Frequency
20006212
20006223
SNR vs. Clock Duty Cycle
Distortion vs. Temperature
20006224
20006225
Distortion vs. Supply Voltage
Distortion vs. Sample Rate
20006226
20006213
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ADC08060
Distortion vs. Input Frequency
Distortion vs. Clock Duty Cycle
20006228
20006229
SINAD/ENOB vs. Temperature
SINAD/ENOB vs. Supply Voltage
20006238
20006230
SINAD/ENOB vs. Sample Rate
SINAD/ENOB vs. Clock Duty Cycle
20006216
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20006240
10
ADC08060
SINAD/ENOB vs. Input Frequency
Power Consumption vs. Sample Rate
20006239
20006219
Spectral Response @ fIN = 10.1 MHz
Spectral Response @ fIN = 25 MHz
20006244
20006245
Intermodulation Distortion (IMD)
20006242
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ADC08060
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes low.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as noise at the
output.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FULL-POWER BANDWIDTH is the frequency at which the
reconstructed output fundamental drops 3 dB below its low
frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1½ LSB below VRT and is defined
as:
where SNR0 is the SNR measured with no noise or signal on
the supply lines and SNR1 is the SNR measured with a 200
kHz, 200 mVP-P signal riding upon the supply lines.
OUTPUT DELAY is the time delay after the rising edge of the
input clock before the data changes at the output pins.
OUTPUT HOLD TIME is the length of time that the output data
is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal frequency at the output
to the rms value of the sum of all other spectral components
below one-half the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal frequency at the output to the rms value of all of
the other spectral components below half the clock frequency,
including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal frequency at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundamental at the output. THD
is calculated as
Vmax + 1.5 LSB – VRT
where Vmax is the voltage at which the transition to the maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero
scale (½ LSB below the first code transition) through positive
full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from
the center of that code value. The end point test method is
used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of the interaction
between two sinusoidal frequencies that are applied to the
ADC input at the same time. IMD is the ratio of the power in
the second and third order intermodulation products to the
total power in the original frequencies.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes cannot be reached with any input value.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. For the ADC08060, PSRR1 is the ratio of the change
in d.c. power supply voltage to the resulting change in FullScale Error, expressed in dB. PSRR2 is a measure of how
well an a.c. signal riding upon the power supply is rejected
and is here defined as:
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where f1 is the RMS power of the fundamental (input) frequency and f2 through f10 is the power in the first 9 harmonics
in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is defined as
VOFF = VZT − VRB
where VZT is the first code transition input voltage.
12
ADC08060
Timing Diagram
20006231
FIGURE 1. ADC08060 Timing Diagram
The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the power
down mode, where the output pins hold the last conversion
before the PD pin went high and the device consumes just 1
mW.
Functional Description
The ADC08060 uses a new, unique architecture that
achieves over 7.4 effective bits at input frequencies up to
30 MHz.
The analog input signal that is within the voltage range set by
VRT and VRB is digitized to eight bits. Output format is straight
binary. Input voltages below VRB will cause the output word
to consist of all zeroes. Input voltages above VRB will cause
the output word to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08060
exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the clock
rate that is used. This and its excellent performance over a
wide range of clock frequencies makes it an ideal choice as
a single ADC for many 8-bit needs.
Data is acquired at the falling edge of the clock and the digital
equivalent of that data is available at the digital outputs 2.5
clock cycles plus tOD later. The ADC08060 will convert as long
as the clock signal is present. The output coding is straight
binary.
Applications Information
1.0 REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External voltages
applied to the reference input pins should be within the range
specified in the Operating Ratings table (1.0V to (VA + 0.1V)
for VRT and 0V to (VRT − 1.0V) for VRB). Any device used to
drive the reference pins should be able to source sufficient
current into the VRT pin and sink sufficient current from the
VRB pin.
13
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ADC08060
20006232
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the
reference voltage can vary too much for some applications.
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Superior performance can generally be achieved by driving
the reference pins with a low impedance source.
The circuit of Figure 3 will allow a more accurate setting of the
reference voltages. The upper amplifier must be able to
source the reference current as determined by the value of
the reference resistor and the value of (VRT - VRB). The lower
amplifier must be able to sink this reference current. Both
should be stable with a capacitive load. The LM8272 was
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chosen because of its rail-to-rail input and output capability,
its high current output and its ability to drive large capacitance
loads. Of course, the divider resistors at the amplifier input
could be changed to suit your reference voltage needs, or the
divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder (VRB) may simply be
returned to ground if the minimum input signal excursion is
0V. Be sure that the driving sources can source sufficient current into the VRT pin and sink enough current from the VRB pin
to keep these pins stable.
14
ADC08060
20006233
FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.
VRT should always be more positive than VRB at least by the
minimum VRT - VRB difference in the Electrical Characteristics
table to minimize noise. Furthermore, the difference between
VRT and VRB should not exceed the maxumum value specified
in the Electrical Characteristics table to avoid signal distortion.
VRM (pin 9) is the center of the reference ladder and should
be bypassed to a clean, quiet point in the analog ground plane
with a 0.1 µF capacitor. DO NOT allow this pin to float.
the clock is high. The sampling nature of the analog input
causes current spikes that result in voltage spikes at the analog input pin. Any circuit used to drive the analog input must
be able to drive that input and to settle within the clock high
time. The LMH6702 has been found to be a good amplifier to
drive the ADC08060.
Figure 4 shows an example of an input circuit using the
LMH6702. Any input amplifier should incorporate some gain
as operational amplifiers exhibit better phase margin and
transient response with gains above 2 or 3 than with unity
gain. If an overall gain of less than 3 is required, attenuate the
input and operate the amplifier at a higher gain, as shown in
Figure 4.
2.0 THE ANALOG INPUT
The analog input of the ADC08060 is a switch followed by an
integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when
15
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ADC08060
20006234
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).
The RC at the amplifier output filters the clock rate energy that
comes out of the analog input due to the input sampling circuit.
The optimum time constant for this circuit depends not only
upon the amplifier and ADC, but also on the circuit layout and
board material. A resistor value should be chosen between
18Ω and 47Ω and the capacitor value chose according to the
formula
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a
0.1 µF ceramic chip capacitor placed within one centimeter of
the converter's power supply pins. Leadless chip capacitors
are preferred because they have low lead inductance.
While a single voltage source is recommended for the VA and
DR VD supplies of the ADC08060, these supply pins should
be well isolated from each other to prevent any digital noise
from being coupled into the analog portions of the ADC. A
choke or 27Ω resistor is recommended between these supply
lines with adequate bypass capacitors close to the supply
pins.
As is the case with all high speed converters, the ADC08060
should be assumed to have little power supply rejection. None
of the supplies for the converter should be the supply that is
used for other digital circuitry in any system with a lot of digital
power being consumed. The ADC supplies should be the
same supply used for other analog circuitry.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 300 mV, not
even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the
ADC08060 power pins.
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values
are both zero. To optimize SINAD, reduce the capacitor or
resistor value until SINAD performance is optimized. That is,
until SNR = −THD. This value will usually be in the range of
40% to 65% of the value calculated with the above formula.
An accurate calculation is not possible because of the board
material and layout dependence.
The above is intended for oversampling or Nyquist applications. There should be no resistor or capacitor between the
ADC input and any amplifier for undersampling applications.
The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may cause signal clipping unless care is exercised in the
worst case analysis of component tolerances and the input
signal excursion is appropriately limited to account for the
worst case conditions. Of course, this means that the designer will not be able to depend upon getting a full scale output
with maximum signal input.
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16
ADC08060
4.0 THE DIGITAL INPUT PINS
The ADC08060 has two digital input pins: The PD pin and the
Clock pin.
where L is the length of the clock line in inches.
4.1 The PD Pin
The Power Down (PD) pin, when high, puts the ADC08060
into a low power mode where power consumption is reduced
to 1 mW. Output data is valid and accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog and
digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
The DR GND connection to the ground plane should not use
the same feedthrough used by other ground connections.
High power digital components should not be located on or
near a straight line between the ADC (or any linear component) and the power supply area as the resulting common
return current path could cause fluctuation in the analog
“ground” return of the ADC.
Generally, analog and digital lines should cross each other at
90° to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL
other lines, analog AND digital. Even the generally accepted
90° crossing should be avoided as even a little coupling can
cause problems at high frequencies. Best performance at
high frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the analog ground plane.
4.2 The ADC08060 Clock
Although the ADC08060 is tested and its performance is
guaranteed with a 60 MHz clock, it typically will function well
with clock frequencies from 20 MHz to 70 MHz.
Halting the clock will provide nearly as much power saving as
raising the PD pin high. Typical power consumption with a
stopped clock is 3 mW, compared to 1 mW when PD is high.
The digital outputs will remain in the same state as they were
before the clock was halted.
Once the clock is restored (or the PD pin is brought low), there
is a time of about 1 µs before the output data is valid. However, because of the linear relationship between total power
consumption and clock frequency, the part requires about 1
µs after the clock is restarted or substantially changed in frequency before the part returns to its specified accuracy.
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC08060 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle
and 60 Msps, ADC08060 performance is typically maintained
with clock high and low times of 3.3 ns, corresponding to a
clock duty cycle range of 40% to 50% with a 60 MHz clock.
Note that the clock minimum high and low times may not be
used simultaneously.
The CLOCK line should be series terminated at the clock
source in the characteristic impedance of that line. If the clock
line is longer than
where tr is the clock rise time and tPD is the propagation rate
of the signal along the trace.
If the clock source is used to drive more than just the
ADD08060, the CLOCK pin should be a.c. terminated with a
series RC to ground such that the resistor value is equal to
the characteristic impedance of the clock line and the capacitor value is
where tPD is the signal propagation rate down the clock line,
"L" is the line length and ZO is the characteristic impedance
of the clock line. This termination should be located as close
as possible to, but within one centimeter of, the ADC08060
clock pin. Further, the termination should be beyond the
ADC08060 clock pin as seen from the clock source. Typical
tPD is about 150 ps/inch on FR-4 board material. For FR-4
board material, the value of C becomes
20006236
FIGURE 5. Layout Example
Figure 5 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.
17
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ADC08060
Care should be taken not to overdrive the inputs of the
ADC08060. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is required from DR VD and DR GND. These large charging current spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74F541, for example) may be necessary if the data bus capacitance exceeds 10 pF. Dynamic performance can also be
improved by adding 100Ω series resistors at each digital output, reducing the energy coupled back into the converter input
pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the input
alternates between 3 pF and 4 pF with the clock. This dynamic
capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving
device. The LMH6702 has been found to be a good device
for driving the ADC08060.
Driving the VRT pin or the VRB pin with devices that can
not source or sink the current required by the ladder.
As mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the
VRT pin and sink sufficient current from the VRB pin. If these
pins are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a
reduction in SNR performance. The use of simple gates with
RC timing is generally inadequate as a clock source.
6.0 DYNAMIC PERFORMANCE
The ADC08060 is a.c. tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 10 ps
(rms) of jitter. For best a.c. performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 6.
It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal. The clock
signal can also introduce noise into the analog path.
20006237
FIGURE 6. Isolating the ADC Clock from Digital Circuitry
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below
ground. A 51Ω resistor in series with the offending digital input
will usually eliminate the problem.
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18
ADC08060
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.
24-Lead Package TC
Order Number ADC08060CIMT
NS Package Number MTC24
19
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ADC08060 8-Bit, 60 MSPS, 1.3 mW/MSPS A/D Converter with Internal Sample-and-Hold
Notes
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