Intersil ICL7112LCDL 12-bit, high-speed, cmos up-compatible a/d converter Datasheet

®
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January 1998
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ICL7112
12-Bit, High-Speed,
CMOS µP-Compatible A/D Converter
Features
Description
• 12-Bit Resolution and Accuracy
The ICL7112 is a monolithic 12-bit resolution, fast
successive approximation A/D converter. It uses thin film
resistors and CMOS circuitry combined with an on-chip
PROM calibration table to achieve 12-bit linearity without
laser trimming. Special design techniques used in the DAC
and comparator result in high speed operation, while the
fully static silicon-gate CMOS circuitry keeps the power
dissipation very low.
• No Missing Codes
• Microprocessor Compatible Byte-Organized Buffered
Outputs
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Errors
• Low Power Consumption (60mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Usable Overrange
• Fast Conversion (40µs)
Microprocessor bus interfacing is eased by the use of
standard memory WRite and ReaD cycle timing and control
signals, combined with Chip Select and Address pins. The
digital output pins are byte-organized and three-state gated
for bus interface to 8-bit and 16-bit systems.
The lCL7112 provides separate Analog and Digital grounds
for increased system accuracy. Operating with ±5V supplies,
the lCL7112 accepts 0V to +10V input with a -10V reference
or 0V to -10V input with a +10V reference.
Ordering Information
PART NO.
TEMP. RANGE (oC)
PACKAGE
RESOLUTION WITH NO MISSION
CODES
ICL7112JCDL
0 to 70
40 Ld CERDIP
11-Bit
ICL7112KCDL
0 to 70
40 Ld CERDIP
12-Bit
ICL7112LCDL
0 to 70
40 Ld CERDIP
12-Bit (Note)±
ICL7112JIDL
-25 to 85
40 Ld CERDIP
11-Bit
ICL7112KIDL
-25 to 85
40 Ld CERDIP
12-Bit
ICL7112LIDL
-25 to 85
40 Ld CERDIP
12-Bit (Note)±
ICL7112JMDL
-55 to 125
40 Ld CERDIP
11-Bit
ICL7112KMDL
-55 to 125
40 Ld CERDIP
12-Bit
ICL7112LMDL
-55 to 125
40 Ld CERDIP
12-Bit (Note)±
NOTE: Over operating temperature range.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
6-1
File Number
3639.1
ICL7112
Pinout
ICL7112
TOP VIEW
NC
1
40 NC
AGNDf
2
39 AGNDs
CS
3
38 VREF
RD
4
37 VIN
A0
5
36 COMP
BUS
6
35 V -
DGND
7
34 CAZ
(MSB) D 11
8
33 WR
D10
9
32 TEST
D9
10
D8
11
30 OSC1
D7
12
29 TEST
D6
13
28 PROG
D5
14
27 V +
D4
15
26 OVR
D3
16
25 EOC
D2
17
24 NC
D1
18
23 NC
(LSB) D0
19
22 NC
NC
20
21 NC
ICL7112
31 OSC2
Functional Block Diagram
VREF
OSC1
VIN
RIN
AGND
DAC
R-1.85R
COMP
CAZ
+
-
SAR
CONTROL LOGIC
Y+
DGND
V-
PROM
OSC2
LATCH
WR
EOC
LATCH
THREE-STATE
OUTPUTS
ADDER
ACCCUM
RD
6-2
CS A0
BUS
OVR
D11 (MSB)
D0 (LSB)
ICL7112
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage (V + to DGND) . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Supply Voltage (V - to DGND). . . . . . . . . . . . . . . . . . . +0.3V to -6.5V
VREF , VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to -1V
VREF , VIN , AGND Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Digital I/O Pin Voltages. . . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V
PROG to DGND Voltage . . . . . . . . . . . . . . . . . . . . V - to (V+ +0.3V)
Thermal Resistance (Typical, Note 1)
θJA ( oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
___
___
Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . . 500mW
Derate above 70oC at 10mW/oC
Maximum Junction Temperature (Ceramic Package) . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
Operating Conditions
ICL7112XCXX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70
ICL7112XIXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 to 70
ICL7112XMXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages with respect to DGND, unless otherwise noted.
3. Assumes all leads soldered or welded to printed circuit board.
Electrical Specifications
PARAMETER
Test Conditions: V+ = +5V, V- = -5V, VREF = -10V, TA = 25oC, fCLK = 500kHz, Unless Otherwise Noted
J
TEST
CONDITIONS
SYMBOL
K
MIN
TYP
MAX
11
10
-
-
L
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
12
11
-
-
12
12
-
-
-
±0.024
±0.030
-
-
±0.012
±0.020
-
-
±0.012 %FSR
±0.020
ACCURACY
Resolution
RES
12
Resolution with No RES
Missing Codes
(NMC)
Notes 4, 5, 6
Integral Linearity
Error
ILE
Notes 4, 5
Unadjusted Full
Scale Error
FSE
Adjustable to
Zero
RM
TMIN -TMAX
RM
TMIN -TMAX
ZE
Bits
C
RM
TMIN TMAX
-
-
±0.10
±0.12
-
-
±0.08
±0.10
-
-
±0.08
±0.10
I
RM
TMIN -TMAX
-
-
±0.10
±0.13
-
-
±0.08
±0.11
-
-
±0.08
±0.11
M
RM
-
-
±0.10
±0.14
-
-
±0.08
±0.12
-
-
±0.08
±0.12
-
-
±1
±1.5
-
-
±1
±1.5
-
-
±1
±1.5
0
-
10.3
0
-
10.3
0
-
10.3
V
4
-
9
4
-
9
4
-
9
kΩ
-
-300
-
-
-300
-
-
-300
-
ppm/oC
TMIN -TMAX
Zero Error
Bits
Notes 4, 5
RM
TMIN -TMAX
%FSR
ANALOG INPUT
Analog Input
Range
VIN
Input Resistance
RIN
Temperature
Coefficient of RIN
TC (R IN)
Notes 5, 8
TMIN -TMAX
REFERENCE INPUT
Analog Reference
V REF
-
-10.0
-
-
-10.0
-
-
-10.0
-
V
Reference
Resistance
RREF
-
5
-
-
5
-
-
5
-
kΩ
RM
V +, V - = 4.5 -5.5V
TMIN -TMAX
-
±0.5
±1
±2
-
±0.5
±1
±2
-
±0.5
±1
±2
LSB
TMIN -TMAX
-
-
0.8
-
-
0.8
-
-
0.8
V
POWER SUPPLY SENSITIVITY
Power Supply
Rejection Ration
PSRR
LOGIC INPUT
Low State
Input Voltage
VIL
6-3
ICL7112
Electrical Specifications
PARAMETER
SYMBOL
High State
Input Voltage
VIH
Logic Input
Current
ILIH
Logic Input
Capacitance
CIN
Test Conditions: V+ = +5V, V- = -5V, VREF = -10V, TA = 25oC, fCLK = 500kHz, Unless Otherwise Noted
TEST
CONDITIONS
TMIN -TMAX
0 < VIN < V+
J
K
L
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
2.4
-
-
2.4
-
-
2.4
-
-
V
-
1
10
-
1
10
-
1
10
µA
-
15
-
-
15
-
-
15
-
pF
LOGIC OUTPUT
Low State Output
Voltage
VOL
IOUT = 1.6mA
TMIN -TMAX
-
-
0.4
-
-
0.4
-
-
0.4
V
High State Output
Voltage
VOH
IOUT = -200µA
TMIN -TMAX
2.8
-
-
2.8
-
-
2.8
-
-
V
Three-State Output IOX
Current
0 < VOUT < V+
-
1
-
-
1
-
-
1
-
µA
Logic Output
Capacitance
Three-State
-
15
-
-
15
-
-
15
-
pF
±4.5
-
±6.0
±4.5
-
±6.0
±4.5
-
±6.0
V
-
2
4
6
-
2
4
6
-
2
4
6
mA
COUT
POWER REQUIREMENTS
Supply Voltage
Range
VSUPPLY Functional Operation Only
Supply Current,
I+, I-
ISUPPLY
RM
TMIN -TMAX
NOTES:
4. Full scale range (FSR) is 10V (reference adjusted).
5. Assume all leads are soldered or welded to printed circuit board.
6. “J” and “K” versions not production tested. Guaranteed by Integral Linearity Test.
7. Typical values are not tested, for reference only.
8. Not production tested. Guaranteed by design.
AC Electrical Specifications Test Conditions V+ = +5V, V- = -5V, TA = 25oC, fCLK = 500kHz, unless otherwise noted. Data
derived from extensive characterization testing. Parameters are not production tested
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
READ CYCLE TIMING
Propagation Delay CS to Date
t cd
RD Low, A0 Valid
-
-
200
Propagation Delay A0 to Data
t ad
CS Low, RD Low
-
-
200
Propagation Delay RD to Data
t rd
CS Low, A0 Valid
-
-
200
Propagation Delay Data to Three-State
t rx
-
-
150
Propagation Delay EOC High to Data
t ed
-
-
200
WR Low Time
t wr
150
-
-
Propagation Delay WR Low to EOC Low
t we
Wait Mode
1
-
2
EOC High Time
t eo
Free Run Mode
0.5
-
1.5
Conversion Time
t conv
-
-
20
Clock Frequency Range
f CLK
-
500
-
ns
WRITE CYCLE TIMING
Functional Operation Only
NOTE:
9. All typical values have been characterized, but are not tested.
6-4
ns
1/fCLK
kHz
ICL7112
Pin Descriptions
PIN NO.
NAME
1
DESCRIPTION
No connection.
FORCE input for analog ground.
2
AGNDf
3
CS
Chip Select enables reading and writing (active low).
4
RD
ReaD (active low).
Byte select (low = D0 -D7, high = D 8 -D 11, OVR).
5
A0
6
BUS
7
DGND
8
D11
Bit 11 (most significant bit).
9
D10
Bit 10
10
D9
Bit 9
11
D8
Bit 8
12
D7
Bit 7
13
D6
Bit 6
14
D5
Bit 5
Bits
15
D4
Bit 4
(High =True)
16
D3
Bit 3
17
D2
Bit 2
18
D1
Bit 1
19
D0
Bit 0 (least significant bit).
Bus select (low = outputs enabled by A0, high = all outputs enabled together).
Digital GrouND return.
High Byte
Output
Data
Low Byte
20
No connection.
21
No connection.
22
No connection.
23
No connection.
24
No connection.
25
EOC
End of conversion flag (low = busy, high = conversion complete).
26
OVR
OVerRange flag (valid at end of conversion when output code exceeds full-scale;
three-state output enabled with high byte).
27
V+
28
PROG
Used for programming only. Must tie to V+ for normal operation.
29
TEST
Used for programming only. Must tie to V+ for normal operation.
30
OSC1
Oscillator inverter input.
31
OSC2
Oscillator inverter output.
32
TEST
Must tie to V+ for normal operation.
33
WR
WRite pulse input (low starts new conversion).
34
CAZ
Auto-zero capacitor connection (Note).
35
V-
36
COMP
37
VIN
38
VREF
SENSE line for reference input.
39
AGNDs
SENSE line for analog ground.
40
Positive power supply input.
Negative power supply input.
Used in test, tie to V -.
SENSE line for input voltage.
No connection
NOTE: The voltage of CAZ is driven; NEVER connect directly to ground.
6-5
ICL7112
Timing Diagrams
tCD
CS
A0
VALID
tAD
RD
tRX
tRD
D0 - D13
VALID
tED
EOC
= DON’T CARE
FIGURE 1. READ CYCLE TIMING
CS
tWR
WR
tWE
tCONV
EOC
tEO
= DON’T CARE
FIGURE 2. WRITE CYCLE TIMING
TABLE 2:
CS WR RD A0
x
x
BUS
x
a standard SAR-type converter. The Functional Block Diagram shows the functional diagram of the ICL7112 12-bit
A/D converter. The additional circuitry incorporated into the
ICL7112 is used to perform error correction and to maintain
the operating speed in the 40µs range.
I/O CONTROL
FUNCTION
0
0
1
x
x
x
x
Disables all chip commands.
0
x
0
0
0
Low byte is enabled.
0
x
0
1
0
High byte is enabled.
0
x
0
x
1
Low and High bytes enabled together.
x
x
1
x
x
Disables outputs (high-impedance).
TABLE 3:
Initiates a conversion.
The internal DAC of the ICL7112 is designed around a radix
of 1.85, rather than the traditional 2.00. This radix gives each
bit of the DAC a weight of approximately 54% of the previous
bit. The result is a usable range that extends to 3% beyond
the full-scale input of the A/D. The actual value of each bit is
measured and stored in the on-chip PROM. The absolute
value of each bit weight then becomes relatively unimportant
because of the error correction action of the ICL7112.
TRANSFER FUNCTION
INPUT VOLTAGE
EXPECTED OUTPUT CODE
VREF = -10.0V
OVR
MSB
0
+0.00244
0
0
0
0
0000000000
0000000000
0
1
+0.30029
0
0
0000111101
1
+4.99756
+5.00000
0
0
0
1
1111111111
0000000000
1
0
+9.99512
+9.99756
+10.00000
+10.00244
0
0
1
1
1
1
0
0
1111111111
1111111111
0000000000
0000000000
0
1
0
1
+10.29000
1
0
0000111101
1
The output of the high-speed auto-zeroed comparator is fed
to the data input of a successive approximation register
(SAR). This register is uniquely designed for the ICL7112 in
that it tests bit pairs instead of individual bits in the manner of
a standard SAR. At the beginning of the conversion cycle,
the SAR turns on the MSB (D11) and the MSB 4-bit (D7).
The sequence continues for each bit pair, BX and Bx-4 , until
only the four LSBs remain. The sequence concludes by testing the four LSBs individually.
LSB
Detailed Description
The ICL7112 is basically a successive approximation A/D
converter with an internal structure much more complex than
The SAR output is fed to the DAC register and to the preprogrammed PROM where it acts as PROM address. PROM
data is fed to a full-adder/accumulator where the decoded
results from each successive phase of the conversion are
summed with the previous results. After 20 clock cycles, the
accumulator contains the final binary data which is latched
and sent to the three-state output buffers. The accuracy of
the A/D converter depends primarily upon the accuracy of
the data that has been programmed into the PROM during
6-6
ICL7112
the final test portion of the manufacturing process.
The error correcting algorithm built into the ICL7112 reduces
the initial accuracy requirements of the DAC. The overlap in
the testing of bit pairs reduces the accuracy requirements on
the comparator which has been optimized for speed. Since
the comparator is auto-zeroed, no external adjustment is
required to get ZERO code for ZERO input voltage.
Twenty clock cycles are required for the complete 12-bit conversion. The auto-zero circuitry associated with the comparator is employed during the last three clock cycles of the
conversion to cancel the effect of offset voltage. Also during
this time, the SAR and accumulator are reset in preparation
for the start of the next conversion.
The overflow output of the full-adder is also the OVer Range
(OVR) output of the ICL7112. Unlike standard SAR type A/D
converters, the ICL7112 has the capability of providing valid
usable data for inputs that exceed the fullscale range by as
much as 3%.
Optimizing System Performance
When using A/D converters with 12 or more bits of resolution, special attention must be paid to grounding and the
elimination of potential ground loops. A ground loop can be
formed by allowing the return current from the lCL7112’s
DAC to flow through traces that are common to other analog
circuitry. If care is not taken, this current can generate small
unwanted voltages that add to or detract from the reference
or input voltages of the A/D converter.
Figure 3 and Figure 4 show two different grounding techniques. Although the difference between the two circuits may
not be readily apparent, the circuit of Figure 3 is very likely to
have significant ground loop errors which the circuit of Figure 4 avoids. In Figure 3, the supply currents for analog
ground, digital ground, and the reference voltage all flow
through a lead, common to the input. This will generate a DC
offset voltage due to the currents flowing in the resistance of
the common lead. This offset voltage will vary with the input
voltage and with the digital output. Even the auto-zero loop
of the ICL7112 cannot remove this error.
Figure 4 shows a much better arrangement. The ground and
reference currents do not flow through the input common
lead, eliminating any error voltages. Note that the supply
currents and any other analog system currents must also be
returned carefully to analog ground. The clamp diodes will
protect the ICL7112 against signals which could result from
separate analog and digital grounds. The absolute maximum
voltage rating between AGND and DGND is ±1.0V. The two
inverse-parallel diodes clamp this voltage to less than ±0.7V.
Input Warning
As with any CMOS integrated circuit, no input voltages
should be applied to the lCL7112 until the ±5V power supplies have stabilized.
Interfacing To Digital Systems
The_ICL7112 provides three-state data output buffers, CS,
RD, WR, and bus select inputs (A0 and BUS) for interfacing
to a wide variety of microcomputers and digital systems. The
I/O Control Truth Table shows the functions of the digital
control lines. The BUS select and A0 lines are provided to
enable the output data onto either 8-bit or 16-bit data buses.
A conversion is initiated by a WR pulse (pin 33) when CS
(pin 3) is low. Data is enabled on the bus when the chip is
selected and RD (pin 4) is low.
Figure 5 illustrates a typical interface to an 8-bit microcomputer. The “Start and Wait” operation requires the fewest
external components and is initiated by a low level on the
WR input to the ICL7112 after the I/O or memory mapped
address decoder has brought the CS input low. After executing a delay or utility routine for a period of time greater than
the conversion time of the ICL7112, the processor issues
two consecutive bus addresses to read output data into two
bytes of memory. A low level on A0 enables the LSBs, and a
high level enables the MSBs.
VIN +
VIN
SOURCE -
ICL7112
VREF -
VREF
SOURCE +
AGND
DGND
FIGURE 3. IMPROPER GROUNDING TECHNIQUE WILL CAUSE GROUND LOOP ERRORS
6-7
ICL7112
VIN +
VIN
SOURCE -
ICL7112
VREF -
VREF
SOURCE +
AGND
DGND
FIGURE 4. RECOMMENDED GROUNDING TECHNIQUE TO ELIMINATE GROUND LOOP ERRORS
ADDRESS BUS
A0
ADDRESS
DECODE
A0
A0 - AN
ICL7112
CS
CS
RD
RD
WR
WR
µP
BUS
OVR
OVR
D0 - D7 D8 - D11
D0 - D7
DATA BUS
WR
CS
A0
RD
START
CONVERSION
READ
LOW BYTE
WAIT
READ
HIGH BYTE
FIGURE 5. “START AND WAIT” OPERATION
By adding a three-state buffer and two control gates, the
End-of-Conversion (EOC) output can be used to control a
“Start and Poll” interface (Figure 6). In this mode, the A0 and
CS lines connect the EOC output to the data bus along with
the most significant byte of data. After pulsing the WR line to
initiate a conversion, the microprocessor continually reads
the most significant byte until it detects a high level on the
EOC bit. The “Start and Poll” interface increases data
throughput compared with the “Start and Wait” method by
eliminating delays between the conversion termination and
the microprocessor read operation.
Other interface configurations can be used to increase data
throughput without monopolizing the microprocessor during
waiting or polling operations by using the EOC line as an
interrupt generator as shown in Figure 7. After the conversion cycle is initiated, the microprocessor can continue to
execute routines that are independent of the A/D converter
until the converter’s output register actually holds valid data.
For fastest data throughput, the ICL7112 can be connected
directly to the data bus but controlled by way of a Direct
6-8
ICL7112
Memory Access (DMA) controller as shown in Figure 8.
Applications
Figure 9 shows a typical application of the ICL7112 12- bit
A/D converter. A bipolar input voltage range of +10V to -10V
is the result of using the current through R2 to force a 1/2
scale offset on the input amplifier (A1). The output of A1
swings from 0V to -1 0V. The overall gain of the A/D is varied
by adjusting the 100Ω trim resistor, R5 . Since the ICL7112 is
automatically zeroed every conversion, the system gain and
offset stability will be superb as long as a reference with a
tempco of 1ppm/oC and stable external resistors are used.
If is important to note that since the 7112’s DAC current
flows in A1 , the amplifier should be a wideband (GBW >
20MHz) type to minimize errors.
The clock for the ICL7112 is taken from whatever system
clock is available and divided down to the level for a conversion time of 40µs. Output data is controlled by the BUS and
A0 inputs. Here they are set for 8-bit bus operation with BUS
grounded and A0 under the control of the address decode
section of the external system.
Because the ICL7112’s internal accumulator generates
accurate output data for input signals as much as 3% greater
than full-scale, and because the converter’s OVR output
flags overrange inputs, a simple microprocessor routine can
be employed to precisely measure and correct for system
gain and offset errors. Figure 10 shows a typical data acquisition system that uses a 10V reference, input signal multiplexer, and input signal Track/Hold amplifier. Two of the
multiplexer’s input channels are dedicated to sampling the
system analog ground and reference voltage. Here, as in
Figure 9, bipolar operation is accommodated by an offset
resistor between the reference voltage and the summing
junction of A1 . A flip-flop in IC3 sets 1C2’s Track/Hold input
after the microprocessor has initiated a WR command, and
resets when EOC goes high at the end of the conversion.
The first step in the system calibration routine is to select the
multiplexer channel that is connected to system analog
ground and initiate a conversion cycle for the ICL7112. The
results represent the system offset error which comes from
the sum of the offsets from IC 1 , IC 2 , and A1 . Next the channel connected to the reference voltage is selected and measured. These results, minus the system offset error,
represent the system full-scale range. A gain error correction
factor can be derived from this data. Since the lCL7112 provides valid data for inputs that exceed full-scale by as much
as 3%, the OVR output can be thought of as a valid 13th
data bit. Whenever the OVR bit is high, however, the total
12-bit result should be checked to ensure that it falls within
100% and 103% of full-scale. Data beyond 103% of fullscale should be discarded.
Clock Considerations
The ICL7112 provides an internal inverter which is brought
out to pins OSC1 and OSC2, for crystal or ceramic resonator
oscillator operation. The clock frequency is calculated from:
20
fCLK = -----------------t C ONV
6-9
ICL7112
( )
ADDRESS BUS
A0
ADDRESS
DECODE
A0
A0 - AN
ICL7112
WR
WR
CS
CS
RD
RD
µP
EOC
BUS
1/4 74125
D0 - D7 D8 - D 11 OVR
D0 - D7
DATA BUS
(B)
END OF
CONVERSION
WR
CS
EOC
A0
RD
START
CONVERSION POLL
READ
HIGH BYTE
READ
HIGH BYTE
FIGURE 6. START AND POLL” OPERATION
6-10
READ
LOW BYTE
ICL7112
ADDRESS BUS
A0
ADDRESS
DECODE
A0
A0 - AN
CS
RD
RD
WR
WR
µP
ICL7112
EOC
INT
BUS
OVR
D0 - D 7 D8 - D11
D0 - D7
DATA BUS
INTERRUPT
WR
CS
EOC
A0
RD
START
CONVERSION
READ
LOW BYTE
FIGURE 7. USING EOC AS AN INTERRUPT
6-11
READ
HIGH BYTE
ICL7112
ADDRESS BUS
A0
A0
WR
A0 - A11
ICL7112
EOC
DRQN
CS
DACKN
RD
CS
DMA
CONTROLLER
BUS
OVR
D0 - D7
D0 - D7 D8 - D11
DATA BUS
EOC
DACKN
A0
READ
LOW BYTE
END OF
CONVERSION
READ
HIGH BYTE
FIGURE 8. DATA TO MEMORY VIA DMA CONTROLLER
6-12
START
CONVERSION
ICL7112
+5V
28
R4
10V
REFERENCE
PROG
R5
32
TEST
29
TEST
V+
OSC
100K
R1
R2
R3
100k
100k
50k
HI
INPUT VOLTAGE
+10V TO -10V
27 500KHz
36
37
EOC
VREF
34
0.22µF
DATA
CAZ
OUT
+
WR
39
RD
AGND
2
CS
A0
DIODES
1N914
25
COMP
36
-5V
HIGH
BYTE
13
8-BIT
DATA BUS
LOW BYTE
21
AGND
A2
SYSTEM
CLOCK
14
ICL7112
LO
DIVIDER
26
VIN
A2
+
30
V+
35
DGND
7
BUS
33
4
3
5
ADDRESS
DECODE
PINS 1, 20, 21, 22, 23, 24, 40
NO CONNECTIONS
6
DIGITAL
GROUND
FIGURE 9. TYPICAL APPLICATION WITH BIPOLAR INPUT RANGE, FORCED GROUND, AND 10V ULTRA STABLE REFERENCE
6-13
ADDRESS BUS
REFERENCE
10V
VCC
ADDRESS
DECODE
VREF
ADDRESS
DECODE
BUS
VS
IS
IC1
IH5108
ANALOG
INPUTS
A0
A0 - AN
CS
RD
RD
WR
WR
µP
ICL7112
IC 2
LF398
EOC
10k
OUT
+
VR
OVR
1/2
74125
IR
D8 - D13 D0 - D7
A0 - A2
Q
D0 - D 7
R
IC3
DATA
LATCH
1/2 4013
D
S
DATA BUS
FIGURE 10. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH ZERO AND REFERENCE LINES BROUGHT TO MULTIPLEXER
FOR SYSTEM GAIN AND OFFSET ERROR CORRECTION
6-14
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