Renesas M38K29MFL-XXXHP Single-chip 8-bit cmos microcomputer Datasheet

38K2 Group
REJ03B0193-0300
Rev.3.00
Oct 15, 2006
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Timers ............................................................................. 8-bit ✕ 3
•Watchdog timer ............................................................. 16-bit ✕ 1
• Serial Interface
DESCRIPTION
The 38K2 group is the 8-bit microcomputer based on the 740 family core technology.
The 38K2 group has the USB function, an 8-bit bus interface, a
Serial Interface, three 8-bit timers, and an 8-channel 10-bit A/D
converter, which are available for the PC peripheral I/O device.
The various microcomputers in the 38K2 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
•
•
•
•
FEATURES
• Basic machine-language instructions ....................................... 71
• The minimum instruction execution time .......................... 0.25 µs
(at 8 MHz system clock✻)
System clock✻: Reference frequency to internal circuit except
USB function
Memory size
ROM ................................................................ 16 K to 32 K bytes
RAM ............................................................... 1024 to 2048 bytes
Programmable input/output ports ............................................. 44
Software pull-up resistors
Interrupts .................................................. 16 sources, 16 vectors
USB function (Full-Speed USB2.0 specification) ...... 4 endpoints
USB HUB function (Full-Speed USB2.0 specification) .... 2 down ports
External bus interface ....................................... 8-bit ✕ 1 channel
Serial I/O ....................... 8-bit ✕ 1 (UART or Clock-synchronized)
A/D converter ................................................ 10-bit ✕ 8 channels
(8-bit reading available)
LED direct drive port ................................................................... 4
Clock generating circuit
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage (L version)
System clock/Internal clock division mode
At 12 MHz/2-divide mode(φ = 6 MHz) ................... 4.00 to 5.25 V
At 8 MHz/Through mode (φ = 8 MHz) ................... 4.00 to 5.25 V
At 6 MHz/Through mode (φ = 6 MHz) ................... 3.00 to 5.25 V
• Power dissipation
At 5 V power source voltage .................................. 125 mW (typ.)
(at 8 MHz system clock, in through mode)
At 3.3 V power source voltage ................................ 30 mW (typ.)
(at 6 MHz system clock, in through mode)
Operating temperature range .................................... –20 to 85°C
Packages
FP ............................ PLQP0064GA-A (64-pin 14 ✕ 14 mm LQFP)
HP ............................ PLQP0064KB-A (64-pin 10 ✕ 10 mm LQFP)
•
•
•
•
•
•
•
•
•
34
33
35
36
37
38
39
41
40
43
42
44
45
46
47
48
P05
P04
P03
P02
P01
P00
P57
P56
P55
P54
P53
P52/INT1
P51/CNTR0
P50/INT0
P27
P26
PIN CONFIGURATION (TOP VIEW)
P06
P07
P40/EXDREQ/RXD
P41/EXDACK/TXD
49
32
50
31
51
30
52
29
P42/EXTC/SCLK
P43/EXA1/SRDY
P30
P31
P32
P33/EXINT
P34/EXCS
P35/EXWR
P36/EXRD
P37/EXA0
P10/DQ0/AN0
P11/DQ1/AN1
53
28
27
54
55
56
M38K27M4L-XXXFP/HP
26
M38K29F8LFP/HP
24
57
58
25
23
12
13
14
15
16
XIN
XOUT
VCC
CNVSS2
P60(LED0)
10
11
9
8
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
CNVSS
RESET
VCCE
VREF
VSS
17
7
18
64
6
19
63
5
20
62
3
21
61
4
60
2
22
1
59
P25
P24
D2+
D2D1+
D1D0D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P63(LED3)
P62(LED2)
P61(LED1)
Package type : PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A)
Fig. 1 Pin configuration of 38K2 group
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 1 of 147
Fig. 2 Functional block diagram
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 2 of 147
12
13
P6 (4)
35 36 37 38 39 4041 42
INT1
INT0
RAM
P5 (8)
Watchdog timer
Clock
generating
circuit
21
16 17 18 19
20
PVSS PVCC XIN XOUT
51 52 53 54
P4 (4)
SI/O
RAM
I/F
9
VCCE
14
VCC
P3 (8)
55 56 57 58 59 60 61 62
EXTBUS (8)
ROM
Data bus
11
VSS
23
24
25
26
D0DVCC TrON
USBVREF D0+
22
USB
CPU
28
29
30
3132 33 34
P2 (4)
8
RESET
D1-D1+D2- D2+
27
USB HUB
FUNCTIONAL BLOCK DIAGRAM (Package : PLQP0064GA-A/PLQP0064KB-A)
VREF
10
P1 (8)
63 64 1 2 3 4 5 6
10-bit A/D
converter (8)
CNTR0
Timer X (8)
Timer 2 (8)
P0(8)
43 44 45 46 47 4849 50
15
7
Timer 1 (8)
CNVSS2
CNVSS
38K2 Group
38K2 Group
PIN DESCRIPTION
Table 1. Pin description
Pin
VCC, VSS
VCCE
CNVSS
CNVSS2
VREF
Function
Name
Function except a port function
Power source
Analog power
source
CNVSS
DVCC
PVCC, PVSS
RESET
XIN
CNVSS2
Analog reference
voltage input
Analog power
source
Reset input
Clock input
XOUT
Clock output
USBVREF
USB reference
power source
TrON
USB reference
voltage output
USB upstream
I/O
D0+, D0-
D1+, D1-,
D2+, D2-
USB downstream I/O
P00–P07
I/O port P0
P10/DQ0/AN0– I/O port P1
P17/DQ7/AN7
P24–P27
I/O port P2
P30–P32
I/O port P3
P33/ExINT
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
P40/ExDREQ/RxD I/O port P4
P41/ExDACK/TxD
P42/ExTC/SCLK
P43/ExA1/SRDY
P50/INT0
P51/CNTR0
P52/INT1
P53–P57
P60–P63
I/O port P5
I/O port P6
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
• Apply voltage of 3.0 V – 5.25 V (L version) to VCC, and 0 V to VSS.
• Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC.
• This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory
mode, this pin becoems VPP power source input pin.
• This pin controls the operation mode of the chip. Connect this pin to VSS.
• Reference voltage input pin for A/D converter.
• Power source pin for analog circuit.
• Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS.
• Reset input pin for active “L”
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Power source pin for USB port circuit.
In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.60 to 4.00 V apply
3.3 V power supply from the external because use of the built-in USB reference voltage circuit is
prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC because use of the
built-in USB reference voltage circuit is prohibited in this voltage range.
• Output pin to pull-up D0+ by 1.5 kΩ external resistor.
• USB upstream I/O port
• USB input level
• USB output level output structure
• USB downstream I/O port
• USB input level
• USB output level output structure
• Key input pins (key-on wake up interrupt)
• 8-bit I/O port
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Pull-up control is enabled.
• A/D converter input pins
• 8-bit I/O port
• External bus interface function pins
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually
• External bus interface function pins
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Serial I/O function pins
• 4-bit I/O port
• External bus interface function pins
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Interrupt input pin
• 8-bit I/O port
• I/O direction register allows each pin to be individually
• Timer X funciton pin
programmed as either input or output.
• Interrupt input pin
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port; • I/O direction register allows each pin to be individually programmed as either input
or output.; • CMOS compatible input level• CMOS 3-state output structure;
• Output large current for LED drive is enabled.
page 3 of 147
38K2 Group
PART NUMBERING
Product M38K2 7 M 4 L - XXX FP
Package type
FP : PLQP0064GA-A package
HP : PLQP0064KB-A package
ROM number
Omitted in the flash memory version.
Omitted in the flash memory version.
L : L version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used as a
user’s ROM area.
However, they can be programmed or erased
in the flash memory version, so that users can
use them.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 4 of 147
38K2 Group
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38K2 group as follows.
PLQP0064GA-A ...................... 0.8 mm-pitch plastic molded LQFP
PLQP0064KB-A ....................... 0.5 mm-pitch plastic molded LQFP
100D0M ........................... 0.65 mm-pitch metal seal PIGGY BACK
Memory Type
Support for mask ROM and flash memory versions.
Memory Size
Flash memory size .......................................................... 32 Kbytes
Mask ROM size ............................................................... 16 Kbytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion Plan
ROM size
(bytes)
: Mass Production
60K
M38K29F8L
32K
M38K27M4L
16K
8K
256
512
1,024
2,048
RAM size (bytes)
Fig. 4 Memory expansion plan
Currently products are listed below.
As of October 2006
Table 2. List of 38K2 group products (L version)
Product
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
16384
(16254)
1024
32768
(32638)
2048
—
2048
M38K27M4L-XXXFP
M38K27M4L-XXXHP
M38K29F8LFP
M38K29F8LHP
M38K29RFS
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 5 of 147
Package
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
100D0M
Remarks
Mask ROM version
Flash memory version
38K2 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
[Accumulator (A)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Figure 6 shows the store and the return movement into the stack.
If there are registers other than those described in Figure 5, the
users need to store them with the program.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Program Counter (PC)]
The 38K2 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The CPU has the 6 registers. The register structure is shown in
Figure 5.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 6 of 147
38K2 Group
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 7 of 147
38K2 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 8 of 147
38K2 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
0
1
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0:
Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Not used (returns “0” when read)
(Do not write “1” to this bit)
System clock selection bit
0 : Main clock (XIN)
1 : fSYN
System clock division ratio selection bits
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
Fig. 7 Structure of CPU mode register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 9 of 147
38K2 Group
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In
the flash memory version, program and erase can be performed in
the reserved area.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF 16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
RAM area
RAM size
(bytes)
Address
XXXX16
192
00FF16
256
013F16
384
01BF16
512
023F16
640
02BF16
768
033F16
896
03BF16
1024
043F16
1536
063F16
2048
083F16
000016
SFR area
Zero page
004016
010016
RAM
XXXX16
Not used
0FE016
0FFF16
SFR area
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
F00016
F08016
YYYY16
Reserved ROM area
(128 bytes)
8192
E00016
E08016
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B08016
24576
A00016
A08016
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
53248
300016
308016
FFFE16
57344
200016
208016
FFFF16
61440
100016
108016
Fig. 8 Memory map diagram
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 10 of 147
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
Reserved ROM area
Special page
38K2 Group
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
002016 Prescaler 12 (PRE12)
002116 Timer 1 (T1)
002216 Timer 2 (T2)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
002316 Timer X mode register (TM)
002416 Prescaler X (PREX)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
002516 Timer X (TX)
002616 Transmit/Receive buffer register (TB/RB)
002716 Serial I/O status register (SIOSTS)
002816 HUB interrupt source enable register (HUBICON)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
002916 HUB interrupt source register (HUBIREQ)
002A16 HUB down stream port index register (HUBINDEX)
002B16 HUB port field register 1 (DPXREG1)
002C16 HUB port field register 2 (DPXREG2)
000D16 Port P6 direction register (P6D)
000E16 Reserved (Note)
000F16 Reserved (Note)
001016 USB control register (USBCON)
002D16 HUB port field register 3 (DPXREG3)
001116 USB function/Hub enable register (USBAE)
001216 USB function address register (USBA0)
001316 USB HUB address register (USBA1)
001416 Frame number register Low (FNUML)
001516 Frame number register High (FNUMH)
001616 USB interrupt source enable register (USBICON)
001716 USB interrupt source register (USBIREQ)
001816 Endpoint index register (USBINDEX)
001916 Endpoint field register 1 (EPXXREG1)
001A16 Endpoint field register 2 (EPXXREG2)
001B16 Endpoint field register 3 (EPXXREG3)
001C16 Endpoint field register 4 (EPXXREG4)
001D16 Endpoint field register 5 (EPXXREG5)
001E16 Endpoint field register 6 (EPXXREG6)
001F16 Endpoint field register 7 (EPXXREG7)
002E16 Reserved (Note)
002F16 Reserved (Note)
003016 EXB interrupt source enable register (EXBICON)
003116 EXB interrupt source register (EXBIREQ)
003216 Reserved (Note)
003316 EXB index register (EXBINDEX)
003416 Register window 1 (EXBREG1)
003516 Register window 2 (EXBREG2)
003616 AD control register (ADCON)
003716 AD conversion register 1 (AD1)
003816 AD conversion register 2 (AD2)
003916 Watchdog timer control register (WDTCON)
003A16 Reserved (Note)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
0F E016 Serial I/O control register (SIOCON)
0F E116 UART control register (UART CON)
0FE216 Baud rate generator (BRG)
0FF016 Port P0 pull-up control register (PULL0)
0FF116 Reserved (Note)
0FE316 Reserved (Note)
0F E416 Reserved (Note)
0FF316 Interrupt edge selection register (INTEDGE)
0FF416 Reserved (Note)
0F E516 Reserved (Note)
0F E616 Reserved (Note)
0FF516 Reserved (Note)
0FF616 Reserved (Note)
0FF716 Reserved (Note)
0F E716 Reserved (Note)
0F E816 Reserved (Note)
0FE916 Reserved (Note)
0FEA16 Reserved (Note)
0FEB16 Reserved (Note)
0FEC16 Endpoint field register 8 (EPXXREG8)
0FED16 Endpoint field register 9 (EPXXREG9)
0FEE16 Reserved (Note)
0FEF16 Reserved (Note)
0FF216 Port P5 pull-up control register (PULL5)
0FF816 PLL control register (PLLCON)
0FF916 Downstream port control register (DPCTL)
0FFA16 Reserved (Note)
0FFB16 MISRG
0FFC16 Reserved (Note)
0FFD16 Reserved (Note)
0FFE16 Flash memory control register (FMCR)
0FFF16 Reserved (Note)
Note: Do not write any data to these addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 11 of 147
38K2 Group
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Table 5 I/O ports functions
Pin
P00–P07
Name
Port P0
P10–P17
Port P1
P24–P27
Port P2
P30–P32
P33/ExINT
Port P3
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
P40/RxD/
ExDREQ
Input/Output
Input/output,
individual bits
I/O Format
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
(Power source is
VCCE)
CMOS compatible
input level
CMOS 3-state output
CMOS/TTL compatible input level
CMOS 3-state output
(Power source is
VccE)
Port P4
P41/TxD/
ExDACK
P42/SCLK/
ExTC
P43/SRDY/
ExA1
P50/INT0
P52/INT1
P51/CNTR0
P53–P57
P60–P63
CMOS compatible
input level
CMOS 3-state output
Port P5
Non-Port Function
Key-on wake up
A/D conversion input
External bus interface
funciton I/O
Diagram No.
(1)
AD control register
EXB control register
(2)
(3)
External bus interface
funciton output
External bus interface
funciton input
EXB control register
(4)
(5)
EXB control register
(6)
Serial I/O input
External bus interface
funciton output
Serial I/O output
External bus interface
funciton input
Serial I/O I/O
External bus interface
funciton input
Serial I/O output
External bus interface
funciton input
External interrupt input
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Port P5 pull-up control
register
Interrupt edge selection
register
Timer X mode register
(7)
Timer X function I/O
Port P6
Related SFRs
Port P0 pull-up control
register
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 12 of 147
38K2 Group
(1) Port P0
(4) Ports P30–P32
Pull-up control bit
Direction register
Direction register
Data bus
Port latch
Data bus
VCCE
Port latch
Key-on wake-up input
(5) Port P33
(2) Port P1
EXOE
VCCE
VCCE
External bus interface enable bit
External bus interface enable bit
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
EXINT output
EXB data output
Output buffer
EXB data input
Input buffer
(6) Ports P34, P35, P36, P37
VCCE
External bus interface enable bit
A/D conversion input
Direction register
Analog input pin selection bit
Data bus
Port latch
(3) Port P2
Direction register
Data bus
Port latch
Fig. 10 Port block diagram (1)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 13 of 147
EXCS(P34)
EXWR(P35)
EXRD(P36)
EXA0(P37)
External bus interface enable bit
38K2 Group
(11) Ports P50, P52
(7) Port P40
Pull-up control bit
Serial I/O enable bit
Receive enable bit
VCCE
Direction register
External bus interface enable bit
Direction register
Port latch
Data bus
Port latch
Data bus
INT0 (P50), INT1 (P52) interrupt input
EXDreq output
Serial I/O input
(8) Port P41
(12) Port P51
Serial I/O enable bit
Receive enable bit
VCCE
Direction register
External bus interface enable bit
Direction register
Port latch
Data bus
Data bus
Port latch
Pulse output mode
Timer output
Serial I/O output
CNTR0 interrupt input
EXDack
External bus interface enable bit
(13) Ports P53–P57
(9) Port P42
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O synchronous clock selection bit
Serial I/O enable bit
External bus interface enable bit
Direction register
VCCE
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O clock output
(14) Port P6
Serial I/O external clock input
Serial I/O synchronous clock selection bit
External bus interface enable bit
EXTC
Data bus
(10) Port P43
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
VCCE
External bus interface enable bit
Direction register
Data bus
Port latch
Serial I/O output
EXA1
Fig. 11 Port block diagram (2)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 14 of 147
External bus interface enable bit
Direction register
Port latch
38K2 Group
b7
b0
Port P0 pull-up control register
(PULL0 : address 0FF016)
P00 pull-up control bit
0 : No pull-up
1 : Pull-up
P01 pull-up control bit
0 : No pull-up
1 : Pull-up
P02 pull-up control bit
0 : No pull-up
1 : Pull-up
P03 pull-up control bit
0 : No pull-up
1 : Pull-up
P04 pull-up control bit
0 : No pull-up
1 : Pull-up
P05 pull-up control bit
0 : No pull-up
1 : Pull-up
P06 pull-up control bit
0 : No pull-up
1 : Pull-up
P07 pull-up control bit
0 : No pull-up
1 : Pull-up
b7
b0
Port P5 pull-up control register
(PULL5 : address 0FF216)
P50 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
P52 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
Fig. 12 Structure of port I/O-related registers
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 15 of 147
38K2 Group
INTERRUPTS
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
0FF3 16 ), Timer X mode register (address
002316)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (active edge switch bit).
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Interrupts occur by sixteen sources: four external, eleven internal,
and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Table 6 Interrupt vector addresses and priority
Interrupt Source
Priority
Reset (Note 2)
USB bus reset
USB SOF
USB device
1
2
3
4
External bus
INT0
Timer X
Timer 1
Timer 2
INT1
USB HUB
Serial I/O
reception
Serial I/O
transmission
CNTR0
Key-on wake up
A/D conversion
BRK instruction
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
Interrupt Request
Generating Conditions
FFF716
FFFA16
FFF816
FFF616
5
FFF516
FFF416
6
7
8
9
10
11
12
FFF316
FFF116
FFED16
FFE716
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
At reset
At detection of USB bus reset signal (2.5 µs interval SE0)
At detection of USB SOF signal
At detection of resume signal (K state or SE0) or suspend signal (3
ms interval bus idle), or at completion of transaction
At completion of reception or transmission or at completion of DMA
transmission
At detection of either rising or falling edge of INT0 input
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling edge of INT1 input
At detection of USB HUB downport’s state switch
At completion of serial I/O data reception
13
FFE516
FFE416
At completion of serial I/O data transmission
14
15
16
17
FFE316
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P0 (at input mode)
At completion of A/D conversion
At BRK instruction execution
FFFB16
FFF916
FFEF16
FFEB16
FFE916
FFE116
FFDF16
FFDD16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 16 of 147
38K2 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 0FF316)
INT0 interrupt edge selection bit
Not used (return “0” when read)
INT1 interrupt edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
USB bus reset interrupt request bit
USB SOF interrupt request bit
USB device interrupt request bit
EXB interrupt request bit
INT0 interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D16)
INT1 interrupt request bit
USB HUB interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
CNTR0 interrupt request bit
Key-on wake-up interrupt request bit
A/D conversion interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
✽ “0” can be set by software, but “1”
cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
USB bus reset interrupt enable bit
USB SOF interrupt enable bit
USB device interrupt enable bit
EXB interrupt enable bit
INT0 interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
✽ “0” can be set by software, but “1”
cannot be set.
Fig. 14 Structure of interrupt-related registers
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 17 of 147
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
INT1 interrupt enable bit
USB HUB interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
CNTR0 interrupt enable bit
Key-on wake-up interrupt enable bit
A/D conversion interrupt enable bit
Fix this bit to “0”.
0 : Interrupts disabled
1 : Interrupts enabled
38K2 Group
Key Input Interrupt (Key-on Wake Up)
“1” to “0”. An example of using a key input interrupt is shown in
Figure 15, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P00–P03.
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P0 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PXx
“L” level output
✽
PULL 0 register
Bit 7 = “0”
✽✽
Port P07
direction register = “1”
Key input interrupt request
Port P07
latch
P07 output
PULL 0 register
Bit 6 = “0”
✽
✽✽
Port P06
direction register = “1”
Port P06
latch
P06 output
PULL 0 register
Bit 5 = “0”
✽
✽✽
Port P05
direction register = “1”
Port P05
latch
P05 output
PULL 0 register
Bit 4 = “0”
✽
✽✽
Port P04
direction register = “1”
Port P04
latch
P04 output
PULL 0 register
Bit 3 = “1”
✽
✽✽
Port P03
direction register = “0”
Port P03
latch
P03 input
PULL 0 register
Bit 2 = “1”
✽
✽✽
Port P02
direction register = “0”
Port P02
latch
P02 input
PULL 0 register
Bit 1 = “1”
✽
✽✽
P01 input
Port P01
direction register = “0”
Port P01
latch
PULL 0 register
Bit 0 = “1”
✽
P00 input
✽✽
Port P0
Input reading circuit
Port P00
latch
Port P00
direction register = “0”
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P0 block diagram
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 18 of 147
38K2 Group
TIMERS
Timer 1 and Timer 2
The 38K2 group has three timers: timer X, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down count timers. When the timer reaches “00 16”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
The count source of prescaler 12 is the system clock divided by
16. The output of prescaler 12 is counted by timer 1 and timer 2,
and a timer underflow periodically sets the interrupt request bit.
Timer X
Timer X can each select in one of four operating modes by setting
the timer X mode register.
(1) Timer Mode
b7
The timer counts the count source selected by timer count source
selection bit.
b0
Timer X mode register
(TM : address 002316)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
0 : Falling edge active for CNTR0 interrupt
Count at rising edge in event counter mode
1 : Rising edge active for CNTR0 interrupt
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
Fig. 16 Structure of timer X mode register
(2) Pulse Output Mode
The timer counts the system clock divided by 16. Whenever the
contents of the timer reach “00 16 ”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is
“0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P51 direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 pin.
When the CNTR0 active edge selection bit is “0”, the rising edge of
the CNTR0 pin is counted.
When the CNTR0 active edge selection bit is “1”, the falling edge
of the CNTR0 pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 active edge selection bit is “0”, the timer counts the
system clock divided by 16 while the CNTR0 pin is at “H”. If the
CNTR0 active edge selection bit is “1”, the timer counts it while the
CNTR0 pin is at “L”.
The count can be stopped by setting “1” to the timer X count stop
bit in any mode. The corresponding interrupt request bit is set
each time a timer underflows.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 19 of 147
38K2 Group
Data bus
Divider
System clock
1/16
Pulse width
measurement
mode
CNTR0 active
edge selection bit
“0”
P51/CNTR0
Event
counter
mode
Prescaler X latch (8)
Timer mode
Pulse output
mode
Prescaler X (8)
Timer X latch (8)
Timer X (8)
Timer X count stop bit
CNTR0 interrupt
request bit
“1”
CNTR0 active
edge selection bit
Port P51
direction
register
Timer X interrupt
request bit
“1”
“0”
Port P51
latch
Q
Q
Toggle
flip-flop
R
T
Timer X latch write
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
Divider
1/16
System clock
Prescaler 12 (8)
Timer 2 interrupt
request bit
Timer 1 interrupt
request bit
Fig. 17 Timer block diagram
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 20 of 147
38K2 Group
SERIAL INTERFACE
Serial I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of address 0FE016) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
Serial I/O control register
Address 002616
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P40/EXDREQ/RxD
Address 0FE016
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P42/EXTC/SCLK
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
System clock
Baud rate generator
P43/EXA1/SRDY
F/F
1/4
Address 0FE216
1/4
Clock control circuit
Falling-edge detector
Shift clock
P41/EXDACK/TxD
Transmit shift register
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 002716
Transmit buffer register
Address 002616
Data bus
Serial I/O status register
Fig. 18 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output
TXD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 002616)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O function
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 21 of 147
38K2 Group
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 002616
P40/EXDREQ/RxD
Serial I/O1 control register Address 0FE016
OE
Receive buffer register
Character length selection bit
STdetector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
UART control register
Address 0FE116
SP detector
PE FE
Clock control circuit
Serial I/O synchronous clock selection bit
P42/EXTC/SCLK
BRG count source selection bit
Frequency division ratio 1/(n+1)
System clock
Baud rate generator
Address 0FE216
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
P41/EXDACK/TxD
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 002716
Transmit buffer register
Address 002616
Data bus
Fig. 20 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TBE=1
Serial output TXD
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
✽ Generated
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
D1
SP
ST
D0
D1
SP
at 2nd bit in 2-stop-bit mode
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : T he receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 22 of 147
38K2 Group
[Serial I/O Control Register (SIOCON)] 0FE016
The serial I/O control register contains eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 0FE116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.
[Serial I/O Status Register (SIOSTS)] 002716
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 002616
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer register is “0”.
[Baud Rate Generator (BRG)] 0FE216
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 23 of 147
38K2 Group
b7
b0
Serial I/O status register
(SIOSTS : address 002716)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b0
Serial I/O control register
(SIOCON : address 0FE016)
BRG count source selection bit (CSS)
0: System clock
1: System clock/4
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY output enable bit (SRDY)
0: P43 pin operates as ordinary I/O pin
1: P43 pin operates as SRDY output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
b7
b7
b0 UART control regi ster
(UART CON : address 0FE116)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Not used (return “0” when read)
(This is a write disabled bit.)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O control registers
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 24 of 147
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P40–P43 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P40–P43 can operate as serial I/O pins)
38K2 Group
USB FUNCTION
38K2 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB2.0's Full-Speed Transfer
Mode (12 Mbps, equivalent to USB1.1). This circuit also supports
all four transfer-types specified in the standard USB specification.
The USBFCC has two USB addresses and 6 endpoints, enabling
separate control of the HUB functions and peripheral functions.
The USB address for HUB functions is equipped with two endpoints. Each endpoint is fixed to a specified transfer type:
Endpoint 0 is fixed to Control Transfer and Endpoint 1 is fixed to
Interrupt Transfer.
The USB address for peripheral functions is equipped with four
endpoints that can select its transfer type. Although Endpoint 0 is
fixed to Control Transfer, the Endpoints 1 to 3 can be set to Interrupt Transfer, Bulk Transfer, or Isochronous Transfer.
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit enables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modification.
The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vectors/24 factors).
With all this essential yet comprehensive built-in hardware, your
system using the 38K2 group will be ready for any USB application that comes its way.
38K2 Group MCU
Built-in Peripheral
Functions
CPU
Program ROM
External MCU
Interrupt request
External Bus Interface
(EXB)
Multi-channel RAM
USB
USB Bus
(USB-Host)
Data transmit/Receive path
[Direct RAM Access Type]
Fig. 23 USB function overview
USB Data Transfer
The USB specification promises 12 Mbps data transfer in the fullspeed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
However, in USB data transfer, bit-stuffing may be executed depending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multichannel RAM will change owing to the frequency of internal clock φ:
When the USBFCC is operating at φ =8 MHZ, access for a normal
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 25 of 147
transfer is performed every 5 to 6 cycles and access for a bit-stuffing transfer is performed in up to 7 cycles.
If the EXB function is enabled in the above conditions, this function generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
When operating at φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock occurs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be extended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.
38K2 Group
USB Function Control Circuit (USBFCC)
Block Diagram
The following diagram shows the USBFCC block diagram. The circuit comprises:
(1) Serial Interface Engine (SIE)
(2) Device Control Unit (DCU)
(3) Internal Memory Interface (MIF)
(4) CPU Interface (CIF)
USB Function Control Circuit
DCU control
MIF control
USB Transceiver
SIE
DCU
SIE status
MIF
CIF
CPU
DCU status
SIE control
D0+
D0-
Transmit/Receive
data
Multi-Channel RAM
Fig. 24 USB Function Control Circuit (USBFCC) block diagram
(1) Serial Interface Engine (SIE)
The SIE performs the following USB lower-layer protocols (packets, transactions):
•Sampling of receive data and clock, generation of transmit clock
•Serial-to-parallel conversion of transmit/receive data
•NRZI (Non Return Zero Invert) encode/decode
•Bit stuffing/unstuffing
•SYNC (Synchronization Pattern) detection, EOP (End of
Packet) detection
•USB address detection, endpoint detection
•CRC (Cyclic Redundancy Check) generation and checking
(2) Device Control Unit (DCU)
The DCU manages the following USB upper-layer protocols (address/endpoint and control-transfer sequence):
•Status control for each endpoint
•Control-transfer sequence control
•Memory interface status control
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 26 of 147
(3) Memory Interface (MIF)
The MIF controls the flow of data transfer between the SIE and the
multi-channel RAM under the management of the DCU.
(4) CPU Interface (CIF)
The CIF performs the following functions:
•Mode setting via registers, DCU control signal generation, DCU
status signal reading
•Interrupt signal generation
•Internal bus interface control.
38K2 Group
USB Port External Circuit Configuration
The operation mode of the USB port driver circuit can be configured by USB control register (address 001016).
Figure 25 and Figure 26 show the USB port external circuit block
diagram.
VREFCON
VREFE
DVCC
0
1
0
Hiz
Hiz
1
3.3V output
Normal mode
3.3V output
Low-power mode
USBVREF status
VREFE
USBVREF
USB Reference
Voltage Circuit
VREFCON
0.1 µF
2.2 µF
TRON
TRONCON
TRONE
XOUT
PLL
1.5 kΩ
Full
Speed
fVCO “1”
D0+
27 Ω
D0-
27 Ω
fUSB
USB
Module
“0”
USBE
+
-
UCLKCON
USBDIFE
USBE
Full
Speed
USBE
Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC ≤ 5.25V)
3.0V to 3.6V
(Note)
USBVREF
0.1 µF
TRON
TRONCON
TRONE
XOUT
PLL
1.5 kΩ
Full
Speed
fVCO “1”
D0+
27 Ω
D0-
27 Ω
fUSB
“0”
USB
Module
USBE
+
-
UCLKCON
USBDIFE
USBE
Full
Speed
USBE
Note: In Vcc = 3.0 V to 3.6 V connect this pin to Vcc.
Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC ≤ 4.0V)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 27 of 147
38K2 Group
Endpoint Buffer Area Setting
The buffer area used in data transfer can be assigned to any area
of the multi-channel RAM for each endpoint.
●Buffer area beginning address
The buffer area configuration register (address 0FED 16) defines
the beginning address of the buffer area (every 32 bytes) for each
Endpoint. However, the only RAM area is configurable.
•00h [Address 000016], 01h [Address 002016]: Not configurable
•02h [Address 004016] to 1Fh [Address 03E016]: Configurable
●Interrupt-source dependant buffer area offset address
An offset value is added to the beginning address of each source,
which is specified by the interrupt source register (address
001D16), for each endpoint.
This section describes in detail the beginning address specified by
the buffer area set register as offset address 00h, according to
each endpoint.
(1) Endpoint 00
Endpoint 00 has two kinds of interrupt sources for accessing the
buffer. The respective address offsets are:
•BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h
•BRDY00 (OUT or IN Buffer Ready Interrupt):
Offset address = 08h
(2) Endpoint 01
The buffer area offset address for each interrupt source for of Endpoint 01 varies according to the contents of the EP01 set register
(address 001916).
•In single buffer mode (DBLB01 = “0”):
Endpoint 01 has only one interrupt source for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
•In double buffer mode (DBLB01 = “1”):
Endpoint 01 has two kinds of interrupt sources for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
(a) When selecting Endpoint 00
Offset
Memory
00h
02A016
(b) When selecting Single Buffer Mode
Offset
Memory
00h
02A016
Memory
0FED16 = 15h
002016
00
SFR
Disabled to be used
01
0000 0010 1010 0000
004016
02
006016
03
RAM
02A016
15
03E016
1F
Fig. 27 Example setting of buffer area beginning address
B1RDY01 (Buffer 1 Ready Interrupt):
The offset address varies according to the double buffer beginning address set bit (BSIZ01).
-Offset address = 08h when BSIZ01 = 00
-Offset address = 10h when BSIZ01 = 01
-Offset address = 40h when BSIZ01 = 10
-Offset address = 80h when BSIZ01 = 11
(3) Endpoints 02 and 03
Same as Endpoint 01.
(4) Endpoint 10
Same as Endpoint 00.
(5) Endpoint 11
Endpoint 11 has only one interrupt source for accessing the buffer.
B0RDY11 (Buffer 0 Ready Interrupt): Offset address = 00h
Notes
The selected RAM area must be within addresses 0040 16 to
03FF16.
Make sure the buffer area beginning address is set in agreement
with the offset address and the number of transmit/receive data
bytes.
This is particularly important when in the double buffer mode or
when handling 64-byte data.
(c) When selecting Double Buffer Mode
(when BSIZ01 = 11)
Offset
Memory
00h
02A016
BSRDY00
02A816
0FED16
000016
(d) When selecting Endpoint 11
Offset
Memory
02A016
00h
B0RDY01
08h
B0RDY11
B0RDY01
80h
032016
BRDY00
B1RDY01
Fig. 28 Examples of interrupt source dependant buffer area offset address
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 28 of 147
38K2 Group
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
22 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
(IREQ1: Address 003C16)
USB bus reset
USB interrupt bit
(USBIREQ: Address 001716)
—
USB SOF
—
USB device
EP00
EP01
EP02
EP03
EP10
EP11
SUS
RSM
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 29 of 147
Interrupt source
At USB bus reset signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoint 01 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 02 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 03 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 10 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoin 11 data transfer complete:
•Buffer 0 ready (write enabled state)
At suspend signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
38K2 Group
[USBIREQ]
[EPXXREG5]
[USBICON]
[EP00REQ]
BRDY00
EP00E
CTEND00
USB device
interrupt request
EP00
CTSTS00
BSYDY00
ERR00
[EP01REQ]
EP01E
B0RDY01
B1RDY01
EP01
ERR01
[EP02REQ]
EP02E
B0RDY02
B1RDY02
EP02
ERR02
[EP03REQ]
EP03E
B0RDY03
B1RDY03
EP03
ERR03
[EP10REQ]
BRDY10
EP10E
CTEND10
EP10
CTSTS10
BSYDY10
ERR10
EP11E
[EP11REQ]
B0RDY11
EP11
SUSE
SUS
RSME
RSM
Fig. 29 USB device interrupt control
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 30 of 147
38K2 Group
USB Register List
The USB register list is shown below.
Address
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
Register Name
SYMBOL
USB SFR
bit 7
bit 6
USB control register
USB Function/Hub enable register
USB function address register
USB HUB address register
Frame number register Low
Frame number register High
USB interrupt source enable register
USB interrupt source register
Endpoint index register
Endpoint field register 1
Endpoint field register 2
Endpoint field register 3
Endpoint field register 4
Endpoint field register 5
Endpoint field register 6
Endpoint field register 7
Endpoint field register 8
Endpoint field register 9
USBCON
USBAE
USBA0
USBA1
FNUML
FNUMH
USBICON
USBIREQ
USBINDEX
EPXXREG1
EPXXREG2
EPXXREG3
EPXXREG4
EPXXREG5
EPXXREG6
EPXXREG7
EPXXREG8
EPXXREG9
EP00 stage register
EP00 control register 1
EP00 control register 2
EP00 control register 3
EP00 interrupt source register
EP00 byte number register
EP00STG
EP00CON1
EP00CON2
EP00CON3
EP00REQ
EP00BYT
EP00 buffer area set register
EP00BUF
EP01 set register
EP01 control register 1
EP01 control register 2
EP01 control register 3
EP01 interrupt source register
EP01 byte number register 0
EP01 byte number register 1
EP01 MAX. packet size register
EP01 buffer area set register
EP01CFG
EP01CON1
EP01CON2
EP01CON3
EP01REQ
EP01BYT0
EP01BYT1
EP01MAX
EP01BUF
TYP01[1:0]
EP02 set register
EP02 control register 1
EP02 control register 2
EP02 control register 3
EP02 interrupt source register
EP02 byte number register 0
EP02 byte number register 1
EP02 MAX. packet size register
EP02 buffer area set register
EP02CFG
EP02CON1
EP02CON2
EP02CON3
EP02REQ
EP02BYT0
EP02BYT1
EP02MAX
EP02BUF
TYP02[1:0]
EP03 set register
EP03 control register 1
EP03 control register 2
EP03 control register 3
EP03 interrupt source register
EP03 byte number register 0
EP03 byte number register 1
EP03 MAX. packet size register
EP03 buffer area set register
EP03CFG
EP03CON1
EP03CON2
EP03CON3
EP03REQ
EP03BYT0
EP03BYT1
EP03MAX
EP03BUF
TYP03[1:0]
EP10 set register
EP10 control register 1
EP10 control register 2
EP10 control register 3
EP10 interrupt source register
EP10 byte number register
EP10STG
EP10CON1
EP10CON2
EP10CON3
EP10REQ
EP10BYT
EP10 buffer area set register
EP10BUF
EP11 set register
EP11 control register 1
EP11 control register 2
EP11CFG
EP11CON1
EP11CON2
EP11 interrupt source register
EP11 byte number register
EP11REQ
EP11BYT0
EP11 buffer area set register
EP11BUF
USBE
UCLKCON
bit 5
USBDIFE
bit 4
bit 3
bit 2
bit 1
bit 0
VREFE
VREFCON
TRONE
TRONCON
AD1E
WKUP
AD0E
USBADD0[6:0]
USBADD1[6:0]
FNUM[7:0]
RSME
RSM
SUSE
SUS
EP11E
EP11
EP10E
EP10
EP03E
EP03
EP02E
EP02
ADIDX
FNUM[10:8]
EP01E
EP00E
EP01
EP00
EPIDX[1:0]
(1) Endpoint 00
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
ERR00
BSRDY00
SETUP00
PID00[1:0]
BVAL00
CTENDE00
CTSTS00
CTEND00
BRDY00
BBYT00[3:0]
BADD00[4:0]
(2) Endpoint 01
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR01
ITMD01
SQCL01
DBLB01
ERR01
BSIZ01[1:0]
PID01[1:0]
B0VAL01
B1VAL01
B1RDY01
B0RDY01
B0BYT01[6:0]
B1BYT01[6:0]
MXPS01[6:0]
BADD01[4:0]
(3) Endpoint 02
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR02
ITMD02
SQCL02
DBLB02
ERR02
BSIZ02[1:0]
PID02[1:0]
B0VAL02
B1VAL02
B1RDY02
B0RDY02
B0BYT02[6:0]
B1BYT02[6:0]
MXPS02[6:0]
BADD02[4:0]
(4) Endpoint 03
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR03
ITMD03
SQCL03
DBLB03
ERR03
BSIZ03[1:0]
PID03[1:0]
B0VAL03
B1VAL03
B1RDY03
B0RDY03
B0BYT03[6:0]
B1BYT03[6:0]
MXPS03[6:0]
BADD03[4:0]
(5) Endpoint 10
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
ERR10
BSRDY10
SETUP10
PID10[1:0]
BVAL10
CTENDE10
CTSTS10
CTEND10
BRDY10
BBYT10[3:0]
BADD10[4:0]
(6) Endpoint 11
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
TYP11
DIR11
SQCL11
PID11[1:0]
B0VAL11
B0RDY11
B0BYT11
BADD11[4:0]
: Not used
Fig. 30 USB related registers
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 31 of 147
38K2 Group
USB Related Registers
The USB related registers are shown below.
b0
b7
USB control register (USBCON) [address 001016]
Bit symbol
WKUP
TRONCON
TRONE
VREFCON
VREFE
USBDIFE
UCLKCON
USBE
At reset
R W
H/W S/W
0 : Returning to BUS idle state by writing “1” first and 0
Remote wakeup bit
– O O
then “0”. (Remote wakeup signal)
1 : K-state output
0 : “L” output mode (valid in TRONE = “1”)
TrON output control bit
0
– O O
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
TrON output enable bit
0
– O O
1 : TrON port output enabled
USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
0
– O O
1 : Low current mode (valid in VREFE = “1”)
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
0
– O O
1 : USB reference voltage circuit operation enabled
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
0
– O O
1 : Upstream--port difference input circuit operation enabled
0 : External oscillating clock f(XIN)
USB clock select bit
0
– O O
1 : PLL circuit output clock (fVCO)
USB module operation enable bit 0 : USB module reset
0
– O O
1 : USB module operation enabled
Bit name
Function
–: State remaining
Fig. 31 Structure of USB control register
b0
b7
0
0 0
0 0 0
USB function/HUB enable register (USBAE) [address 001116]
Bit symbol
Bit name
AD0E
USB function enable bit
AD1E
USB HUB enable bit
b7:b2
Not used
Function
0: USB function address register invalidated
1: USB function address register validated
0: USB HUB address register invalidated
1: USB HUB address register validated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
–: State remaining
Fig. 32 Structure of USB function/HUB enable register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 32 of 147
38K2 Group
b0
b7
USB function address register (USBA0) [address 001216]
0
Bit symbol
Function
Bit name
USBADD0
[6:0]
USB function address bit
b7
Not used
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
–
–
O O
–: State remaining
Fig. 33 Structure of USB function address register
b0
b7
USB HUB address register (USBA1) [address 001316]
0
Bit symbol
Function
Bit name
USBADD1
[6:0]
USB HUB address bit
b7
Not used
In AD1E = “0”, this value changes after writing.
In AD1E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
–
–
O O
–: State remaining
Fig. 34 Structure of USB HUB address register
b0
b7
Frame number register Low (FNUML) [address 001416]
Bit symbol
FNUM
[7:0]
Function
Bit name
Frame number low bit
The frame number is updated at SOF reception.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
Fig. 35 Structure of Frame number register Low
b0
b7
0
0 0
0 0
Frame number register High (FNUMH) [address 001516]
Bit symbol
FNUM
[10:8]
b7:b3
Bit name
Function
Frame number high bit
The frame number is updated at SOF reception.
Not used
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
–
–
O O
–: State remaining
Fig. 36 Structure of Frame number register High
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 33 of 147
38K2 Group
b7
b0
USB interrupt source enable register (USBICON) [address 001616]
Bit symbol
SUSE
USB function/Endpoint 0 interrupt
enable bit
USB function/Endpoint 1 interrupt
enable bit
USB function/Endpoint 2 interrupt
enable bit
USB function/Endpoint 3 interrupt
enable bit
USB HUB/Endpoint 0 interrupt
enable bit
USB HUB/Endpoint 1 interrupt
enable bit
Suspend interrupt enable bit
RSME
Resume interrupt enable bit
EP00E
EP01E
EP02E
EP03E
EP10E
EP11E
Fig. 37 Structure of USB interrupt source enable register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Function
Bit name
page 34 of 147
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
38K2 Group
b7
b0
USB interrupt source register (USBIREQ) [address 001716]
Bit symbol
Bit name
EP00
USB function/Endpoint 0
interrupt bit
EP01
USB function/Endpoint 1
interrupt bit
EP02
USB function/Endpoint 2
interrupt bit
EP03
USB function/Endpoint 3
interrupt bit
EP10
USB HUB/Endpoint 0 interrupt
bit
EP11
USB HUB/Endpoint 1 interrupt
bit
SUS
Suspend interrupt bit
RSM
Resume interrupt bit
Fig.38 Structure of USB interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 35 of 147
At reset
R W
H/W S/W
This bit is set to “1” when any one of EP00 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP10 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP10 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP11 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP11 interrupt
source register to “0016”.
Writing to this bit causes no state change.
0 : No interrupt request issued
0
0 O O
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of Jstate, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes 0
0 O ✕
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Function
38K2 Group
b0
b7
0
0 0
0 0
Endpoint index register (USBINDEX) [address 001816]
Bit symbol
Bit name
EPIDX [1:0] Endpoint index bit
ADIDX
Address index bit
b7:b3
Not used
Function
b1 b0
0 0 : Endpoint 0
0 1 : Endpoint 1
1 0 : Endpoint 2
1 1 : Endpoint 3
0 : USB function
1 : USB HUB
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
–: State remaining
Fig. 39 Structure of Endpoint index register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 36 of 147
38K2 Group
(1) Endpoint 00
b0
b7
0
0
0
0 0
EP00 stage register (EP00STG) [address 001916]
0 0
Bit symbol
Function
Bit name
SETUP00
SETUP packet detection bit
b7:b1
Not used
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
Writing “1” to this bit causes no state change of the
status flags.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
1
1 O O
–
–
O O
–: State remaining
Fig. 40 Structure of EP00 stage register
b0
b7
0
0
0
0 0
EP00 control register 1 (EP00CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID00 [1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 41 Structure of EP00 control register 1
b0
b7
0
0
0 0
0 0
0
EP00 control register 2 (EP00CON2) [address 001B16]
Bit symbol
Bit name
BVAL00
Buffer enable bit
b7:b1
Not used
Function
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 42 Structure of EP00 control register 2
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 37 of 147
38K2 Group
b0
b7
0
0
0 0
0 0
EP00 control register 3 (EP00CON3) [address 001C16]
0
Bit symbol
CTENDE00 Control transfer completion
enable bit
b7:b1
Function
Bit name
Not used
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 43 Structure of EP00 control register 3
b7
0 0 0
b0
EP00 interrupt source register (EP00REQ) [address 001D16]
Bit symbol
BRDY00
CTEND00
CTSTS00
BSRDY00
ERR00
b7:b5
Bit name
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
1: Interrupt request issued
stage transition interrupt bit
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
USB function/Endpoint 0 SETUP 0: No interrupt request issued
1: Interrupt request issued
buffer ready interrupt bit
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
1: Interrupt request issued
interrupt bit
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
“0” is read when reading.
USB function/Endpoint 0 buffer
ready interrupt bit
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
–: State remaining
Fig. 44 Structure of EP00 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 38 of 147
38K2 Group
b0
b7
0
0 0
EP00 byte number register (EP00BYT) [address 001E16]
0
Bit symbol
BBYT00
[3:0]
b7:b4
Function
Bit name
Transmit/receive byte number bit OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
Not used
0 is read when reading.
At reset
R W
H/W S/W
0
— O O
—
—
O O
—: State remaining
Fig. 45 Structure of EP00 byte number register
b0
b7
0
0 0
EP00 buffer area set register (EP00BUF) [address 0FED16]
Bit symbol
Bit name
BADD00
[4:0]
EP00 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP00’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 46 Structure of EP00 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 39 of 147
38K2 Group
(2) Endpoint 01
b0
b7
EP01 set register (EP01CFG) [address 001916]
Bit symbol
BSIZ01
[1:0]
DBLB01
SQCL01
ITMD01
DIR01
TYP01
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of 0
– O O
buffer 1 area, using a relative value for the beginning
bit
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 47 Structure of EP01 set register
b0
b7
0 0 0
0
0
0
EP01 control register 1 (EP01CON1) [address 001A16]
Bit symbol
Bit name
PID01
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 48 Structure of EP01 control register 1
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 40 of 147
38K2 Group
b0
b7
0
0
0 0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16]
Bit symbol
Bit name
B0VAL01
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 49 Structure of EP01 control register 2
b0
b7
0 0 0 0
EP01 control register 3 (EP01CON3) [address 001C16]
0 0 0
Bit symbol
Bit name
B1VAL01
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig.50 Structure of EP01 control register 3
b0
b7
0 0 0 0
0
EP01 interrupt source register (EP01REQ) [address 001D16]
Bit symbol
B0RDY01
B1RDY01
ERR01
b7:b3
Bit name
USB function/Endpoint 1 buffer 0 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 buffer 1 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 error
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 51 Structure of EP01 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Function
page 41 of 147
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
38K2 Group
b7
b0
EP01 byte number register 0 (EP01BYT0) [address 001E16]
0
Bit symbol
B0BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode : The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 52 Structure of EP01 byte number register 0
b7
b0
EP01 byte number register 1 (EP01BYT1) [address 001F16]
0
Bit symbol
B1BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 53 Structure of EP01 byte number register 1
b7
0
b0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16]
Bit symbol
MXPS01
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 54 Structure of EP01 MAX. packet size register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 42 of 147
38K2 Group
b0
b7
0 0
0
EP01 buffer area set register (EP01BUF) [address 0FED16]
Bit symbol
Bit name
BADD01
[4:0]
EP01 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP01’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 55 Structure of EP01 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 43 of 147
38K2 Group
(3) Endpoint 02
b0
b7
EP02 set register (EP02CFG) [address 001916]
Bit symbol
BSIZ02
[1:0]
DBLB02
SQCL02
ITMD02
DIR02
TYP02
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 56 Structure of EP02 set register
b0
b7
0 0
0
0
0 0
EP02 control register 1 (EP02CON1) [address 001A16]
Bit symbol
Bit name
PID02
[1: 0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 57 Structure of EP02 control register 1
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 44 of 147
38K2 Group
b0
b7
0
0
0
0 0
0
EP02 control register 2 (EP02CON2) [address 001B16]
0
Bit symbol
Bit name
B0VAL02
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 58 Structure of EP02 control register 2
b0
b7
0
0
0
0 0
0
0
EP02 control register 3 (EP02CON3) [address 001C16]
Bit symbol
Bit name
B1VAL02
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 59 Structure of EP02 control register 3
b0
b7
0
0
0
0
0
EP02 interrupt source register (EP02REQ) [address 001D16]
Bit symbol
B0RDY02
B1RDY02
ERR02
b7 to b3
Bit name
USB function/Endpoint 2 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 60 Structure of EP02 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Function
page 45 of 147
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
38K2 Group
b7
b0
EP02 byte number register 0 (EP02BYT0) [address 001E16]
0
Bit symbol
B0BYT02
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 61 Structure of EP02 byte number register 0
b7
b0
EP02 byte number register 1 (EP02BYT1) [address 001F16]
0
Bit symbol
B1BYT02
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 62 Structure of EP02 byte number register 1
b7
0
b0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16]
Bit symbol
MXPS02
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 63 Structure of EP02 MAX. packet size register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 46 of 147
38K2 Group
b0
b7
0 0
0
EP02 buffer area set register (EP02BUF) [address 0FED16]
Bit symbol
Bit name
BADD02
[4:0]
EP02 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP02’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 64 Structure of EP02 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 47 of 147
38K2 Group
(4) Endpoint 03
b0
b7
EP03 set register (EP03CFG) [address 001916]
Bit symbol
BSIZ03
[1:0]
DBLB03
SQCL03
ITMD03
DIR03
TYP03
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bit
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 65 Structure of EP03 set register
b0
b7
0 0 0
0
0
0
EP03 control register 1 (EP03CON1) [address 001A16]
Bit symbol
Bit name
PID03
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 66 Structure of EP03 control register 1
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 48 of 147
38K2 Group
b0
b7
0
0
0
0 0
0
0
EP03 control register 2 (EP03CON2) [address 001B16]
Bit symbol
Bit name
B0VAL03
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 67 Structure of EP03 control register 2
b0
b7
0 0 0 0
EP03 control register 3 (EP03CON3) [address 001C16]
0 0 0
Bit symbol
Bit name
B1VAL03
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 68 Structure of EP03 control register 3
b0
b7
0 0 0 0
0
EP03 interrupt source register (EP03REQ) [address 001D16]
Bit symbol
B0RDY03
B1RDY03
ERR03
b7:b3
Bit name
USB function/Endpoint 3 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 69 Structure of EP03 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Function
page 49 of 147
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
38K2 Group
b7
b0
EP03 byte number register 0 (EP03BYT0) [address 001E16]
0
Bit symbol
B0BYT03
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Not used
At reset
R W
H/W S/W
0
– O O
Function
Bit name
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
0
–
O ✕
–
–
O O
–: State remaining
Fig. 70 Structure of EP03 byte number register 0
b7
b0
EP03 byte number register 1 (EP03BYT1) [address 001F16]
0
Bit symbol
B1BYT03
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 71 Structure of EP03 byte number register 1
b7
0
b0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16]
Bit symbol
MXPS03
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 72 Structure of EP03 MAX. packet size register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 50 of 147
38K2 Group
b0
b7
0 0
0
EP03 buffer area set register (EP03BUF) [address 0FED16]
Bit symbol
Bit name
BADD03
[4:0]
EP03 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP03’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 73 Structure of EP03 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 51 of 147
38K2 Group
(5) Endpoint 10
b0
b7
0
0
0
0 0
EP10 stage register (EP10STG) [address 001916]
0 0
Bit symbol
Function
Bit name
SETUP10
SETUP packet detection bit
b7:b1
Not used
This bit is set to “1” at reception of SETUP packet.
Writing “0” clears this bit if the next SETUP token does
not occur.
Writing “1” causes no state change of the status flags.
This bit change is not for an interrupt source.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
1
1 O O
–
–
O O
–: State remaining
Fig. 74 Structure of EP10 stage register
b0
b7
0
0
0
0 0
EP10 control register 1 (EP10CON1) [address 001A16]
0
Bit symbol
PID10 [1:0]
Response PID bit
b7:b2
Not used
At reset
R W
H/W S/W
0
– O O
Function
Bit name
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
–
–
O O
–: State remaining
Fig. 75 Structure of EP10 control register 1
b0
b7
0
0
0 0
0 0
0
EP10 control register 2 (EP10CON2) [address 001B16]
Bit symbol
Bit name
BVAL10
Buffer enable bit
b7:b1
Not used
Function
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible to
read from/write to a buffer.) (Valid in PID10 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 76 Structure of EP10 control register 2
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 52 of 147
38K2 Group
b0
b7
0
0
0 0
0 0
EP10 control register 3 (EP10CON3) [address 001C16]
0
Bit symbol
CTENDE10 Control transfer completion
enable bit
b7:b1
Function
Bit name
Not used
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (Valid in PID10 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 77 Structure of EP10 control register 3
b7
0 0 0
b0
EP10 interrupt source register (EP10REQ) [address 001D16]
Bit symbol
Bit name
BRDY10
USB HUB/Endpoint 10 buffer
ready interrupt bit
CTEND10
USB HUB/Endpoint 10 control
transfer completion interrupt bit
CTSTS10
USB HUB/Endpoint 10 status
stage transition interrupt bit
BSRDY10
USB HUB/Endpoint 10 SETUP
buffer ready interrupt bit
ERR10
USB HUB/Endpoint 10 error
interrupt bit
b7:b5
Not used
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE10 = “0” (control transfer completion
disabled) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB HUB/Endpoint 10.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
–: State remaining
Fig. 78 Structure of EP10 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 53 of 147
38K2 Group
b0
b7
0
0 0
EP10 byte number register (EP10BYT) [address 001E16]
0
Bit symbol
BBYT10
[3:0]
b7:b4
Function
Bit name
Transmit/receive byte number bit OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
Not used
0 is read when reading.
At reset
R W
H/W S/W
0
— O O
—
—
O O
—: State remaining
Fig. 79 Structure of EP10 byte number register
b0
b7
0
0 0
EP10 buffer area set register (EP10BUF) [address 0FED16]
Bit symbol
Bit name
BADD10
[4:0]
EP10 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP10’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 80 Structure of EP10 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 54 of 147
38K2 Group
(6) Endpoint 11
b0
b7
0
0
0
0 0 EP11 set register (EP11CFG) [address 001916]
Bit symbol
Function
Bit name
b2:b0
Not used
SQCL11
Sequence toggle bit clear bit
b4
Not used
DIR11
Transfer direction bit
b6
Not used
TYP11
Transfer type bite
Write “0” when writing.
“0” is read when reading.
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Write “0” when writing.
“0” is read when reading.
0 : IN transfer disabled
1 : IN (Data is transmitted to the host.)
Write “0” when writing.
“0” is read when reading.
0 : Transfer disabled
1 : Interrupt transfer
At reset
R W
H/W S/W
–
– O O
0
–
–
–
O O
0
–
O O
–
–
O O
0
–
O O
–: State remaining
Fig. 81 Structure of EP11 set register
b0
b7
0 0 0
0
0
EP11 control register 1 (EP11CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID11
[1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (NAK, DATA0, DATA1)
1 X : STALL
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 82 Structure of EP11 control register 1
b0
b7
0
0
0
0 0
0
0
EP11 control register 2 (EP11CON2) [address 001B16]
Bit symbol
Bit name
B0VAL11
Buffer 0 status bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
This bit set to “1” shows the transmitting data is in a set 0
state (SIE is possible to read).
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 83 Structure of EP11 control register 2
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 55 of 147
38K2 Group
b0
b7
0 0 0
EP11 interrupt source register (EP11REQ) [address 001D16]
0 0 0 0
Bit symbol
Function
Bit name
B0RDY11
USB HUB/Endpoint 1 buffer 0
ready interrupt bit
b7:b1
Not used
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
–
–
O O
–: State remaining
Fig. 84 Structure of EP11 interrupt source register
b0
b7
0
0
0
0 0
0
EP11 byte number register (EP11BYT0) [address 001E16]
0
Bit symbol
Function
Bit name
B0BYT11
Transmit byte number bit
IN : Set the transmitting byte number.
b7:b1
Not used
Write 0 when writing.
0 is read when reading.
At reset
R W
H/W S/W
0
— O O
—
—
O O
—: State remaining
Fig. 85 Structure of EP11 byte number register
b0
b7
0
0 0
EP11 buffer area set register (EP11BUF) [address 0FED16]
Bit symbol
Bit name
BADD11
[4:0]
EP11 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP11’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 86 Structure of EP11 buffer area set register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 56 of 147
38K2 Group
HUB FUNCTION
The 38K2 Group has a HUB Function Control Circuit (HUBFCC)
that offers easy implementation of USB-hub functions (signal repeat and bus state detection). This circuit is in compliance with
USB Specification Version 2.0 Full-Speed/Low-Speed Transfer
Modes (12 Mbps/1.5 Mbps, equivalent to Version 1.1).
The HUBFCC operates with two external down-ports and one internal down-port, which is utilized by the USB addresses of the
built-in peripherals, enabling management of a total of three downports independently.
A dedicated circuit automatically performs the bus state change
detection and error detection needed for the sequence management of the hub repeater circuit, data repeat function, and
down-port status management. This dedicated control circuit ensures the user easy development of a program or timing design.
Each down-port register can be controlled by USB commands using USB addresses for HUB functions or detecting changes in the
bus state of down-ports. The HUBFCC is also equipped with a remote wakeup signal transfer function for use during global resume
as other special signals management. The HUBFCC generates an
interrupt to the CPU when detecting a down-port state change (1
vector, 10 sources).
The flexibility of the indispensable yet wide-ranging HUBFCC
structure and an external interrupt function and I/O ports implemented in the standard features of this MCU enable the power
supply management essential for USB-HUB functions and also allow users to easily and effortlessly configure their optimum
system.
38K2 Group
CPU
USB
Up-port
(USB host)
HUB
Internal downport
External down-port
(USB device)
Fig. 87 HUB functions
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 57 of 147
External down-port
(USB device)
38K2 Group
HUB Function Control Circuit Block Diagram
The HUB function control circuit, as show in the diagram below,
consists of the following blocks.
(1) HUB repeater block
(2) Down-port control block
(3) CPU interface block (CIF)
USB transceiver
HUB Function Control Circuit
CIF
CPU
HUB repeater block
D0+
D0-
Down-port control block
USB down-port 1
transceiver
D1+
D1-
USB Down-port 2
transceiver
D2+
D2-
Fig. 88 HUB function control circuit block diagram
(1) HUB repeater block
The HUB repeater block, consisting of the circuits listed below,
processes the HUB repeater function sequence. The HUB repeater is ready for operation after enabling the USB module
(USBE = “1”).
•Repeater circuit (detects SOP/EOP signal)
•Frame-time circuit (synchronizes to SOF signal and manages
frames in 1 ms)
•Receiver circuit (manages up-port states)
•Transmitter circuit (controls up-port outputs)
(2) Down-port control block
The down-port control block, consisting of the circuits listed below,
performs down-port controls under supervision of the HUB repeater state operation.
•Down-port sequencer circuit
•Down-port state change detect circuit
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 58 of 147
(3) CPU interface block (CIF)
The CPU interface block performs the following processes.
•Control of repeater/down-port states through registers.
•Generates interrupt signal
•Controls internal bus interface
38K2 Group
USB Down-port Peripheral Circuit Setting
The USB down-port peripheral circuits can be set with the downstream port control register (address 0FF916). Figures 89 and 90
show the circuit block diagrams.
Low
Speed
PCON11
PCON10
D1+
Full
Speed
PCON11
PCON11
PCON10
PCON10
27 Ω
15 kΩ
+
-
HUB Module
PCON11
PCON11
PCON10
D1-
Full
Speed
27 Ω
15 kΩ
PCON11
PCON10
Low
Speed
PCON11
PCON10
Fig. 89 Block diagram of USB down-port peripheral circuits (D1+, D1-)
Low
Speed
PCON21
PCON20
D2+
Full
Speed
27 Ω
15 kΩ
PCON21
PCON20
PCON21
PCON20
+
-
HUB Module
PCON21
PCON21
PCON20
Full
Speed
Low
Speed
PCON21
PCON20
Fig. 90 Block diagram of USB down-port peripheral circuits (D2+, D2-)
page 59 of 147
27 Ω
15 kΩ
PCON21
PCON20
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
D2-
38K2 Group
HUB Interrupt Function
The HUB function control circuit has one interrupt request consisting of 10 interrupt sources each of which can be determined
through the interrupt source register. Table 8 shows the HUB interrupt sources.
Table 8 HUB interrupt sources
Interrupt request bit
(IREQ2: Address 003D16)
USB HUB
HUB interrupt bit
(HUBIREQ: Address 002916)
DP1
DP2
[DPXREG1]
[HUBIREQ]
Interrupt source
At HUB down-port 1 state change detected:
•Disconnected state detected
•Connected state detected
•Port error state detected
•Resume signal detected
•Bus state change detected
At HUB down-port 2 state change detected:
•Disconnected state detected
•Connected state detected
•Port error state detected
•Resume signal detected
•Bus state change detected
[HUBICON]
[DP1REQ]
PTDIS1
PTCON1
PTERR1
DP1E
DP1
PTRSM1
PTCHG1
[DP2REQ]
PTDIS2
DP2E
PTCON2
PTERR2
PTRSM2
PTCHG2
Fig. 91 USB HUB interrupt control
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 60 of 147
DP2
USB HUB
interrupt request
38K2 Group
HUB Register List
The HUB register list is shown below.
Address
002816
002916
002A16
002B16
002C16
002D16
Register Name
SYMBOL
USB SFR
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DP2E
DP2
DP1E
DP1
DPIDX
PTERR1
DSSUSP1
PTCON1
DSPTEN1
D1PLUS
PTDIS1
DSCONN1
D1MINUS
PTERR2
DSSUSP2
PTCON2
DSPTEN2
D2PLUS
PTDIS2
DSCONN2
D2MINUS
HRWUE
HUB interrupt source enable register
HUB interrupt source register
HUB downstream port index register
HUB port field register 1
HUB port field register 2
HUB port field register 3
HUBICON
HUBIREQ
HUBINDEX
DPXREG1
DPXREG2
DPXREG3
DP1 interrupt source register
DP1 control register
DP1 status register
DP1REQ
DP1CON
DP1STS
DSLSPD1
DSRMOD1
DSRSMO1
PTCHG1
DSRSTO1
PTRSM1
DSDETE1
002B16
002C16
002D16
DP2 interrupt source register
DP2 control register
DP2 status register
DP2REQ
DP2CON
DP2STS
DSLSPD2
DSRMOD2
DSRSMO2
PTCHG2
DSRSTO2
PTRSM2
DSDETE2
0FF916
Downstream port control register
DPCTL
HRWU
(1) HUB port 1
002B16
002C16
002D16
(2) HUB port 2
PCON2[1:0]
PCON1[1:0]
: Not used
Fig. 92 HUB related registers
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 61 of 147
38K2 Group
HUB Related Registers
The HUB related registers are shown below.
b0
b7
0
0 0
HUB interrupt source enable register (HUBICON) [address 002816]
0 0
Bit symbol
DP1E
DP2E
b6:b2
HRWUE
Function
Bit name
HUB downstream port 1 interrupt
enable bit
HUB downstream port 2 interrupt
enable bit
Not used
HUB upstream port remotewakeup output enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Write “0” when writing.
“0” is read when reading.
0 : Disabled
1 : Enabled
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
0
–
O O
–: State remaining
Fig. 93 Structure of HUB interrupt source enable register
b0
b7
0
0 0 0
0
HUB interrupt source register (HUBIREQ) [address 002916]
Bit symbol
Bit name
DP1
HUB downstream port 1
interrupt bit
DP2
HUB downstream port 1
interrupt bit
b6:b2
Not used
HRWU
HUB upstream port remote
-wakeup output enable bit
At reset
R W
H/W S/W
– O ✕
This bit is set to “1” when any one of DP1 interrupt 0
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP1 interrupt
source register to “0016”.
Writing to this bit causes no state change.
– O ✕
This bit is set to “1” when any one of DP2 interrupt 0
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP2 interrupt
source register to “0016”.
Writing to this bit causes no state change.
–
– O O
Write “0” when writing.
“0” is read when reading.
0
– O O
0 : Remote-wakeup being not output
1 : Remote-wakeup being output
This bit change is not for a interrupt source.
When detecting 2.5 µs or more of K-signal on a
downstream port in Hub-suspended state, K-signal is
output on from a upstream port and this bit is
simultaneously set to “1”.
“0” can be set by software, but “1” cannot be set.
Function
–: State remaining
Fig. 94 Structure of HUB interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 62 of 147
38K2 Group
b0
b7
0
0
0 0
0 0
0
HUB downstream port index register (HUBINDEX) [address 002A16]
Bit symbol
Bit name
DPIDX
HUB downstream port index bit
b7:b1
Not used
Function
0 : HUB downstream port 1
1 : HUB downstream port 2
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 95 Structure of HUB downstream port index register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 63 of 147
38K2 Group
(1) Downstream port 1
b0
b7
0
0 0
DP1 interrupt source register (DP1REQ) [address 002B16]
Bit symbol
PTDIS1
PTCON1
PTERR1
PTRSM1
PTCHG1
b7:b5
Bit name
Downstream port 1 disconnect
detection interrupt bit
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 1 in
DSCONN1 = “1”.
“0” can be set by software, but “1” cannot be set.
Downstream port 1 connect
0: No interrupt request issued
detection interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 1 in DSCONN1 = “0”.
“0” can be set by software, but “1” cannot be set.
Downstream port 1 port error
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 1.
“0” can be set by software, but “1” cannot be set.
Downstream port 1 resume
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 1 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
Downstream port 1 bus-change 0: No interrupt request issued
detection interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 1 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
At reset R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 96 Structure of DP1 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 64 of 147
38K2 Group
b0
b7
DP1 control register (DP1CON) [address 002C16]
Bit symbol
DSCONN1
DSPTEN1
DSSUSP1
DSDETE1
DSRSTO1
DSRSMO1
DSRMOD1
DSLSPD1
Function
Bit name
Downstream port 1 connect bit
0 : Disconnect ; PTCON1 interrupt enabled
1 : Connect ; PTDIS1 interrupt enabled
Downstream port 1 enable bit
0 : Downstream port 1 disabled
1 : Downstream port 1 enabled ; This bit is cleared when
an interrupt of PTDIS1 or PTERR1 is generated.
Downstream port 1 suspend bit 0 : No port suspended
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS1 or PTRSM1 is generated.
Downstream port 1 connect0 : Connect/disconnect-state detection disabled ; PTCON1
state detection enable bit
and PTDIS1 interrupts disabled
1 : Connect/disconnect-state detection enabled ; This bit
is cleared when an interrupt of PTCON1, PTDIS1 or
PTERR1 is generated.
Downstream port 1 SE0 signal 0 : Being not output
transmit bit
1 : SE0 signal being output
Downstream port 1 resume
0 : Being not output
signal transmit bit
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
Downstream port 1 bus-state
0 : Mode where a downstream port 1 bus-state is read,
read mode control bit
using RD signal
1 : Mode where a downstream port 1 bus-state is read,
using EOF2 signal (internal signal)
Downstream port 1 USB transfer 0 : Full-speed mode (12MHz)
1 : Low-speed mode (1.5 MHz)
At reset
R W
H/W S/W
– O O
0
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
–: State remaining
Fig. 97 Structure of DP1 control register
b0
b7
0
0
0 0
0 0
DP1 status register (DP1STS) [address 002D16]
Bit symbol
Bit name
D1MINUS
D1- signal bit
D1PLUS
D1+ signal bit
b7:b2
Not used
At reset
R W
H/W S/W
InInO
✕
In DSRMOD1 = “0”, a downstream port 1 bus-state is
definite definite
read, using RD signal.
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
In- O ✕
In DSRMOD1 = “0”, a downstream port 1 bus-state is Indefinite definite
read, using RD signal.
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
–
–
O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 98 Structure of DP1 status register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 65 of 147
38K2 Group
(2) Downstream port 2
b0
b7
0
0 0
DP2 interrupt source register (DP2REQ) [address 002B16]
Bit symbol
PTDIS2
PTCON2
PTERR2
PTRSM2
PTCHG2
b7:b5
Bit name
Downstream port 2 disconnect
detection interrupt bit
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 2 in
DSCONN2 = “1”.
“0” can be set by software, but “1” cannot be set.
Downstream port 2 connect
0: No interrupt request issued
detection interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 2 in DSCONN2 = “0”.
“0” can be set by software, but “1” cannot be set.
Downstream port 2 port error
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 2.
“0” can be set by software, but “1” cannot be set.
Downstream port 2 resume
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 2 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
Downstream port 2 bus-change 0: No interrupt request issued
detection interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 2 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
At reset R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 99 Structure of DP2 interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 66 of 147
38K2 Group
b0
b7
DP2 control register (DP2CON) [address 002C16]
Bit symbol
DSCONN2
DSPTEN2
DSSUSP2
DSDETE2
DSRSTO2
DSRSMO2
DSRMOD2
DSLSPD2
Function
Bit name
Downstream port 2 connect bit
0 : Disconnect ; PTCON2 interrupt enabled
1 : Connect ; PTDIS2 interrupt enabled
Downstream port 2 enable bit
0 : Downstream port 2 disabled
1 : Downstream port 2 enabled ; This bit is cleared when
an interrupt of PTDIS2 or PTERR2 is generated.
Downstream port 2 suspend bit 0 : No port suspended
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS2 or PTRSM2 is generated.
Downstream port 2 connect0 : Connect-state detection disabled ; PTCON2 and PTDIS2
state detection enable bit
interrupts disabled
1 : Connect-state detection enabled ; This bit is cleared when an
interrupt of PTCON2, PTDIS2 or PTERR2 is generated.
Downstream port 2 SE0 signal 0 : Being not output
transmit bit
1 : SE0 signal being output
Downstream port 2 resume
0 : Being not output
signal transmit bit
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
Downstream port 2 bus-state
0 : Mode where a downstream port 2 bus-state is read,
read mode control bit
using RD signal
1 : Mode where a downstream port 2 bus-state is read,
using EOF2 signal (internal signal)
Downstream port 2 USB transfer 0 : Full-speed mode (12MHz)
speed select bit
1 : Low-speed mode (1.5 MHz)
At reset
R W
H/W S/W
– O O
0
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
0
–
O O
–: State remaining
Fig. 100 Structure of DP2 control register
b0
b7
0
0
0 0
0 0
DP2 status register (DP2STS) [address 002D16]
Bit symbol
Bit name
D2MINUS
D2- signal bit
D2PLUS
D2+ signal bit
b7:b2
Not used
At reset
R W
H/W S/W
In- O ✕
In DSRMOD2 = “0”, a downstream port 2 bus-state is Indefinite definite
read, using RD signal.
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
In- O ✕
In DSRMOD2 = “0”, a downstream port 2 bus-state is Indefinite definite
read, using RD signal.
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
–
–
O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 101 Structure of DP2 status register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 67 of 147
38K2 Group
b0
b7
0
0
0 0
Downstream port control register (DPCTL) [address 0FF916]
Bit symbol
Bit name
PCON1
[1:0]
Downstream port 1 function
select bit
PCON2
[1:0]
Downstream port 2 function
select bit
b7:b4
Not used
Function
b1b0
0 0 : USB port (D1-, D1+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D1-, D1+),
USB difference amplifier OFF
1 0 : Full-speed port (D1-, D1+),
USB difference amplifier ON
1 1 : Low-speed port (D1-, D1+),
USB difference amplifier ON
b3b2
0 0 : USB port (D2-, D2+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D2-, D2+),
USB difference amplifier OFF
1 0 : Full-speed port (D2-, D2+),
USB difference amplifier ON
1 1 : Low-speed port (D2-, D2+),
USB difference amplifier ON
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
– O O
0
0
–
O O
–
–
O O
–: State remaining
Fig. 102 Structure of Downstream port control register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 68 of 147
38K2 Group
EXTERNAL BUS INTERFACE (EXB)
The external bus interface (EXB) controls the data transfer between the external MCU and the 38K2 group’s CPU or its
memory (multichannel RAM). The external bus interface is shown
below.
38K2 group
CPU
Program ROM
Peripheral functions
External MCU
CPU channel
[Interrupt type]
External bus interface
(EXB)
Multichannel RAM
USB
USB bus
(USB host)
Memory channel
[Direct RAM access type]
Fig. 103 External bus interface
●CPU channel
It is a data transfer course by the interrupt processing between the
external MCU and the 38K2 group’s CPU.
●Memory channel
It is a data transfer course by direct RAM access of the memory
channel controller between the external MCU and the 38K2
group’s memory (multichannel RAM)
●Data transfer of memory channel
When the burst mode is selected with the burst bit of the memory
channel operation mode register, data transfer can be carried out
at the highest speed. After the external bus interface detects a rise
of external read signal/write signal and synchronizes it with the internal clock φ, it completes the data transfer between the transmit/
receive buffer and the multichannel RAM in two clocks.
However, the waiting time of two clocks at a maximum is generated to access the multichannel RAM in USB being operating
because the USB has priority to access.
Therefore, it is necessary to set up the access interval which fills
the following timing with the external MCU bus side.
In φ = 8 MHz, data transfer at about 2 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1.3 Mbytes/second.
In φ = 6 MHz, data transfer at about 1.5 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1 Mbytes/second.
Address
CS, RD, WR,
DMA acknowledge
Access cycle time from externals:
•3 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB inactive
•5 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB active
Fig. 104 Data transfer timing of memory channel
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 69 of 147
38K2 Group
EXB Pin Assignment
The external bus interface (EXB) pins are shown bellow.
The 38K2 group can transmit/receive a data to/from an external
MCU, using the following signals:
•Control input signal ................ 4 (ExCS, ExA0, ExRD, ExWR)
•Data input/output pin .............. 8 (DQ0 to DQ7)
•Interrupt output signal ............ 1 (ExINT)
Additionally, the DMA interface signal and the buffer status read
select signal of 38K2 group can be set up per one by the program.
•Control input signal ................ 3 (ExTC, ExDACK, ExRD, ExA1)
•Interrupt output signal ............ 1 (ExDREQ)
38K2 group
External bus interface
(EXB)
External pins
External chip select
External address
External read
External write
External data
External interrupt
8
P34/ExCS [ L ]
P37/ExA0 [address]
P36/ExRD [ L ]
P35/ExWR [ L ]
P10/DQ0/AN0—P17/DQ7/AN7 [data]
P33/ExINT [ L ]
DMA request
Terminal count
DMA acknowledge
P40/ExDREQ/RxD [ L ]
P42/ExTC/SCLK [ L ]
P41/ExDACK/TxD [ L ]
Status read select
P43/ExA1/SRDY [ H ]
: Functions as normal ports
just after reset.
Fig. 105 External bus interface (EXB) pin assignment
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 70 of 147
CPU
Multichannel RAM
38K2 Group
EXB Block Diagram
The block diagram of external bus interface (EXB) is shown below.
The external bus interface (EXB) consists of:
(1) External I/O interface part
(2) CPU interface part
(3) Internal memory interface part
(4) Transmit/Receive data buffer part
External I/O interface
CPU interface
Configuration
signal
Index register
External I/O
configuration
register
EXB interrupt
source enable register
Cch_WR
External MCU bus
Cch_RD
P34/ExCS
TxB_RDY
CPU channel
controller
Decoder data selector
RxB_RDY
Command decoder
P37/ExA0
P36/ExRD
P35/ExWR
Memory channel
control
Mch_RD
Mch_WR
Mch_TC
P41/ExDACK/TxD
P42/ExTC/SCLK
mRX_enb
mTX_enb
Memory channel
status
Internal memory
interface
Memory channel
operation mode register
P43/ExA1/SRDY
Memory address
Output selector
Memory address
counter
P40/ExDREQ/RxD
End address register
Mch_req
FIFO_stt
Request acknowledge
Memory channel
controller
MRDsel
Memory channel
transmit buffer control
stt_sel
Buf_WR
ExOE
Transmit/Receive data
buffer
Memory read data
P10/DQ0/AN0–
P17/DQ7/AN7
Transmit buffer register
Memory write data
Receive buffer register
: Functions as normal ports just after reset.
Fig. 106 Block diagram of external bus interface (EXB)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 71 of 147
Multichannel RAM
P33/ExINT
38K2 Group
(1) External I/O Interface Part
(2) CPU Interface Part
The external I/O interface part consists of a command decoder
and an output selector. A command decoder generates the following signals to each unit.
The CPU interface part consists of the decoder/data selector of
the CPU channel, the CPU write register and CPU channel controller
●CPU interface part
•CPU channel read (Cch_RD)
•CPU channel write (Cch_WR)
●Decoder/data selector of CPU channel
A write operation to the CPU register is performed by generating a
write signal for each register with an address decode signal and a
write signal.
A read operation from the CPU register is performed by generating an output enable signal of the internal data bus with an module
select signal and a read signal and generating a select signal for
each register with an address decode signal.
●Internal memory interface part
•Memory channel read (Mch_RD)
•Memory channel write (Mch_WR)
•Memory channel terminal count (Mch_TC)
●Transmit/receive data buffer part
•Buffer write (Buf_WR)
●External I/O interface part
•Status selection (stt_sel)
•Output enable (ExOE)
Access to the CPU channel can be controlled only by setup of
external signals.
Access to the memory channel can be controlled by the value of
the external I/O configuration register and the state (mRX_enb,
mTX_enb signals) of the internal memory interface part.
The output selector has the function which selects from the state
of CPU channel (TxB_RDY and RxD_RDY) and the state of
memory channel (Mch_req) as the signal assigned to P3 3 /
ExINT pin and P40/ExDREQ/RxD pin.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 72 of 147
●CPU write register
There are three CPU write registers as follows:
•EXB interrupt source enable register
•Index register
•External I/O configuration register
The EXB interrupt source register is a read-only register.
A status signal of the CPU channel controller and a status signal
of the memory channel controller in the internal memory interface
part are generated.
●CPU channel controller
The CPU channel controller generates the following signals, using
bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source enable register.
•Memory channel transmitting buffer control signal (MRD_sel),
generated in the internal memory interface part
•CPU channel command signal (Cch_RD, Cch_WR), generated
in the external I/O interface part
•Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, generated with read/write signals from the CPU channel
38K2 Group
(3) Internal Memory Interface Part
(5) External Pin
The internal memory interface part consists of the CPU register
and the memory channel controller.
The external bus interface has the following pins to connect with
an external MCU bus.
•Chip select ........................... P34/ExCS
•Address ................................ P37/ExA0
•Data ...................................... P10/DQ0/AN0 to P17/DQ7/AN7
•Read .................................... P36/ExRD
•Write ..................................... P35/ExWR
•Interrupt request .................. P33/ExINT
●CPU register
The CPU register consists of the follows:
•Memory channel operation mode register
•Memory address counter
•End address register
The CPU can set the beginning address into the memory address
counter when the memory channel operation enable bit
(MC_ENB) of EXB interrupt source enable register is “0”. When
this bit is “1”, the write operation from the CPU is invalid and each
access from the external bus causes count-up operation.
●Memory channel controller
The CPU register consists of the follows:
•Main sequencer
•Internal memory request signal generating circuit
•External memory channel request signal generating circuit
•Address end detection circuit
•Terminal end input processing circuit
(4) Transmit/Receive Data Buffer Part
The transmit/receive data buffer part consists of the 8-bit transmit
buffer register (TXBUF) and the 8-bit receive buffer register
(RXBUF).
Both CPU channel and memory channel use the same transmit
buffer register/receive buffer register to transfer a data to an external MCU bus.
It also has the following pins to connect with an external DMAC.
Each pin can be programmed for an ordinary port function or a
DMA interface pin function.
•DMA request ........................ P40/ExDREQ/RxD
•DMA acknowledgment ......... P41/ExDACK/TxD
•Terminal count ..................... P42/ExTC/SCLK
It also has the status read select pin (P43/ExA1/SRDY pin) to confirm a ready status of the data buffer from an external MCU bus
This pin functions as a port just after reset. The status read select
function can be set by a program.
•Status read select ................ P43/ExA1/SRDY
●CPU channel: Communication with 38K2 group CPU
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “H”, the interrupt is generated and
the 38K2 group CPU can confirm its access. The 38K2 group CPU
judges the interrupt source and it starts a data transmission/reception with an external MCU bus.
●Memory channel: Communication with 38K2 group memory
multichannel RAM
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “L”, access to the multichannel RAM
is performed. Then an address of the multichannel RAM is made
by the external bus interface and it is increased at each access
completion. Consequently, FIFO access is performed.
Even if a read/write operation is performed in DACK = “L” instead
of ExCS = “L” and ExA0 = “L”, FIFO access to the multichannel
RAM is performed.
The beginning address and the end address must be set by the
CPU in advance.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 73 of 147
38K2 Group
●P33/ExINT pin
Any one of the following signals for this pin can be selected:
•TxB_RDY (transmit buffer ready) output
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Either TxB_RDY or RxB_RDY is normally selected. The memory
channel request is for an access request signal to the memory
channel.
In a small system, a data transfer processing to the internal
memory is performed in the interrupt routine. According to that
situation, the 38K2 group has the function automatically to switch
an interrupt factor attached on the interrupt pin by program.
●P40/ExDREQ/RxD pin
This pin is a port at the initial state. Which signal can be set by
program.
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Mch_req of DMAC is normally selected. The output method of the
memory channel request signal depends on the burst bit (BURST)
of memory channel operation mode register. When the burst bit is
“0”, this signal is periodically output at each 1-byte transfer. (See
Figures 124 and 127.)
When the burst bit is “1”, this signal is continuously output while
the memory address counter is counting from the beginning address to the end address (See Figures 125 and 128.)
●P41/ExDACK/TxD pin
This pin is a port at the initial state. The DMA acknowledge signal
can be set by program.
The DMA acknowledge signal DACK = “L” is the same state as
that of CS = “L” and A0 = “L”. Access to multichannel RAM is
started by a rise of read signal or write signal which is set during
this term.
Note: If the DMA acknowledge signal and the chip select signal
are simultaneously active (DACK = “L” and CS = “L”), also
set the address signal A0 to “L”. If A0 is “H”, the memory
channel and the CPU channel are activated simultaneously
and it might cause some error.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 74 of 147
●P42/ExTC/SCLK pin
This pin is a port at the initial state. The terminal count signal can
be set by program.
If the terminal count signal is set at one bus cycle while a memory
channel operation write is being performed, the 38K2 group confirms that its bus cycle is the write cycle of the last data and sets
the memory channel status bits to “112”, and the interrupt is generated and the memory channel operation ends even if the memory
address counter has not reached the end address.
The CPU can obtain the last address where the data is written by
reading out the value of memory address counter. (See Figure
126.)
38K2 Group
EXB Register List
The EXB register list is shown below.
Address
Register Name
EXB SFR
SYMBOL
003016
003116
EXB interrupt source enable register
EXB interrupt source register
EXBICON
EXBIREQ
003316
003416
003516
EXB index register
Register window 1 (low)
Register window 2 (high)
EXBINDEX
EXBREG1
EXBREG2
bit7
bit6
bit5
bit4
bit2
bit3
MC_ENB
MC_STS[1:0]
0
0
0
0
bit1
bit0
TXB_ENB
TXB_EMPTY
RXB_EMB
RXB_FULL
INDEX[2:0]
0
LOW_WIN[7:0]
HIGH_WIN[7:0]
: Not used
0 : “0” fixed
Fig. 107 EXB related registers (1)
•EXB interrupt source enable register
This register enables/disables access from an external bus and an
internal interrupt.
•EXB index register/Register windows 1, 2
The accessible register is switched by treating addresses 003416
and 003516 as a register window depending on the value of EXB
index register at address 003316.
•EXB interrupt source register
This register indicates the state of CPU channel’s transmit/receive
buffer register and the memory channel. The same value can be
read out from the external MCU bus by using the buffer status
read select signal (A1 pin = “H”).
Index
0016
low
high
low
Register Name
External I/O configuration register
high
0116
low
Transmit/Receive
buffer register
SYMBOL
low
low
low
bit4
bit3
EXBCFGH
TC_CTR
bit2
bit1
INT_CTR[2:0]
DAK_CTR[1:0]
bit0
EXB_CTR
DRQ_CTR[1:0]
At CPU read : RXBUF[7:0]
At CPU write : TXBUF[7:0]
RXBUF/TXBUF
—
BURST
Memory channel ope- MCHMOD
ration mode register
MC_DIR[1:0]
—
Memory address
counter
high
0416
bit5
A1_CTR
high
0316
bit6
EXBCFGL
high
0216
EXB SFR
bit7
MEMADL
MEMADH
End address
register
high
IM_A[7:0]
0
0
0
0
IM_A[10:8]
0
END_A[10:8]
END_A[7:0]
ENDADL
ENDADH
0
0
0
0
0
: Not used
0 : “0” fixed
Fig. 108 EXB related registers (2)
•External I/O configuration register
This register selects the function of each pin.
•Transmit/Receive buffer register
This register consists of the receive buffer register (RXBUF) and
the transmit buffer register (TXBUF)
•Memory channel operation mode register
This register sets the operation mode of the memory channel.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 75 of 147
•Memory address counter
This is a counter to set the beginning address which FIFO accesses. This register is increased by access from the external
MCU bus.
•End address register
This register is to set the end address which FIFO accesses.
38K2 Group
EXB Related Registers
The EXB related registers are shown below.
b0
b7
0 0
0
0
EXB interrupt source enable register (EXBICON) [address 003016]
(Note)
0
Bit symbol
RXB_ENB
TXB_ENB
MC_ENB
b7:b3
Bit name
Function
CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
0 : Operation disabled (Memory channel operation end
Memory channel operation
interrupt disabled)
enable bit
1 : Operation enabled (Memory channel operation end
interrupt disabled)
Write “0” when writing.
Not used
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 109 Structure of EXB interrupt source enable register
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
Bit symbol
Bit name
RXB_FULL
Receive buffer full bit
TXB_EMPTY Transmit buffer empty bit
MC_STS
[1:0]
(Note 2)
Memory channel status bits
b7:b4
Not used
Function
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O –
(Note 3)
0
0
O –
(Note 4)
0
0
O –
–
–
O O
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“002”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 110 Structure of EXB interrupt source register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 76 of 147
38K2 Group
b0
b7
0
0
0
EXB index register (EXBINDEX) [address 003316]
0 0
Bit symbol
Bit name
INDEX
[2:0]
Index bits
b7:b3
Not used
At reset
R W
H/W S/W
– O O
The accessible register, using the register window, 0
depends on these index bits contents as follows:
b2b1b0
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 111 Structure of EXB index register
b7
b0
Register window 1 (EXBREG1) [address 003416]
Bit symbol
LOW_WIN
[7:0]
Bit name
–
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
: External I/O configuration register
“0016”
“0116”
: Transmit/Receive buffer register
“0216”
: Memory channel operation mode register
“0316”
: Memory address counter
“0416”
: End address register
Function
Fig. 112 Structure of Register window 1
b7
b0
Register window 2 (EXBREG2) [address 003516]
Bit symbol
HIGH_WIN
[7:0]
Bit name
–
Fig. 113 Structure of Register window 2
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 77 of 147
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
: External I/O configuration register
“0016”
“0116”
: Transmit/Receive buffer register
: Memory channel operation mode register
“0216”
: Memory address counter
“0316”
: End address register
“0416”
Function
38K2 Group
b0
b7
0
0
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416]
0
Bit symbol
EXB_CTR
INT_CTR
[2:0]
Function
Bit name
EXB pin control bit
(Pins P10 to P17, P30 to P34)
P33/ExINT pin control bit
A1_CTR
P43/ExA1 pin control bit
b7:b5
Not used
0 : Port
1 : EXB function pin
Selects a signal of P33/ExINT pin.
ON/OFF is programmed by each bit. An output logical
sum of P33/ExINT pins set for ON are performed and it
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
1 : A1 input (used to read status)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 114 Index00[low]; Structure of External I/O configuration register
b0
b7
0
0
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516]
Bit symbol
Function
Bit name
DRQ_CTR
[1:0]
P40/ExDREQ/RxD pin control
bit
DAK_CTR
[1:0]
P41/ExDACK/TxD pin control
bit
TC_CTR
P42/ExTC/SCLK pin control bit
b7:b5
Not used
b1b0
0 0 : Port
0 1 : Do not set.
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
1 : ExTC (terminal count) input
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 115 Index00[high]; Structure of External I/O configuration register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 78 of 147
38K2 Group
b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416]
Bit symbol
RXBUF/
TXBUF
Bit name
–
At reset
R W
H/W S/W
– O O
The data received from an external bus is written here 0
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
Function
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “012” or “102” (memory channel being operating).
Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
0
0
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416]
0
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
BURST
Burst bit
b7:b3
Not used
b1b0
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
0 : Cycle mode (each byte transfer according to
assertion or negation)
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
–: State remaining
Fig. 117 Index02[low]; Structure of Memory channel operation mode register
b7
b0
Index = 0316 : Memory address counter (MEMADL) [address 003416]
Bit symbol
IM_A
[7:0]
Bit name
–
Fig. 118 Index03[low]; Structure of Memory address counter
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 79 of 147
At reset
R W
H/W S/W
Register to set the low-order address of memory 0
– O O
channel operation beginning.
This contents are increased each time one memory
access ends.
Function
38K2 Group
b0
b7
0
0
0
0
Index = 0316 : Memory address counter (MEMADH) [address 003516]
0
Bit symbol
Bit name
IM_A
[10:8]
–
b7:b3
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation start.
This contents are increased each time one memory
access ends.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 119 Index03[high]; Structure of Memory address counter
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416]
Bit symbol
END_A
[7:0]
Bit name
–
At reset
R W
H/W S/W
Register to set the low-order address of memory 0
– O O
channel operation end.
Function
–: State remaining
Fig. 120 Index04[low]; Structure of End address register
b0
b7
0
0
0
0
0
Index = 0416 : End address register (ENDADH) [address 003516]
Bit symbol
END_A
[10:8]
b7:b3
Bit name
–
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation end.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 121 Index04[high]; Structure of End address register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 80 of 147
38K2 Group
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
➀
➁
➂
Address ExA0
A0 = “1”
A0 = “1”
Chip select ExCS
CS = “0”
CS = “0”
Read ExRD
➁
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[RxB_RDY]
RxB_RDY
RxB_RDY
Receive buffer full bit RXB_FULL
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
➀
CPU channel receive enable bit
RXB_ENB
Receive buffer read
➂
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
➀ Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
➁ When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
• The data is written into the receive buffer (RXBUF)
• Negation of the receive buffer ready signal (RxB_RDY) to an external is made
• The RXB_FULL interrupt is generated.
➂ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
Fig. 122 CPU channel receiving operation
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 81 of 147
38K2 Group
(2) CPU Channel Transmitting Operation
CPU channel transmitting operation is shown bellow.
➀
➁
➂
➁’
Address ExA0
A0 = “1”
A0 = “1”
Chip select ExCS
CS = “0”
CS = “0”
➂
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[TxB_RDY]
TxB_RDY
TxB_RDY
Transmit buffer empty bit
TXB_EMPTY
Receive buffer RXBUF
Transmit buffer TXBUF
#0
#1
➀
CPU channel transmit enable bit
TXB_ENB
Transmit data write
➁’
➁
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)
➀ Writing the command for enabling operation generates TXB_EMPTY interrupt.
If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to
an external are inactive.
➁ When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared
to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.
➂ When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:
• The contents of the transmit buffer (TXBUF) is read out
• The transmit buffer empty bit (TXB_EMPTY) is set to “1”
• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.
Fig. 123 CPU channel tranmitting operation
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 82 of 147
38K2 Group
(3) Memory Channel Receiving Operation (1)Cycle Mode
Memory channel receiving operation (1) is shown bellow.
➀
➁
➂
➃
➁’
Address ExA0
A0 = “0”
A0 = “0”
Chip select ExCS
CS = “0”
CS = “0”
➂’
➄
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
Mch_req
Receive buffer RXBUF
#0
#1
➀
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
010116
010016
010216
Counter end
Acknowledgment of
internal memory access
ack
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
(Example) 010016
End address register
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of φ is made.
➁ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➂ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➃ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
➄ When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
Fig. 124 Memory channel receiving operation (1)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 83 of 147
38K2 Group
(4) Memory Channel Receiving Operation (2)Burst Mode
Memory channel receiving operation (2) is shown bellow.
➀
➁
➂
➁’
➃
➄
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
Dack = “0”
DMA acknowledge
ExDACK
Read ExRD
➁’
➁
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
Receive buffer RXBUF
#0
#1
#2
Operation enabled
➀
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
req
010116
010016
010216
010316
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
➂
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized
with a rise of φ is made.
➁ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➂ The memory address counter is increased simultaneously at the former data write completion.
➃
When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the
memory channel request which synchronized with the following φ is made.
➄ When
the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end
interrupt is generated.
Fig. 125 Memory channel receiving operation (2)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 84 of 147
38K2 Group
(5) Memory Channel Receiving Operation (3)Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
➀’
Address ExA0
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
DMA acknowledge
ExDACK
➁’
➀
➀
➀’
Terminal count ExTC
➁
TC
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
mTC
➔
Receive buffer RxBuf
#0
#1
detection
TC synchronizing
➁’
TC end
➁
➁’
Operation enabled
Main sequencer
0
1
2
3
(5)
5
Memory channel operation
end interrupt
➁’
req
Internal memory access
Memory address
010116
010016
➁’
010216
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
➁ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 126 Memory channel receiving operation (3)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 85 of 147
➁
38K2 Group
(6) Memory Channel Transmitting Operation
(1)-Cycle Mode
Memory channel transmitting operation (1) is shown bellow.
➀
➁
➂
➃
➄
➂’
➅
Address ExA0
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
DMA acknowledge
ExDACK
Dack = “0”
➂
Dack = “0”
➃
➂’
➅
Read ExRD
Write ExWR
#0
Data DQ0 to DQ7
#1
Internal clock φ
mRD
➔
detection
mRD
➔
DMA request
ExDREQ
detection
Mch_req
Mch_req
Transmission completed
Transmit buffer TXBUF
#0
➀
#1
Operation enabled
Main sequencer
0
1
2
3
4
5
Memory channel operation
end interrupt
req
Internal memory access
Memory address
req
010116
010016
010216
Counter end
Acknowledgment of
internal memory access
ack
ack
➄
➁
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
(Example) 010016
End address register
(Example) 010116
<Operation start command>
EXB interrupt source enable register
➀
MC_ENB (Memory channel operation enable) = “1” (Operation start)
In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal
memory access sequence which synchronized with a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➃ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➄ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 127 Memory channel tranmitting operation (1)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 86 of 147
38K2 Group
(7) Memory Channel Transmitting Operation
(2)-Burst Mode
Memory channel transmitting operation (2) is shown bellow.
➀
➁
➂
➃
➂’
➄
➅
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
DMA acknowledge
ExDACK
➂
Dack = “0”
➅
➂’
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
mRD
➔
detection
mRD
➔
DMA request
ExDREQ
detection
Mch_req
Transmission completed
Transmit buffer TXBUF
#0
#1
#2
Operation enabled
➀
Main sequencer
0
1
2
3
4
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
010016
req
010116
010216
010316
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
➁
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➃ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
➄ When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following φ is made.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 128 Memory channel tranmitting operation (2)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 87 of 147
5
38K2 Group
MULTICHANNEL RAM
The 38K2 group has the built-in multichannel RAM including the
small logic circuit (RAM I/F) instead of ordinary RAM.
The multichannel RAM has the USB channel and the EXB channel
in addition to the CPU channel.
The multichannel RAM controls access from CPU, USB and EXB,
synchronizing control with φ. The USB transfer rate is about 1.5
Mbytes/second. Access to the multichannel RAM is performed at
every about 5.3 clocks in φ = 8 MHz, or at every about 4 clocks in
φ = 6 MHz. The USB’s access has priority to the EXB’s.
The one wait function (ONW function) of 38000 series CPU is
used internally to control access with the CPU. When receiving an
access request from the USB or the EXB, the multichannel RAM
outputs ONW signal to wait the CPU for one clock, and access of
the USB or the EXB is performed.
If the multichannel RAM is outputting ONW signal while the CPU
is in the state of reading/writing for the RAM area, the CPU read
cycle or write cycle is extended by 1 period of φ.
No wait
No wait
No wait
ONW = “H”
Except RAM
No RD/WR
φ
CPU AD
CPU bus cycle
RAM area
Except RAM
RAM area
CPU
USB
CPU
RD/WR
USB REQ
Multichannel RAM
EXB REQ
ONW
RAM access right
RAM bus cycle
RAM RD/WR
Fig. 129 Multichannel RAM timing diagram (no wait)
One wait
CPU accessing RAM at the latter part
One wait
Prohibiting continuous access of
USB/EXB
Prior CPU
Prior CPU
One wait
USB having priority of USB/EXB
simultaneous access
Prior USB
One wait
2-cycle wait (max.) for EXB
Prior CPU
φ
CPU bus cycle
RAM area
CPU AD
RAM area
RAM area
RAM area
RD/WR
USB REQ
Multichannel RAM
EXB REQ
ONW
RAM access right
EXB
CPU
RAM bus cycle
RAM RD/WR
Fig. 130 Multichannel RAM timing diagram (one wait)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 88 of 147
USB
CPU
USB
CPU
EXB
CPU
38K2 Group
Multichannel RAM Operation Example
The multichannel RAM operation example is shown below.
This example shows the case that an external MCU uses the
38K2 group as a peripheral LSI (USB controller).
The following explains that the external MCU reads out the data
which is received via the USB.
➀ The data which is received via the USB is written into the multichannel RAM.
➁ Receive completion is propagated to the CPU.
➂ The external bus interface is activated owing to the CPU.
➃ (1) The external bus interface sets the data which is read from
the multichannel RAM into the internal data buffer.
(2) The external MCU reads out the data bus buffer of the external bus interface.
(3) The above operation is repeated by the number of the received bytes. After that, the data transfer is completed.
Program ROM
External MCU
CPU
➂ Activating
Peripheral functions
➁ Notice of receive completion
External MCU bus
External bus interface
➃ FIFO read of received data
by External bus interface
Fig. 131 Multichannel RAM operation example
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 89 of 147
Multichannel RAM
USB
➀ FIFO write of received data
by USB
USB bus
(USB host)
38K2 Group
A/D CONVERTER
Comparator and Control Circuit
The functional blocks of the A/D converter are described below.
The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(system clock) to 500 kHz or more during an A/D
conversion.
[AD Conversion Register 1, 2 (AD1, AD2)]
003716, 003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 must be set to “0”. Not only
10-bit reading but also only high-order 8-bit reading of conversion
result can be performed by selecting the reading procedure of the
AD conversion registers 1, 2 after A/D conversion is completed (in
Figure 133).
The 8-bit reading inclined to MSB is performed when reading the
AD converter register 1 after A/D conversion is started or reset;
and when the AD converter register 1 is read after reading the AD
converter register 2, the 8-bit reading inclined to LSB is performed.
b7
b0
AD control register
(ADCON : address 003616)
Analog input pin selection bits
0 0 0 : P10/DQ0/AN0
0 0 1 : P11/DQ1/AN1
0 1 0 : P12/DQ2/AN2
0 1 1 : P13/DQ3/AN3
1 0 0 : P14/DQ4/AN4
1 0 1 : P15/DQ5/AN5
1 1 0 : P16/DQ6/AN6
1 1 1 : P17/DQ7/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (indefinite at read)
(These bits are write disabled bits.)
[AD Control Register (ADCON)] 003616
The AD control register controls the A/D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0”
during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison voltage.
The A/D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
• 10-bit reading
VREF
Vref = 1024 ✕ n (n = 0–1023)
Fig. 132 Structure of AD control register
10-bit reading
(Read address 003816 before 003716)
b7
(address 003816)
0
(address 003716)
• 8-bit reading
b0
b7
b7 b6 b5 b4 b3 b2 b1 b0
Note : Bits 2 to 7 of address 003816 become “0”
at reading.
Vref = VREF ✕ n (n = 0–255)
256
8-bit reading
Channel Selector
(Read only address 003716)
The channel selector selects one of the input ports P17/AN7–P10/
AN0.
b7
(address 003716)
Fig. 133 10-bit/8-bit reading
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
b0
b9 b8
page 90 of 147
b0
b9 b8 b7 b6 b5 b4 b3 b2
38K2 Group
Data bus
AD control register
(address 003616)
b7
b0
3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
Comparator
AD conversion register 2
(address 003816)
AD conversion register 1
(address 003716)
10
Resistor ladder
VREF
Fig. 134 A/D converter block diagram
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
A/D interrupt request
A/D control circuit
Channel selector
P10/DQ0/AN0
P11/DQ1/AN1
P12/DQ2/AN2
P13/DQ3/AN3
page 91 of 147
VSS
38K2 Group
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 0039 16) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at system clock 8 MHz frequency.
When this bit is set to “1”, the count source becomes the system
clock divided by 16. The detection time in this case is set to 512
µs at system clock 8 MHz frequency. This bit is cleared to “0” after
resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039 16 ) may be
started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit (bit 6), and
watchdog timer H count source selection bit (bit 7) are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0039 16) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer L (8)
System clock
1/16
“0”
“1”
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset circuit
RESET
Internal reset
Fig. 135 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: System clock/16
Fig. 136 Structure of Watchdog timer control register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 92 of 147
38K2 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage should be between 3.0 V
and 5.25 V for L version, and the oscillation should be stable), reset is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-order byte)
and address FFFC16 (low-order byte). Make sure that the reset input voltage is under 0.6 V for VCC of 3.0 V (L version).
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ;
Vcc = 3.0 V (L version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 137 Example of reset circuit
XIN
φ
RESET
Internal
reset
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 138 Reset sequence
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 93 of 147
38K2 Group
PLL CIRCUIT (FREQUENCY SYNTHESIZER)
The PLL circuit generates f VCO (PLL output clock), which is required for fUSB (USB clock) and f SYN (fUSB division clock), from
f(XIN) (external input reference clock). Figure 139 shows the PLL
circuit block diagram.
It is possible to input 6 or 12 MHz clock from the externals as a
standard clock input. When using the USB function, set the PLL
operation mode selection bit so that fvco may be set to 48 MHz.
The PLL circuit operates by setting the PLL operation enable bit to
“1”. When supplying fVCO to the USB block, wait for the oscillation
stable time (1ms or less) of PLL before selecting fVCO with the
USB clock selection bit.
According to the setting of the USB clock division ratio selection
bit, the division clock of fUSB is supplied to fSYN. When using this
clock as system clock, set the USB clock division ratio selection
bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However,
using it only when fUSB is 48MHz is recommended).
fUSB
f(XIN)
PLL
fVCO
PLLCON
(address 0FF816)
Fig. 139 Block diagram of PLL circuit
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 94 of 147
Division circuit
USBCON
(address 001016)
fSYN
38K2 Group
b7
b0
PLL control register
(PLLCON: address 0FF816)
Not used (return “0” when read)
USB clock division ratio selection bits
b4b3
0 0: Divided by 8 (fSYN = fUSB/8)
0 1: Divided by 6 (fSYN = fUSB/6)
1 0: Divided by 4 (fSYN = fUSB/4)
1 1: Not selected
PLL operation mode selection bits
b6b5
0 0: Not multiplied (fVCO = fXIN)
0 1: Double (fVCO = fXIN ✕ 2)
1 0: Quadruple (fVCO = fXIN ✕ 4)
1 1: Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL Enable Bit
0: Disabled
1: Enabled
Fig. 140 Structure of PLL control register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 95 of 147
38K2 Group
CLOCK GENERATING CIRCUIT
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed
depending on conditions.)
Frequency Control
Either fSYN or f(XIN) can be selected as an internal system clock.
Furthermore, the frequency of internal clock φ can be selected by
the system clock division ratio selection bit.
(1) fSYN clock
fSYN clock is generated by the PLL circuit. f(X IN) or f VCO can be
selected as an input clock. When using as an internal system
clock, there is restriction on use. Refer to the clause of “PLL CIRCUIT”.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and the XIN oscillator stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. X IN
divided by 16 is compulsorily connected to the input of the
prescaler 12. Oscillator restarts when an external interrupt (including USB resume interrupt) is received, but the internal clock φ
remains at “H” until timer 1 underflows. The internal clock φ is not
supplied until timer 1 underflows. Because the sufficient time is required for the oscillation to stabilize when a ceramic resonator etc.
is used. When the oscillator is restarted by reset, apply “L” level to
the RESET pin until the oscillation is stable since a wait time will
not be generated automatically.
(2) f(XIN) clock
The frequency applied to the XIN pin is used as an internal system
clock frequency.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock X IN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruction.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 96 of 147
38K2 Group
b7
XIN
b0
XOUT
MISRG
(MISRG: address 0FFB16)
Rd (Note)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Not used (indefinite at read)
COUT
CIN
Note : Insert a damping resistor if required.
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external
to the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT
following the instruction.
Fig. 143 Structure of MISRG
Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit
XIN
XOUT
Open
External oscillation circuit
VCC
VSS
Fig. 142 External clock input circuit
XIN
XOUT
PLL
fvco USB clock selection bit
fUSB
1/6
1/4
1/8
USB clock division
ration selection bits
System clock selection bit
fSYN
fsio
fAD
1/2
1/1
1/2
1/2
1/4
1/2
1/8
1/2
Prescaler 12
FF16
System clock division
ration selection bits
Timer 1
0116
Reset or STP
instruction
Timing φ (internal clock)
S Q
Q S
R
STP instruction
WIT
instruction
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 144 System clock generating circuit block diagram (single-chip mode)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 97 of 147
Reset
Q S
R
STP instruction
38K2 Group
Reset
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN.
f(SYN) 2-divide mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 0
CM5 = 1
PLLCON [4:3] = 10
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
CM6
“0”←→“1”
CM7
“1”←→“0”
XIN 4-divide mode
f(φ) = 1.5 MHz
CM 7 = 0
CM 6 = 0
CM 5 = 0
PLLCON [4:3] = xx
(arbitrary)
XIN through mode
f(φ) = 1.5 MHz
CM 7 = 0
CM 6 = 0
CM 5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM5
“1”←→“0”
C
“0 M6
CM ”←
“1 7 →“
1”
”←
→
“0
”
CM7
“1”←→“0”
XIN 2-divide mode
f(φ) = 3.0 MHz
CM7 = 1
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM5
“1”←→“0”
CM6
“0”←→“1”
”
6 →“1
CM ”←
1”
“0 M7 →“
C ”←
“0
XIN 8-divide mode
f(φ) = 0.75 MHz
CM 7 = 0
CM 6 = 0
CM 5 = 0
PLLCON [4:3] = 00
f(SYN) through mode
f(φ) = 12.0 MHz
CM 7 = 1
CM 6 = 1
CM 5 = 1
PLLCON [4:3] = 10
Under planning
f(SYN) through mode
f(φ) = 6.0 MHz
CM 7 = 1
CM 6 = 1
CM 5 = 1
PLLCON [4:3] = 00
f(SYN) through mode
f(φ) = 8.0 MHz
CM 7 = 1
CM 6 = 1
CM 5 = 1
PLLCON [4:3] = 01
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN.
5 : Set the system clock to XIN when entering STOP mode.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
Fig. 145 State transitions of clock
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 98 of 147
38K2 Group
FLASH MEMORY MODE
The 38K2 group’s flash memory version has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 4.5 to 5.25 V, and 2 power
sources when VCC is 3.0 to 4.5 V.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
This flash memory version has some blocks on the flash memory
as shown in Figure 146 and each block can be erased. The flash
memory is divided into User ROM area and Boot ROM area.
In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O
mode.
Summary
Table 9 lists the summary of the 38K2 group’s flash memory version.
Table 9 Summary of 38K2 group’s flash memory version
Item
Power source voltage (Vcc)
Program/Erase VPP voltage (VPP)
Flash memory mode
Specifications
3.00 – 5.25 V (L version) (Program and erase in 4.00 to 5.25 V of Vcc.)
3.00 – 4.00 V (L version) (Program and erase in 3.00 to 5.25 V of Vcc.)
4.50 – 5.25 V
3 modes; Flash memory can be manipulated as follows:
•CPU rewrite mode: Manipulated by the Central Processing Unit (CPU).
•Parallel I/O mode: Manipulated using an external programmer (Note 1)
•Standard serial I/O mode: Manipulated using an external programmer (Note 1)
Erase block division
User ROM area
Boot ROM area
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
Data retention period
ROM code protection
1 block (32 Kbytes)
1 block (4 Kbytes) (Note 2)
Byte program
Batch erasing
Program/Erase control by software command
6 commands
100 times
10 years
Available in parallel I/O mode and standard serial I/O mode
Notes 1: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 38K2 Group
(flash memory version).
2: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 99 of 147
38K2 Group
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Processing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure
146 can be rewritten; the Boot ROM area cannot be rewritten.
Make sure the program and block erase commands are issued for
only the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be
executed before it can be executed.
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.)
See Figure 146 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNV SS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P16 (CE) pin high,
the CNVSS pin high, the CPU starts operating using the control
program in the Boot ROM area. This mode is called the “Boot”
mode.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
User ROM area
800016
Block 1 : 32 Kbytes
Boot ROM area
F00016
FFFF16
FFFF16
4 Kbytes
Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other
areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 146 Block diagram of built-in flash memory
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 100 of 147
38K2 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select
Bit (bit 1 of address 0FFE16). Software commands are accepted
once the mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 147 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready). This is
equivalent to the RY/BY pin function in parallel I/O mode.
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
b7
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. The bit can
be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Figure 148 shows a flowchart for setting/releasing CPU rewrite
mode.
b0
Flash memory control register (address 0FFE16)
FMCR (Note 1)
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 147 Structure of flash memory control register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 101 of 147
38K2 Group
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program to
memory other than internal flash memory
Jump to control program transferred in memory
other than internal flash memory
(Subsequent operations are executed by control
program in this memory)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply
4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag.
2: Set the system clock division ration selection bits of CPU mode register (bits 6 and
7 at address 003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 148 CPU rewrite mode set/release flowchart
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 102 of 147
38K2 Group
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
●Operation speed
During CPU rewrite mode, set the internal clock φ to 1.5 MHz or
less using the system clock division ratio selection bits (bits 6 and
7 of address 003B16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
●Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the program will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 103 of 147
38K2 Group
____
Software Commands
During the program movement, The RY/BY Status Flag of flash
memory control register is set to “0”. When the program completes, it becomes “1”.
At program end, program results can be checked by reading the
status register.
Table 10 lists the software commands.
After setting the CPU Rewrite Mode Select Bit to “1”, write a software command to specify an erase or program operation.
Each software command is explained below.
●Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7).
The read array mode is retained intact until another command is
written.
Start
Write 4016
Write Write address
Write data
●Read Status Register Command (7016)
When the command code “70 16” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Status register
read
●Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
or
RY/BY = 1 ?
●Program Command (4016)
Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, the control circuit of flash memory
(data programming and verification) will start a program.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag. When the
program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus
(DB0 to DB7). The status register bit 7 (SR7) is set to “0” at the
same time the write operation starts and is returned to “1” upon
completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is
written.
S R4 = 0 ?
NO
YES
NO
Program
error
YES
Program
completed
Fig. 149 Program flowchart
Table 10 List of software commands (CPU rewrite mode)
Command
Cycle number
Mode
Read array
1
Write
First bus cycle
Data
Address
(D0 to D7)
X
(Note 4)
Second bus cycle
Data
Mode
Address
(D0 to D7)
FF16
Read status register
2
Write
X
7016
Clear status register
1
Write
X
5016
Program
2
Write
X
4016
Write
WA (Note 2)
WD (Note 2)
Erase all blocks
2
Write
X
2016
Write
X
2016
Block erase
2
Write
X
2016
Write
(Note 3)
D016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 104 of 147
Read
X
BA
SRD
(Note 1)
38K2 Group
●Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is written.
____
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7.
After the erase all blocks end, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
●Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is written.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register bit 7.
After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the
status register is detailed.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 105 of 147
Start
Write 2016
Write
2016/D016
Block address
2016:Erase all blocks
D016:Block erase
Status register
read
SR7 = 1 ?
or
RY/BY = 1 ?
NO
YES
SR5 = 0 ?
YES
Erase completed
Fig. 150 Erase flowchart
NO
Erase error
38K2 Group
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 11 shows the status register. Each bit in this register is explained below.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status register command (5016) and clear the status register.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 11 Definition of each bit in status register
Each bit of
SRD0 bits
Status name
SR7 (bit7)
SR6 (bit6)
Sequencer status
Reserved
SR5 (bit5)
SR4 (bit4)
Erase status
Program status
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Definition
“1”
“0”
Ready
-
Busy
-
Terminated in error
Terminated in error
Terminated normally
Terminated normally
Reserved
Reserved
-
-
Reserved
Reserved
-
-
page 106 of 147
38K2 Group
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 151 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 151 Full status check flowchart and remedial procedure for errors
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 107 of 147
38K2 Group
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode.
●ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control register (address FFDB16) in parallel I/O mode. Figure 152 shows the ROM code protect control
register (address FFDB16). (This address exists in the User ROM
area.)
b7
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits.
b0
ROM code protect control register (address FFDB16)
ROMCP
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Fig. 152 Structure of ROM code protect control register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 108 of 147
38K2 Group
ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD4 16 to FFDA 16. Write a program which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM cord protect control
Interrupt vector area
Fig. 153 ID code store addresses
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 109 of 147
38K2 Group
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the
38K2 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 146 can be rewritten. Both areas of flash memory can be operated
on in the same way.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block.
The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial I/O mode, you must perform
program and block erase in the user ROM area.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 110 of 147
38K2 Group
(3) Standard Serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific peripheral unit.The standard serial I/O mode is different from the
parallel I/O mode in that the CPU controls flash memory rewrite
(uses the CPU rewrite mode), rewrite data input and so forth. The
standard serial I/O mode is started by connecting “H” to the P16
(CE) pin and “H” to the P42 (SCLK) pin and “H” to the CNVSS (VPP)
pin (apply 4.5 V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode,
set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Renesas Technology Corp.. Accordingly,
make note of the fact that the standard serial I/O mode cannot be
used if the Boot ROM area is rewritten in parallel I/O mode. Figure
154 shows the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY (BUSY) pin outputs “L” level when ready for reception and “H” level when
reception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 146 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 111 of 147
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is “H” level. Accordingly,
always start the next transfer after the S RDY (BUSY) pin is “L”
level.
Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
38K2 Group
Table 12 Description of pin function (Standard Serial I/O Mode)
Pin name
VCC,VSS
VCCE
CNVSS
CNVSS2
VREF
DVCC, PVCC
PVSS
RESET
XIN
XOUT
USBVREF
TrON
D0+,D0D1+,D1D2+,D2P00 to P07
P10 to P15
P16
P17
P20 to P24
P30 to P37
P40
P41
P42
P43
P50 to P57
P60 to P63
Signal name
Power supply
Power supply
VPP
CNVSS2
Analog reference voltage
Analog power supply
Analog power supply
Reset input
Clock input
Clock output
USB reference voltage input
USB reference voltage output
USB upstream input
USB downstream input
USB downstream input
Input port P0
I
I
O
I
O
I/O
I/O
I/O
I
Input port P1
Input port P1
Input port P1
Input port P2
Input port P3
RxD input
TxD output
SCLK input
BUSY output
Input port P5
Input port P6
I
I
I
I
I
I
O
I
O
I
I
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 112 of 147
I/O
I
I
I
Function
Apply 3.00 to 5.25 V (L version) to the Vcc pin and 0 V to the Vss pin.
Connect this pin to Vcc.
Connect this pin to VPP (VPP = 4.50 to 5.25 V).
Connect this pin to Vss.
Connect this pin to Vcc when not using.
Connect this pin to Vcc.
Connect this pin to Vss.
To reset, input “L” level for 20 cycles or longer clocks of φ.
Connect a ceramic or crystal resonator between the XIN and XOUT pins. When
entering an externally drived clock, enter it from XIN and leave XOUT open.
Connect this pin to Vcc when not using.
Leave this pin open when not using.
Input “L” level when not using.
Input “L” level when not using.
Input “L” level when not using.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.Input “H” level only at release of reset.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
This is a serial data input pin.
This is a serial data output pin.
This is a serial clock input pin.Input “H” level only at release of reset.
This is a BUSY output pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
P05
P04
P03
P02
P01
P00
P57
P56
P55
P54
P53
P52/INT1
P51/CNTR0
P50/INT0
P27
P26
38K2 Group
Vcc
34
33
36
35
37
41
40
39
38
44
43
42
54
55
56
57
58
59
27
26
25
24
28
M38K29F8LFP/HP
23
22
21
20
60
61
19
18
17
62
63
CE
15
16
13
14
11
12
8
9
10
RESET
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
CNVSS
RESET
VCCE
VREF
VSS
XIN
XOUT
VCC
CNVSS2
P60(LED0)
4
64
1
BUSY
5
6
7
SCLK
32
31
30
29
3
RXD
TXD
49
50
51
52
53
2
P06
P07
P40/EXDREQ/RXD
P41/EXDACK/TXD
P42/EXTC/SCLK
P43/EXA1/SRDY
P30
P31
P32
P33/EXINT
P34/EXCS
P35/EXWR
P36/EXRD
P37/EXA0
P10/DQ0/AN0
P11/DQ1/AN1
47
46
45
48
Vss
Mode setup method
Value
4.5 to 5.25 V
SCLK
Vcc (Note 2)
RESET
CE
Vss → Vcc
Vcc (Note 2)
(Note 1)
VPP
Signal
CNVss
Connect to oscillator circuit.
Notes 1: Connect to Vcc in the case of Vcc = 4.5 V to 5.25 V.
Connect to VPP (= 4.5 V to 5.25 V) in the case of Vcc = 3.0 V to 4.5 V.
2: Supply Vcc at releasimg Reset.
Package outline: PLQP0064GA-A, PLQP0064KB-A
Fig. 154 Pin connection diagram in standard serial I/O mode
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 113 of 147
P25
P24
D2+
D2D1+
D1D0D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P63(LED3)
P62(LED2)
P61(LED1)
38K2 Group
Software Commands
Table 13 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
commands via the RxD pin. Software commands are explained
here below. Basically, the software commands of the standard serial I/O mode are the same as that of the parallel I/O mode, but the
block erase function is excluded, and 4 commands are added: ID
check, download, version data output and Boot ROM area output
functions.
Table 13 Software commands (Standard serial I/O mode)
Control command
1st byte
transfer
2nd byte
3rd byte
4th byte
5th byte
6th byte
.....
When ID is
not verified
Data
output to
259th byte
Data input
to 259th
byte
Not
acceptable
1
Page read
FF16
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
2
Page program
4116
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
3
Erase all blocks
A716
D016
4
Read status register
7016
SRD
output
5
Clear status register
5016
6
ID check function
F516
Address
(low)
Address
(middle)
7
Download function
FA16
Size
(low)
8
Version data output function
FB16
9
Boot ROM area output
function
FC16
Version
data
output
Address
(middle)
Not
acceptable
Not
acceptable
Acceptable
SRD1
output
Not
acceptable
ID size
ID1
Size
(high)
Address
(high)
Checksum
Data
input
Version
data
output
Address
(high)
Version
data
output
Data
output
Version
data
output
Data
output
To
required
number
of times
Version
data
output
Data
output
To ID7
Acceptable
Not
acceptable
Version
data output
to 9th byte
Data
output to
259th byte
Acceptable
Not
acceptable
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from a programmer to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address low is A0 to A7; Address middle is A8 to A15; Address high is A16 to A23. Address-high A16 to A23 are always “0016”.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 114 of 147
38K2 Group
The contents of software commands are explained as follows.
●Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A 8 to A 23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
SCLK
RxD
FF16
A8 to
A15
A16 to
A23
TxD
data0
SRDY (BUSY)
Fig. 155 Timing for page read
●Read Status Register Command
This command reads status information. When the “7016 ” command code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 156 Timing for reading status register
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 115 of 147
7016
SRD
output
SRD1
output
data255
38K2 Group
●Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from “H” to “L” level.
SCLK
5016
RxD
TxD
SRDY (BUSY)
Fig. 157 Timing for clear status register
●Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0 to D 7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the S RDY
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
SCLK
RxD
4116
TxD
SRDY (BUSY)
Fig. 158 Timing for page program
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 116 of 147
A8 to
A15
A16 to data0
A23
data255
38K2 Group
●Erase All Blocks Command
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
When erase all blocks end, the SRDY (BUSY) signal changes from
“H” to “L” level. The result of the erase operation can be known by
reading the status register.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 159 Timing for erase all blocks
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 117 of 147
A716
D016
38K2 Group
●Download Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 160 Timing for download
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 118 of 147
FA16
Data size Data size
(low)
(high)
Check
sum
Program
data
Program
data
38K2 Group
●Version Information Output Command
This command outputs the version information of the control program stored in the Boot ROM area. Execute the version
information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward.
This data is composed of 8 ASCII code characters.
SCLK
RxD
FB16
TxD
‘V’
‘E’
‘R’
‘X’
SRDY (BUSY)
Fig. 161 Timing for version information output
●Boot ROM Area Output Command
This command reads the control program stored in the Boot ROM
area in page (256 bytes) unit. Execute the Boot ROM area output
command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A 8 to A 23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
SCLK
R xD
FC16
TxD
SRDY (BUSY)
Fig. 162 Timing for Boot ROM area output
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 119 of 147
A 8 to A 15
A 1 6 to A23
data0
data255
38K2 Group
●ID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd and 4th respectively.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
SCLK
RxD
F516
D416
FF16
0016
ID size
TxD
SRDY (BUSY)
Fig. 163 Timing for ID check
●ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM code protect control
Interrupt vector area
Fig. 164 ID code storage addresses
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 120 of 147
ID1
ID7
38K2 Group
●Status Register (SRD)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (70 16 ). Also, the status register is
cleared by writing the clear status register command (5016).
Table 14 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the the
flash memory.
After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 14 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
Ready
Busy
Reserved
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
SR3 (bit3)
Program status
Reserved
Terminated in error
-
Terminated normally
-
SR2 (bit2)
SR1 (bit1)
Reserved
Reserved
-
-
SR0 (bit0)
Reserved
-
-
SR7 (bit7)
Sequencer status
SR6 (bit6)
SR5 (bit5)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 121 of 147
38K2 Group
●Status Register 1 (SRD1)
The status register 1 indicates the status of serial communications, results from ID checks and results from check sum
comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by
writing the clear status register command (5016).
Table 15 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download function.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command
wait state.
Table 15 Status register 1 (SRD1)
SRD1 bits
SR15 (bit7)
SR14 (bit6)
Boot update completed bit
Reserved
SR13 (bit5)
SR12 (bit4)
Reserved
Checksum match bit
SR11 (bit3)
SR10 (bit2)
ID check completed bits
SR9 (bit1)
SR8 (bit0)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
Definition
Status name
Data reception time out
Reserved
page 122 of 147
“1”
“0”
Update completed
-
Not Update
-
Match
00
01
Not verified
Verification mismatch
10
11
Reserved
Verified
Time out
-
Mismatch
Normal operation
-
38K2 Group
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 165 shows a flowchart of the full status check and explains how to remedy errors
which occur.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 165 Full status check flowchart and remedial procedure for errors
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 123 of 147
38K2 Group
Example Circuit Application for Standard
Serial I/O Mode
Figure 166 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
VCC
Clock input
BUSY output
VCC
SCLK
P16 (CE)
SRDY (BUSY)
Data input
RxD
Data output
TxD
VPP power
source input
CNVss
M38K29F8L
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the VPP power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.25 V.
Fig. 166 Example circuit application for standard serial I/O mode
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 124 of 147
38K2 Group
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer
X.
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(system clock) in the middle/highspeed mode is at least on 500 kHz during an A/D conversion.
Do not execute the STP or WIT instruction during an A/D conversion.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 125 of 147
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction. However, When using the USB function or
EXB function, an occurrence of one-wait due to the multichannel
RAM will double an internal clock φ cycle.
38K2 Group
Definition of A/D Conversion Accuracy
The A/D conversion accuracy is defined below (refer to Figure
167).
•Relative accuracy
➀ Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
➂ Non-linearity error
This means a deviation from the line between VOT and VFST of
a converted value between VOT and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value between VOT and VFST by 1
LSB of the 1 LSB at the relative accuracy.
•Absolute accuracy
This means a deviation from the ideal characteristics between 0 to
VREF of actual A/D conversion characteristics.
Ou tp u t d a ta
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error=
c
Non-linearity error=
a [LSB]
b-a
a [LSB]
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-Vn
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
V0
V1
Zero transition voltage (V0T)
Vn
Vn+1
V1022
Analog voltage
VREF
Fig. 167 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V FST – V OT
1022
VREF
• 1 LSB at absolute accuracy →
1024
• 1 LSB at relative accuracy →
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 126 of 147
(V)
(V)
38K2 Group
NOTES ON USAGE
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic or electrolytic capacitor of 1.0 µF is recommended.
USB Port Pins (D0+, D0-, D1+, D1-, D2+, D2-)
Treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In
order to meet the USB specification impedance requirements,
connect a resistor (27 Ω recommended) in series to the USB port
pins.
In addition, in order to reduce the ringing and control the falling/
rising timing and a crossover point, connect a capacitor between
the USB port pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on
the impedance characteristics and the layout of the printed circuit
board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of
resistors and capacitors.
•Make sure the USB D+/D- lines do not cross any other wires.
Keep a large GND area to protect the USB lines. Also, make sure
you use a USB specification compliant connecter for the connection.
USBVREF pin Treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin.
The capacitor should have a 2.2 µF capacitor (electrolytic capacitor) and a 0.1 µF capacitor (ceramic type capacitor) connected in
parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly
to the Vcc pin in order to supply power to the USB port circuit. In
addition, you will need to disable the built-in USB reference voltage circuit in this operation (set bit 4 of the USB control register
to “0”.) If you are using the bus powered supply in this condition,
the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external
DC-DC converter to the USBVREF pin. Use the built-in USB reference voltage circuit.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 127 of 147
USB Communication
In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB
communication from being terminated unexpectedly, for example
due to external causes such as noise.
Flash Memory Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the Flash
Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form✽
2. Mark Specification Form✽
3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
✽ For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
38K2 Group
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 16 Absolute maximum ratings
Parameter
Symbol
VCC
Power source voltage
AVCC
Analog power source voltage VCCE, VREF, PVCC, DVCC,
USBVREF
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ratings
Unit
–0.3 to 6.5
V
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
VI
Input voltage
P00–P07, P10–P17, P24–P27, P30–
P37, P40–P43, P50–P57, P60–P63
VI
Input voltage
RESET, XIN, CNVSS2
–0.3 to VCC + 0.3
V
VI
Input voltage
CNVSS
–0.3 to VCC + 0.3
V
–0.3 to 6.5
V
–0.5 to 3.8
V
–0.3 to VCC + 0.3
V
–0.5 to 3.8
V
Mask ROM version
Flash memory version
VI
Input voltage
D0+, D0-, D1+, D1-, D2+, D2-
VO
Output voltage
P00–P07, P10–P17, P24–P27, P30–
P37, P40–P43, P50–P57, P60–P63,
XOUT
VO
Output voltage
D0+, D0-, D1+, D1-, D2+, D2-, TrON
Pd
Power dissipation
Topr
Operating temperature
(Note)
Ta = 25°C
MCU operating
In flash memory mode
(For flash memory version)
Tstg
Storage temperature
500
mW
–20 to 85
°C
25±5
°C
–40 to 125
°C
Note: The maximum rating value depends on not only the MCU’s power dissipation but the heat consumption characteristics of the package.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 128 of 147
38K2 Group (L Ver.)
Recommended Operating Conditions
Table 17 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VCC
Limits
Parameter
Power source voltage
VCC
Unit
Min.
Typ.
Max.
System clock 12 MHz
(2-/4-/8-divide mode)
4.00
5.00
5.25
V
System clock 8 MHz
4.00
5.00
5.25
V
System clock 6 MHz
3.00
5.00
5.25
V
AVCC
Analog power source voltage
PVCC, DVCC
VCC
AVCC
Analog power source voltage
VCCE
VCC
VREF
Analog reference voltage
VREF
VREF
Analog reference voltage
USBVREF
VSS
Power source voltage
VSS
0
AVSS
Analog power source voltage
PVSS
0
VIH
“H” input voltage
VIH
VIH
V
V
2.0
VCC
V
Vcc = 3.6 to 4.0 V
3.0
3.6
V
Vcc = 3.0 to 3.6 V
3.0
VCC
V
V
V
0.8VCC
VCC
V
V
P10–P17, P30–P37, P40–P43
0.8VCCE
VCCE
V
RESET, XIN, CNVSS, CNVSS2
0.8VCC
VCC
V
D0+, D0-, D1+, D1-, D2+, D2-
2.0
3.6
V
P00–P07, P24–P27, P50–P57,
P60–P63
0
0.2VCC
V
“L” input voltage
P10–P17, P30–P37, P40–P43
0
0.2VCCE
V
“L” input voltage
RESET, XIN, CNVSS, CNVSS2
0
0.2VCC
V
“L” input voltage
D0+, D0-, D1+, D1-, D2+, D2-
0
0.8
V
P00–P07, P24–P27, P50–P57,
P60–P63
“H” input voltage
“H” input voltage
VIH
“H” input voltage
VIL
“L” input voltage
VIL
VIL
VIL
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 129 of 147
38K2 Group (L Ver.)
Table 18 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
∑IOH(peak)
“H” total peak output current (Note 1)
∑IOH(peak)
∑IOL(peak)
Min.
Typ.
Max.
Unit
P00–P07, P24–P27, P50–P57,
P60–P63
–80
mA
“H” total peak output current (Note 1)
P10–P17, P30–P37, P40–P43
–80
mA
“L” total peak output current (Note 1)
P00–P07, P24–P27, P50–P57
80
mA
∑IOL(peak)
“L” total peak output current (Note 1)
P60–P63
80
mA
∑IOL(peak)
“L” total peak output current (Note 1)
P10–P17, P30–P37, P40–P43
80
mA
∑IOH(avg)
“H” total average output current (Note 1)
P00–P07, P24–P27, P50–P57,
P60–P63
–40
mA
∑IOH(avg)
“H” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
–40
mA
∑IOL(avg)
“L” total average output current (Note 1)
P00–P07, P24–P27, P50–P57
40
mA
∑IOL(avg)
“L” total average output current (Note 1)
P60–P63
40
mA
∑IOL(avg)
“L” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
40
mA
P00–P07, P24–P27, P50–P57,
P60–P63
–10
mA
IOH(peak)
“H” peak output current (Note 2)
IOH(peak)
“H” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
–10
mA
IOL(peak)
“L” peak output current (Note 2)
P00–P07, P24–P27, P50–P57
10
mA
P60–P63
20
mA
IOL(peak)
“L” peak output current (Note 2)
IOL(peak)
“L” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
10
mA
IOH(avg)
“H” average output current (Note 3)
P00–P07, P24–P27, P50–P57,
P60–P63
–5
mA
IOH(avg)
“H” average output current (Note 3)
P10–P17, P30–P37, P40–P43
–5
mA
IOL(avg)
“L” average output current (Note 3)
P00–P07, P24–P27, P50–P57
5
mA
IOL(avg)
“L” average output current (Note 3)
P60–P63
10
mA
IOL(avg)
“L” average output current (Note 3)
P10–P17, P30–P37, P40–P43
5
mA
f(XIN)
Main clock input oscillation frequency
Vcc = 4.00 to 5.25 V
6
12
MHz
(Note 4)
Vcc = 3.00 to 4.00 V
6
6
MHz
System clock frequency
Vcc = 4.00 to 5.25 V
6
12
MHz
Vcc = 3.00 to 4.00 V
6
6
MHz
Vcc = 4.00 to 5.25 V
8
MHz
Vcc = 3.00 to 4.00 V
6
MHz
f(XIN) or
f(SYN)
f(φ)
φ frequency
Notes 1: The total peak output current is the absolute value of the peak currents flowing through all the applicable ports. The total average output current is
the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the absolute value of the peak current flowing in each port.
3: The average output current is the average value of the absolute value of the currents measured over 100 ms.
4: The duty of oscillation frequency is 50 %. 6 MHz or 12 MHz is usable.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 130 of 147
38K2 Group (L Ver.)
Electrical Characteristics
Table 19 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage
P00–P07, P24–P27, P50–P57, P60–P63
VOH
“H” output voltage
P10–P17, P30–P37, P40–P43
VOH
“H” output voltage
D0+, D0-, D1+, D1-, D2+, D2-
VOL
“L” output voltage
P00–P07, P24–P27, P50–P57
VOL
“L” output voltage
P60–P63
VOL
“L” output voltage
P10–P17, P30–P37, P40–P43
VOL
“L” output voltage
D0+, D0-, D1+, D1-, D2+, D2-
VT+–VT-
Hysteresis
CNTR0, INT0, INT1
Hysteresis
P10/DQ0–P17/DQ7, P30–P32, P33/ExINT,
P34/ExCS, P35/ExWR, P36/ExRD, P37/
ExA0, P40/ExDREQ/RxD, P41/ExDACK/
TxD, P42/ExTC/SCLK, P43/ExA1/SRDY
Hysteresis
D0+, D0-, D1+, D1-, D2+, D2Hysteresis RESET
“H” input current
P00–P07, P24–P27, P50–P57, P60–P63
“H” input current
P10–P17, P30–P37, P40–P43
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P24–P27, P50–P57, P60–P63
“L” input current
P10–P17, P30–P37, P40–P43
“L” input current RESET, CNVSS, CNVSS2
“L” input current XIN
“L” input current P00–P07, P50, P52
(Pull-ups “on”)
VT+–VT-
VT+–VT
VT+–VTIIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
VRAM
RAM hold voltage
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 131 of 147
Test conditions
IOH = –10 mA
(Vcc = 4.00 to 5.25 V)
IOH = –1 mA
IOH = –10 mA (VCCE =
4.00 to 5.25 V)
IOH = –1 mA
D+ and D- pins pulldown with 0 V via a
resistor of 15 kΩ ± 5 %
IOL = 10 mA
(Vcc = 4.00 to 5.25 V)
IOL = 1 mA
IOL = 20 mA
(Vcc = 4.00 to 5.25 V)
IOL = 1 mA
IOL = 10 mA (VCCE =
4.00 to 5.25 V)
IOL = 1 mA (VCCE =
3.00 to 5.25 V)
D+ and D- pins pull-up
with 3.6 V via a resistor
of 1.5 kΩ ± 5 %
Min.
VCC–2.0
Limits
Typ.
Max.
Unit
V
VCC–1.0
V
V
VCCE–2.0
V
VCCE–1.0
2.8
0
3.6
V
2.0
V
1.0
2.0
V
V
1.0
2.0
V
1.0
V
0.3
V
V
0.6
V
0.6
V
0.25
V
0.5
VI = VCC (Pull-ups “off”)
5.0
V
µA
VI = VCCE
5.0
µA
5.0
µA
VI = VCC
VI = VCC
VI = VSS (Pull-ups “off”)
µA
4.0
–5.0
µA
VI = VSS
–5.0
µA
VI = VSS
VI = VSS
VI = VSS
(Vcc = 4.00 to 5.25 V)
VI = VSS
When clock is stopped
–5.0
µA
–120.0
µA
5.25
µA
V
–20.0
–10.0
2.00
–4.0
–60.0
µA
38K2 Group (L Ver.)
Table 20 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ICC
Test conditions
Parameter
Power source current
(Output transistor is
isolated.)
Normal
mode
(Note 1)
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 4.00 V
Wait
mode
(Note 2)
Vcc = 3.00
to 3.60 V
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 4.00 V
Stop
mode
(Note 3)
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 5.25 V
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, CPU, Timers
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, Timers, USB receiving
Disabled functions: CPU
3: Operating in single-chip mode with Stop mode
Oscillation stopped
All USB difference-input circuits disabled
Leaving I/O pins open
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 132 of 147
f(XIN) = system clock = 12 MHz,
φ = 6 MHz,
USB reference voltage circuit enabled
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = 6 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
USB reference voltage circuit enabled
Low current mode
USB reference voltage circuit disabled
Ta = 25 °C
USB reference voltage circuit disabled
Ta = 85 °C
Min.
Limits
Typ.
21.0
Max.
60
22.5
60
mA
22.0
60
mA
21.0
60
mA
35
mA
30
mA
9.0
Unit
mA
6.0
mA
2.0
mA
125.0
250
µA
µA
0.1
10
µA
38K2 Group (L Ver.)
Table 21 A/D Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
—
Resolution
—
Linearity error
—
Differential nonlinear error
Ta = 25 °C
Ta = 25 °C
VOT
Zero transition voltage
VCC = VREF = 5.12 V
0
VFST
Full scale transition voltage
VCC = VREF = 5.12 V
5105
tCONV
Conversion time
RLADDER
Ladder resistor
IVREF
Reference power source input current
A/D port input current
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 133 of 147
Max.
50
Unit
10
Bits
±3
±1.5
LSB
LSB
15
35
mV
5125
5150
mV
122
tc(XIN)
or
tc(fSYN)
kΩ
200
µA
5
5.0
µA
35
A/D converter operating; VREF = 5.0 V
A/D converter not operating; VREF = 5.0 V
II(AD)
Limits
Typ.
150
38K2 Group (L Ver.)
Timing Requirements
Table 22 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
Main clock input cycle time
83
ns
tWH(XIN)
Main clock input “H” pulse width
35
ns
tWL(XIN)
Main clock input “L” pulse width
35
ns
tC(CNTR)
CNTR0 input cycle time
200
ns
tWH(CNTR)
CNTR0 input “H” pulse width
80
ns
tWL(CNTR)
CNTR0 input “L” pulse width
80
ns
tWH(INT)
INT0, INT1 input “H” pulse width
80
ns
tWL(INT)
INT0, INT1 input “L” pulse width
80
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
800
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
370
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
370
ns
tsu(RxD–SCLK)
Serial I/O input set up time
220
ns
th(SCLK–RxD)
Serial I/O input hold time
100
ns
µs
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Table 23 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
Main clock input cycle time
166
ns
tWH(XIN)
Main clock input “H” pulse width
70
ns
tWL(XIN)
Main clock input “L” pulse width
70
ns
tC(CNTR)
CNTR0 input cycle time
500
ns
tWH(CNTR)
CNTR0 input “H” pulse width
230
ns
tWL(CNTR)
CNTR0 input “L” pulse width
230
ns
Typ.
Max.
µs
tWH(INT)
INT0, INT1 input “H” pulse width
230
ns
tWL(INT)
INT0, INT1 input “L” pulse width
230
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
2000
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
950
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
950
ns
tsu(RxD–SCLK)
Serial I/O input set up time
400
ns
th(SCLK–RxD)
Serial I/O input hold time
200
ns
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 134 of 147
38K2 Group (L Ver.)
Table 24 Timing requirements of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Unit
tsu(S-R)
ExCS setup time for read
Min.
0
tsu(S-W)
ExCS setup time for write
0
ns
th(R-S)
ExCS hold time for read
0
ns
th(W-S)
ExCS hold time for write
0
ns
tsu(A-R)
ExA0, ExA1 setup time for read
10
ns
tsu(A-W)
ExA0, ExA1 setup time for write
10
ns
th(R-A)
ExA0, ExA1 hold time for read
0
ns
th(W-A)
ExA0, ExA1 hold time for write
0
ns
tsu(ACK-R)
ExDACK setup time for read
10
ns
tsu(ACK-W)
ExDACK setup time for write
10
ns
th(R-ACK)
ExDACK hold time for read
0
ns
th(W-ACK)
ExDACK hold time for write
0
ns
tWH(R)
Read “H” pulse width
80
ns
tWL(R)
Read “L” pulse width
80
ns
tWH(W)
Write “H” pulse width
80
ns
tWL(W)
Write “L” pulse width
80
ns
Typ.
Max.
ns
tWH(ACK)
ExDACK “H” pulse width
120
ns
tWL(ACK)
ExDACK “L” pulse width
120
ns
tsu(D-W)
Data input setup time before write
40
ns
th(W-D)
Data input hold time after write
0
ns
tsu(D-ACK)
Data input setup time before ExDACK
60
ns
th(ACK-W)
Data input hold time after ExDACK
5
ns
tC(φ)
CPU clock cycle time
125
ns
tW(cycle)
Burst mode access cycle time
USB function not operating
tC(φ)•3+10
ns
USB function operating
tC(φ)•5+10
ns
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 135 of 147
38K2 Group (L Ver.)
Table 25 Timing requirements of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Unit
tsu(S-R)
ExCS setup time for read
Min.
0
tsu(S-W)
ExCS setup time for write
0
ns
th(R-S)
ExCS hold time for read
0
ns
th(W-S)
ExCS hold time for write
0
ns
tsu(A-R)
ExA0, ExA1 setup time for read
30
ns
tsu(A-W)
ExA0, ExA1 setup time for write
30
ns
th(R-A)
ExA0, ExA1 hold time for read
0
ns
th(W-A)
ExA0, ExA1 hold time for write
0
ns
tsu(ACK-R)
ExDACK setup time for read
30
ns
tsu(ACK-W)
ExDACK setup time for write
30
ns
th(R-ACK)
ExDACK hold time for read
0
ns
th(W-ACK)
ExDACK hold time for write
0
ns
tWH(R)
Read “H” pulse width
120
ns
tWL(R)
Read “L” pulse width
120
ns
tWH(W)
Write “H” pulse width
120
ns
tWL(W)
Write “L” pulse width
120
ns
Typ.
Max.
ns
tWH(ACK)
ExDACK “H” pulse width
160
ns
tWL(ACK)
ExDACK “L” pulse width
160
ns
tsu(D-W)
Data input setup time before write
60
ns
th(W-D)
Data input hold time after write
0
ns
tsu(D-ACK)
Data input setup time before ExDACK
80
ns
th(ACK-W)
Data input hold time after ExDACK
10
ns
tC(φ)
CPU clock cycle time
166
ns
tW(cycle)
Burst mode access cycle time
USB function not operating
tC(φ)•3+30
ns
USB function operating
tC(φ)•5+30
ns
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 136 of 147
38K2 Group (L Ver.)
Switching Characteristics
Table 26 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–30
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–30
ns
td(SCLK–TxD)
Serial I/O output delay time
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
30
ns
tf(SCLK)
Serial I/O clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note)
30
ns
tf(CMOS)
CMOS output falling time (Note)
30
ns
140
ns
ns
–30
Notes: Pins XOUT, D0+, D0-, D1+, D2-, D2+, D2- are excluded.
Table 27 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–50
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–50
ns
td(SCLK–TxD)
Serial I/O output delay time
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
50
ns
tf(SCLK)
Serial I/O clock output falling time
50
ns
tr(CMOS)
CMOS output rising time (Note)
50
ns
tf(CMOS)
CMOS output falling time (Note)
50
ns
Notes: Pins XOUT, D0+, D0-, D1+, D2-, D2+, D2- are excluded.
Measured output pin
100 pF
CMOS output
Fig. 168 Output switching characteristics measurement circuit
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 137 of 147
350
ns
ns
–30
38K2 Group (L Ver.)
Table 28 Switching characteristics of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
ta(R-D)
Data output enable time after read
tv(R-D)
Data output disable time after read
ta(ACK-D)
Data output enable time after ExDACK
tv(ACK-D)
Data output disable time after ExDACK
td(R-Mdis)
In cycle mode
Mch_req disable output delay time after read
tC(φ)+10
ns
td(W-Mdis)
In cycle mode
Mch_req disable output delay time after write
tC(φ)+10
ns
td(R-Men)
In cycle mode
Mch_req enable output delay time after read
tC(φ)•3+10
tC(φ)•5+10
ns
ns
tC(φ)•3+10
tC(φ)•5+10
ns
ns
td(W-Men)
In cycle mode
Mch_req enable output delay time after write
60
ns
ns
0
80
ns
ns
0
USB function not operating
USB function operating
USB function not operating
USB function operating
Table 29 Switching characteristics of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
ta(R-D)
Data output enable time after read
tv(R-D)
Data output disable time after read
ta(ACK-D)
Data output enable time after ExDACK
tv(ACK-D)
Data output disable time after ExDACK
td(R-Mdis)
In cycle mode
Mch_req disable output delay time after read
tC(φ)+30
ns
td(W-Mdis)
In cycle mode
Mch_req disable output delay time after write
tC(φ)+30
ns
td(R-Men)
In cycle mode
Mch_req enable output delay time after read
tC(φ)•3+30
tC(φ)•5+30
ns
ns
td(W-Men)
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+30
tC(φ)•5+30
ns
ns
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 138 of 147
80
120
USB function operating
USB function not operating
USB function operating
ns
ns
0
USB function not operating
ns
ns
0
38K2 Group (L Ver.)
Table 30 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
tfr(D+/D-)
USB full-speed output rising time
CL = 50 pF
4
20
ns
tff(D+/D-)
USB full-speed output rising time
CL = 50 pF
4
20
ns
tlr(D+/D-)
USB low-speed output rising time
CL = 200 to 600 pF
75
300
ns
75
300
ns
65
300
ns
75
300
ns
75
300
ns
65
300
ns
Ta = 0 to 85 °C
CL = 250 to 600 pF
Ta = –20 to 85 °C
CL = 200 to 600 pF
Ta = –20 to 85 °C
tlf(D+/D-)
USB low-speed output falling time
CL = 200 to 600 pF
Ta = 0 to 85 °C
CL = 250 to 600 pF
Ta = –20 to 85 °C
CL = 200 to 600 pF
Ta = –20 to 85 °C
tfrfm(D+/D-)
USB full-speed ports rising/falling ratio
tfr(D+/D-)/tff(D+/D-)
90
111.11
%
tlrfm(D+/D-)
USB low-speed ports rising/falling ratio
tlr(D+/D-)/tff(D+/D-)
80
125
%
Vcrs(D+/D-)
USB output signal cross-over voltage
1.3
2.0
V
TrON
RL = 27 Ω
RL = 1.5 kΩ
Measured output pin
RL = 27 Ω
RL = 15 kΩ
CL
Measured output pin
RL = 15 kΩ
CL
USB port output
USB port output
Fig. 169 USB output switching characteristics measurement circuit
(1) for D0-, D1+/D2+ (low-speed), D1-/D2- (full-speed)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 139 of 147
Fig. 170 USB output switching characteristics measurement circuit
(2) for D0+, D1+/D2+ (full-speed), D1-/D2- (low-speed)
38K2 Group
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
CNTR0
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0/INT1
0.2VCC
tW(RESET)
RESET
0.8
VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
[Serial I/O]
tC(SCLK)
tf
tWL(SCLK)
SCLK
tWH(SCLK)
0.8VCCE
0.2VCCE
tsu(RxD-SCLK)
th(SCLK-RxD)
0.8VCCE
0.2VCCE
RxD(at receive)
td(SCLK-TxD)
TxD (at transmit)
Fig. 171 Timing chart (1)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
tr
page 140 of 147
tv(SCLK-TxD)
38K2 Group
● Timing chart
[ EXB <CPU channel mode> ]
< Read >
tsu(A-R)
ExA0, ExA1
th(R-A)
0.8VCC
0.2VCC
tsu(S-R)
ExCS
th(R-S)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
< Write >
tsu(A-W)
ExA0, ExA1
th(W-A)
0.8VCC
0.2VCC
tsu(S-W)
ExCS
th(W-S)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
Fig. 172 Timing chart (2)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 141 of 147
0.8VCC
0.2VCC
th(W-D)
0.8VCC
0.2VCC
38K2 Group
● Timing chart
[ EXB <Memory channel mode, Normal port function> ]
< Read >
tsu(A-R)
ExA0, ExA1
th(R-A)
0.8VCC
0.2VCC
tsu(S-R)
ExCS
th(R-S)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Men)
td(R-Mdis)
ExINT(Mch_req)
0.2VCC
0.2VCC
< Write >
tsu(A-W)
ExA0, ExA1
th(W-A)
0.8VCC
0.2VCC
tsu(S-W)
ExCS
th(W-S)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
0.8VCC
0.2VCC
td(W-Mdis)
ExINT(Mch_req)
0.2VCC
Fig. 173 Timing chart (3)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 142 of 147
th(W-D)
0.8VCC
0.2VCC
td(W-Men)
0.2VCC
38K2 Group
● Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals used together mode> ]
< Read >
tsu(ACK-R)
ExDACK
th(R-ACK)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
td(R-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
< Write >
tsu(ACK-W)
ExDACK
th(W-ACK)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
0.8VCC
0.2VCC
td(W-Mdis)
ExDREQ(Mch_req)
Fig. 174 Timing chart (4)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 143 of 147
0.2VCC
th(W-D)
0.8VCC
0.2VCC
td(W-Men)
0.2VCC
38K2 Group
● Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals not required mode> ]
< Read >
twL(ACK)
ExDACK
DQ0 to DQ7
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
ta(ACK-D)
tv(ACK-D)
td(ACK-Mdis)
ExDREQ(Mch_req)
td(ACK-Men)
0.2VCC
0.2VCC
twL(ACK)
< Write >
ExDACK
0.8VCC
0.2VCC
tsu(D-ACK)
DQ0 to DQ7
ExDREQ(Mch_req)
Fig. 175 Timing chart (5)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 144 of 147
th(ACK-D)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
td(ACK-Mdis)
td(ACK-Men)
0.2VCC
0.2VCC
38K2 Group
● Timing chart
[ EXB <Memory channel mode, Burst transfer> ]
< Read >
ExDACK
twL(R) twH(R)
ExRD
0.8VCC
0.2VCC
tw(cycle)
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
ExDREQ(Mch_req)
0.2VCC
< Write >
ExDACK
twL(W) twH(W)
ExWR
0.8VCC
0.2VCC
tw(cycle)
DQ0 to DQ7
tsu(D-W)
th(W-D)
td(W-Mdis)
ExDREQ(Mch_req)
Fig. 176 Timing chart (6)
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 145 of 147
0.2VCC
38K2 Group
PACKAGE OUTLINE
PLQP0064GA-A
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
*3
Detail F
bp
page 146 of 147
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
38K2 Group
PLQP0064KB-A
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
HE
64
1
c
Reference
Symbol
Terminal cross section
ZE
17
c1
*2
E
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
L
x
L1
Detail F
Rev.3.00 Oct 15, 2006
REJ03B0193-0300
page 147 of 147
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
REVISION HISTORY
Rev.
38K2 GROUP DATA SHEET
Date
Description
Summary
Page
1.0
7/6/01
1.1
7/19/01
2.0
2/14/02
First edition issued
26
Fig.24: VREFCON.....1: Low current mode
64
P41/ExDACK/TxD pin
P42/ExTC/SCLK pin
68
Fig.102: INT_CTR.....0 0 1: RxB_RDY
1
Some Features are revised: Power source voltage, Power dissipation, Operating
temperature range.
Fig.1: The design of top view is revised.
3
Table 1: The Function of Vcc, VccE and USBVREF is revised.
5
100D0M package is added.
Table 2: The product M38K29RFS is added.
9
25–30
Fig. 7: The description of system clock division ratio selection bits is revised.
The explanations from pages 25 to 30 are added.
31
Fig. 29: In (6) Endpoint 11 Bit name of EP11REQ is revised.
32
Fig. 31: The Function is revised.
50
Fig. 70: The Function is revised.
57–60
The explanations from pages 57 to 60 are added.
75
Fig. 106: Bit name of EXBIREQ. is revised:
76
Fig. 108: Note is added.
Fig. 109: Bit attributes are revised.
78
Fig. 114: Register symbol is revised.
90
The explanations of A-D converter are revised.
93
The voltages regarding RESET is revised.
94
The clock frequency regarding PLL is revised.
98
Fig. 144 is added.
99
The explanations of FLASH MEMORY MODE and Table 9 are revised.
100
The explanations of Microcomputer Mode and Boot Mode, and Fig.145 are revised.
103
The explanations of Operation speed are revised.
110
The explanations of (2) Parallel I/O Mode are revised.
111
The explanations of (3) Standard Serial I/O Mode are revised.
112
Table 12: The Function of VccE, CNVss, P10 to P15, P16 and P17 is revised.
113
Fig. 153: The descriptions of CE and SCLK are added.
124
Fig. 165: P16 (CE) is added.
125
The explanations of Instruction Execution Time are revised.
126
The explanations of Definition of A-D Conversion Accuracy is added.
(1/3)
REVISION HISTORY
Rev.
38K2 GROUP DATA SHEET
Date
Description
Summary
Page
2.0
2/14/02
127
The explanations are added: USB Port Pins, USBVREF pin Treatment and Electric
Characteristic Differences Between Mask ROM and Flash Memory Version MCUs.
128
Table 16: Operating temperature is revised.
129
Table 17: Measuring conditions, Power source voltage Vcc and Analog power source
voltage VccE are revised. Analog power source voltage USBVREF is
added.
130
Table 18: Measuring conditions, f(XIN) and Notes 1 and 2 are revised. [f(XIN) or
f(SYN)] and f(φ) are added.
131
Table 19: Measuring conditions and some of VOH, VOL, VT+–VT- and IIL are revised or added.
132
Table 20: The information are revised.
133
Table 21: Measuring conditions and IVREF are revised.
134 to 136 Tables 22 to 26: The information are revised or added.
Figures 168 and 169 are added.
136
2.1
2.2
2.3
2/18/02
3/05/02
10/09/02
All pages The symbol “PRELIMINARY” is deleted from the header.
94
Some explanations of PLL CIRCUIT are deleted.
112
Table 12: Vcc apply voltage is revised.
137
Fig. 170: The symbols in SCLK and RxD are revised.
1
FEATURES: USB specification ver.1.1→ Full-Speed USB2.0 specification
Power source voltage: Standard and L version are indicated respectively.
Power dissipation(at 3.3V): 45mW→ 30mW
2. of Notes is deleted.
Fig. 1: Product name of L version is added.
3
Table 1: Vcc and USBREF are revised.
5
Fig. 4: L version is added.
Table 3 is added. Subsequent table numbers are changed.
16
Table 7: Key-on wake up is revised.
27
Fig. 25: Tytle: Vcc condition is added. Condensers are added.
Fig. 26 is added. Subsequent figure numbers are changed.
31
Fig. 30: EP00 transmit/receive byte number register→EP00 byte number register,
EP10 transmit/receive byte number register→EP10 byte number register,
EP11 transmit byte number register→EP11 byte number register
39
Fig. 45: EP00 transmit/receive byte number register→EP00 byte number register
54
Fig. 79: EP10 transmit/receive byte number register→EP10 byte number register
56
Fig. 85: EP11 transmit byte number register→EP11 byte number register
59
Fig. 89, Fig. 90: Capacitors and resistors are added.
67
Fig. 100: Function of bit 0 to bit 3 is revised.
(2/3)
REVISION HISTORY
Rev.
38K2 GROUP DATA SHEET
Date
Description
Summary
Page
2.3
10/09/02
93
Power source voltage and reset input voltage of Standard and L version are indicated.
Fig. 137:Reset release voltage of Standard and L version are indicated.
3.0
10/15/06
99
Table 10: Vcc of Standard and L version are indicated.
112
Tbale 13:Vcc of Standard and L version are indicated.
113
Fig. 154: Product name of L version is added. Vcc when connect to Vpp is revised.
129 --
Electrical characteristics of Standard and L version are indicated respectively (Those
of L version are indicated from page 137).
Table 18 to Tbale 23: Tytle: Vcc=3.00 to 5.25 V →Vcc=4.00 to 5.25 V, Vcc when
system clock 6MHz is deleted, 2,4-divide mode when system clock 12MHz is deleted.
129
Vcc when system clock 8MHz→Vcc when system clock ≤ 8MHz
USBVREF is deleted.
130
Table 19:Vcc conditions of f(XIN), f(XIN) or f(SYN), and f(φ) are deleted. Data when
Vcc=3.00 to 4.00 V is deleted. Notes 4 is revised.
131
Table 20: Indications of Vcc and VccE in Test conditions are deleted. Data when
VI=VSS in IIL pull-up is deleted.
132
Table 21: Ranges of Vcc in Test conditions are deleted. Data when Vcc= 3.00 to
4.00 V is deleted. Typ. in normal mode are revised.
134
Timing requirements table when Vcc= 3.00 to 4.00 V is deleted.
Table 24 is added.
135
Switching characteristics table when Vcc= 3.00 to 4.00 V is deleted.
Table 26 is added.
136
Table 27: Tytle: Vcc=3.00 to 5.25 V→Vcc 4.00 to 5.25V
137 --
Electrical characteristics and switching characteristics of L version are added.
149 --
Timing chart (2) to (6) are added.
All pages Package names “64P6U-A” → “PLQP0064GA-A” revised
Package names “64P6Q-A” → “PLQP0064KB-A” revised
38K2 group (Standard) deleted
Fig. 137 revised
93
CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor ex96
ists on-chip.” → “No external resistor is needed .... depending on conditions.)
Fig. 141; Pulled up added, NOTE added
97
Fig. 144 revised
NOTES ON USAGE; Power Source Voltage, USB Communication added
127
Package outline revised
154
(3/3)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0
Similar pages