FAIRCHILD 74F779SCX

Revised March 2000
74F779
8-Bit Bidirectional Binary Counter with 3-STATE Outputs
General Description
Features
The 74F779 is a fully synchronous 8-stage up/down
counter with multiplexed 3-STATE I/O ports for bus-oriented applications. All control functions (hold, count up,
count down, synchronous load) are controlled by two mode
pins (S0, S1). The device also features carry lookahead for
easy cascading. All state changes are initiated by the rising
edge of the clock.
■ Multiplexed 3-STATE I/O ports
■ Built-in lookahead carry capability
■ Count frequency 100 MHz typ
■ Supply current 80 mA typ
■ Available in SOIC (300 mil only)
Ordering Code:
Order Number
Package Number
Package Description
74F779SC
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F779PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
Connection Diagram
DS009593
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74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
April 1988
74F779
Unit Loading/Fan Out
Pin Names
Description
I/O0–I/O7
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
0.25/0.33
5 µA/−0.2 mA
Data Outputs
75/15 (12.5)
−3 mA/24 mA (20 mA)
5 µA/−0.2 mA
Data Inputs
S0, S1
Select Inputs
0.25/0.33
OE
Output Enable Input (Active LOW)
0.25/0.33
5 µA/−0.2 mA
CET
Count Enable Trickle Input (Active LOW)
0.25/0.33
5 µA/−0.2 mA
CP
Clock Pulse Input (Active Rising Edge)
0.25/0.33
5 µA/−0.2 mA
TC
Terminal Count Output (Active LOW)
25/12.5
−1 mA/20 mA
Function Table
S1
S0
CET
OE
CP
X
X
X
H
X
X
X
X
L
L
L
X
H
H
X
H
(Not LL)
L
L
X
L
H
L
X
Function
I/O0 to I/O7 in High Z
X
Flip-Flop Outputs Appear on I/O Lines
Parallel Load All Flip-Flops
Hold (TC Held HIGH)
Count Up
Count Down
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
(Not LL) means S0 and S 1 should never both be LOW level at the same time.
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2
74F779
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F779
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current ((Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
in LOW State (Max)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
IIN = −18 mA
VOH
Output HIGH
V
Min
IOH = −3 mA
V
Min
5.0
µA
Max
VIN = 2.7V (Non-I/O Pins)
7.0
µA
Max
VIN = 7.0V (Non-I/O Pins)
0.5
mA
Max
VIN = 5.5V (I/On)
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
0.0
VOL
Output LOW
Voltage
IIH
IBVI
10% VCC
2.4
5% VCC
2.7
V
Conditions
Input HIGH Voltage
Voltage
2.0
Units
VIH
10% VCC
0.5
5% VCC
0.5
Input HIGH Current
Input HIGH Current
Breakdown Test
IBVIT
Input HIGH Current
Breakdown (I/O)
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
4.75
Output Leakage
Circuit Current
Recognized as a HIGH Signal
Recognized as a LOW Signal
IOL = 20 mA
IOL = 20 mA
IID = 1.9 µA
All other pins grounded
VIOD = 150 mV
All other pins grounded
IZZ
Bus Drainage Test
500
µA
IIL
Input LOW Current
−0.2
mA
Max
VIN = 0.5V (Non I/O Pins)
IIH + IOZH
Output Leakage Current
70
µA
Max
VOUT = 2.7V (I/On)
IIL + IOZL
Output Leakage Current
−200
µA
Max
VOUT = 0.5V (I/On)
IOS
Output Short-Circuit Current
−150
mA
Max
VOUT = 0V
ICCH
Power Supply Current
90
mA
Max
VO = HIGH
ICCL
Power Supply Current
105
mA
Max
VO = LOW
ICCZ
Power Supply Current
110
mA
Max
VO = HIGH Z
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−60
4
VOUT = 5.25V
74F779
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Typ
fMAX
Maximum Clock Frequency
100
105
Max
Min
Units
Max
90
tPLH
Propagation Delay
3.0
5.0
8.0
3.0
8.5
tPHL
CP to I/On
5.0
7.5
11.0
5.0
11.0
tPLH
Propagation Delay
5.0
7.5
9.0
5.0
10.0
tPHL
CP to TC
5.0
9.3
10.5
5.0
11.5
tPLH
Propagation Delay
2.5
3.8
5.5
2.5
6.0
tPHL
CET to TC
4.5
6.1
8.0
4.5
8.5
tPLH
Propagation Delay
3.5
6.5
12.0
3.5
13.0
tPHL
SN to TC
3.5
7.5
12.0
3.5
13.0
tPZH
Output Enable Time
3.0
5.0
7.0
3.0
8.0
tPZL
OE to I/On
5.0
8.0
10.0
5.0
10.5
tPHZ
Output Disable Time
1.0
4.0
6.5
1.0
7.0
tPLZ
OE to I/On
1.0
3.7
6.5
1.0
7.0
ns
ns
ns
ns
ns
ns
AC Operating Requirements
TA = +25°C
Symbol
VCC = +5.0V
Parameter
Min
Max
TA = 0°C to +70°C
VCC = +5.0V
Min
tS(H)
Setup Time
5.0
5.0
tS(L)
I/On to CP
5.0
5.0
tH(H)
Hold Time
0.0
0.0
tH(L)
I/On to CP
0.0
0.0
tS(H)
Setup Time
9.5
10.0
tS(L)
Sn to CP
9.5
10.0
tH(H)
Hold Time
0.0
0.0
tH(L)
Sn to CP
0.0
0.0
tS(H)
Setup Time
7.0
7.0
tS(L)
CET to CP
7.0
7.0
tH(H)
Hold Time
0.0
0.0
tH(L)
CET to CP
0.0
0.0
tW(H)
Clock Pulse Width
4.0
4.0
tW(L)
HIGH or LOW
4.0
4.0
5
Units
Max
ns
ns
ns
ns
ns
ns
ns
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74F779
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
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6
74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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