Elpida MC-458CB642XS-A75 8m-word by 64-bit synchronous dynamic ram module (so dimm) Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CB642XS
8M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
EO
The MC-458CB642XS is 8,388,608 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on
which 4 pieces of 128M SDRAM: µPD45128163 are assembled.
This module provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
L
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency (MAX.)
Access time from CLK (MAX.)
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6 ns
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6 ns
MC-458CB642XS-A75
Pr
MC-458CB642XS-A75L
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
od
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length: 1, 2, 4, 8 and Full Page
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
t
uc
• Single 3.3 V ± 0.3 V power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0115N20 (Ver. 2.0)
Date Published September 2001 (K)
Printed in Japan
This product became EOL in March, 2004.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-458CB642XS
Ordering Information
Part number
Clock frequency
Package
Mounted devices
MHz (MAX.)
MC-458CB642XS-A75
MC-458CB642XS-A75L
133 MHz
133 MHz
144-pin Small Outline DIMM
4 pieces of µPD45128163G5 (Rev. X)
(Socket Type)
(10.16 mm (400) TSOP (II))
Edge connector: Gold plated
25.4 mm height
L
EO
t
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od
Pr
2
Data Sheet E0115N20
MC-458CB642XS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
Vss
DQ 0
DQ 1
DQ 2
DQ 3
VCC
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB0
DQMB1
VCC
A0
A1
A2
Vss
DQ 8
DQ 9
DQ 10
DQ 11
VCC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
L
EO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CLK0
CKE0
Vcc
Vcc
/RAS
/CAS
/WE
NC
/CS0
NC
NC
NC
NC
CLK1
Vss
Vss
NC
NC
NC
NC
VCC
Vcc
DQ 16
DQ 48
DQ 17
DQ 49
DQ 18
DQ 50
DQ 19
DQ 51
Vss
Vss
DQ 20
DQ 52
DQ 21
DQ 53
DQ 22
DQ 54
DQ 23
DQ 55
Vcc
Vcc
A6
A7
A8
BA0 (A13)
Vss
Vss
A9
BA1 (A12)
A10
A11
Vcc
Vcc
DQMB2
DQMB6
DQMB3
DQMB7
Vss
Vss
DQ 24
DQ 56
DQ 25
DQ 57
DQ 26
DQ 58
DQ 27
DQ 59
VCC
Vcc
DQ 28
DQ 60
DQ 29
DQ 61
DQ 30
DQ 62
DQ 31
DQ 63
Vss
Vss
SDA
SCL
VCC
Vcc
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
/xxx indicates active low signal.
Pr
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0 (A13), BA1 (A12) : SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0, CLK1
: Clock Input
od
Data Sheet E0115N20
CKE0
: Clock Enable Input
/CS0
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SDA
SCL
VCC
VSS
NC
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62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
: No Connection
3
MC-458CB642XS
Block Diagram
/WE
/CS0
/CS
LDQM
DQMB0
DQ 0
/WE
LDQM
DQMB4
DQ 32
DQ 0
DQ 1
DQ 1
DQ 33
DQ 1
DQ 2
DQ 2
DQ 34
DQ 2
DQ 3
DQ 3
DQ 35
DQ 3
DQ 4
DQ 4
DQ 36
DQ 4
DQ 5
DQ 5
DQ 37
DQ 5
DQ 6
DQ 6
DQ 38
DQ 6
DQ 7
DQ 7
DQ 39
DQ 7
UDQM
EO
DQ 0
D0
UDQM
DQMB1
DQ 8
DQ 15
DQMB5
DQ 40
DQ 9
DQ 14
DQ 41
DQ 14
DQ 10
DQ 13
DQ 42
DQ 13
DQ 11
DQ 12
DQ 43
DQ 12
DQ 12
DQ 11
DQ 44
DQ 11
DQ 13
DQ 10
DQ 45
DQ 10
DQ 14
DQ 9
DQ 46
DQ 9
DQ 15
DQ 8
DQ 47
DQ 8
L
/CS
LDQM
/WE
LDQM
DQMB6
DQ 48
DQ 7
DQ 17
DQ 6
DQ 49
DQ 6
DQ 18
DQ 5
DQ 50
DQ 5
DQ 19
DQ 4
DQ 51
DQ 4
DQ 20
DQ 3
DQ 52
DQ 3
DQ 21
DQ 2
DQ 22
DQ 1
DQ 23
DQ 0
Pr
DQ 7
UDQM
DQMB3
DQ 8
DQ 25
DQ 9
DQ 26
DQ 10
DQ 27
DQ 11
DQ 28
DQ 12
DQ 29
DQ 13
DQ 30
DQ 14
DQ 31
DQ 15
DQ 53
DQ 2
DQ 54
DQ 1
DQ 55
DQ 0
SERIAL PD
/WE
/CS
D3
UDQM
DQMB7
DQ 56
DQ 8
DQ 57
DQ 9
DQ 58
DQ 10
DQ 59
DQ 11
DQ 60
DQ 12
DQ 61
DQ 13
DQ 62
DQ 14
DQ 63
DQ 15
od
DQ 24
D2
DQ 15
DQMB2
DQ 16
D1
/WE
/CS
VCC
D0 - D3
C
SDA
A0
A1
10 Ω
A2
CLK0
CLK : D0 - D3
/RAS
A0 - A11
A0 - A11 : D0 - D3
BA0
A13 : D0 - D3
BA1
A12 : D0 - D3
Remarks 1. D0 - D3: µPD45128163 (2M words x 16 bits x 4 banks)
2. The value of all resistors is 10 Ω.
4
D0 - D3
t
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SCL
VSS
Data Sheet E0115N20
/CAS
CKE0
CLK1
10 pF
/RAS : D0 - D3
/CAS : D0 - D3
CKE : D0 - D3
MC-458CB642XS
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
4
W
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
EO
Voltage on power supply pin relative to GND
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
L
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Condition
VCC
Low level input voltage
Operating ambient temperature
Pr
High level input voltage
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
VIH
2.0
VCC + 0.3
V
VIL
–0.3
+0.8
V
TA
0
70
°C
MAX.
Unit
pF
Capacitance (TA = 25 °C, f = 1 MHz)
Input capacitance
Symbol
CI1
od
Parameter
Test condition
MIN.
TYP.
A0 - A11, BA0 (A13), BA1 (A12),
15
30
/RAS, /CAS, /WE
CLK0
23
37
CI3
CKE0
15
26
CI4
/CS0
15
26
CI5
DQMB0 - DQMB7
5
10
CI/O
DQ0 - DQ63
5
12
Data Sheet E0115N20
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Data input/output capacitance
CI2
pF
5
MC-458CB642XS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
ICC1
Precharge standby current in
power down mode
Precharge standby current in
ICC2P
ICC2PS
ICC2N
non power down mode
EO
power down mode
Active standby current in
ICC3P
ICC3PS
ICC3N
non power down mode
Operating current
Burst length = 1, tRC ≥ tRC (MIN.)
Unit
Notes
/CAS latency = 2
440
mA
1
/CAS latency = 3
460
4
CKE ≤ VIL (MAX.), tCK = ∞
4
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
80
CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
32
CKE ≤ VIL (MAX.), tCK = 15 ns
20
CKE ≤ VIL (MAX.), tCK = ∞
16
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
120
mA
mA
mA
mA
Input signals are changed one time during 30 ns.
ICC3NS
ICC4
CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
80
tCK ≥ tCK (MIN.), IO = 0 mA
/CAS latency = 2
580
/CAS latency = 3
740
ICC5
/CAS latency = 2
920
/CAS latency = 3
960
tRC ≥ tRC (MIN.)
L
Self refresh current
MAX.
CKE ≤ VIL (MAX.), tCK = 15 ns
(Burst mode)
CBR (Auto) refresh current
MIN.
Input signals are changed one time during 30 ns.
ICC2NS
Active standby current in
Test condition
ICC6
CKE ≤ 0.2 V
mA
2
mA
3
-**
8
mA
-**L
3.2
mA
–4
+4
µA
+1.5
µA
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
Output leakage current
IO(L)
DOUT is disabled, VO = 0 to 3.6 V
–1.5
High level output voltage
VOH
IO = –4.0 mA
2.4
Low level output voltage
VOL
IO = +4.0 mA
Pr
Input leakage current
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
od
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
t
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6
Data Sheet E0115N20
MC-458CB642XS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
Input
2.4 V
1.4 V
0.4 V
L
EO
tCK
tCH
tAC
tOH
Output
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Pr
Data Sheet E0115N20
7
MC-458CB642XS
Synchronous Characteristics
Parameter
Clock cycle time
Access time from CLK
Symbol
-A75
Unit
MIN.
MAX.
Note
/CAS latency = 3
tCK3
7.5
(133 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
ns
/CAS latency = 3
tAC3
5.4
ns
1
/CAS latency = 2
tAC2
6
ns
1
CLK high level width
tCH
2.5
ns
CLK low level width
tCL
2.5
ns
/CAS latency = 3
tOH3
3
ns
1
/CAS latency = 2
tOH2
3
ns
1
tLZ
0
ns
/CAS latency = 3
tHZ3
3
5.4
ns
/CAS latency = 2
tHZ2
3
6
ns
Data-in setup time
tDS
1.5
ns
Data-in hold time
tDH
0.8
ns
Address setup time
tAS
1.5
ns
Address hold time
tAH
0.8
ns
CKE setup time
tCKS
1.5
ns
CKE hold time
tCKH
0.8
ns
CKE setup time (Power down exit)
tCKSP
1.5
ns
tCMS
1.5
ns
tCMH
0.8
ns
EO
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time
L
DQMB0 - DQMB7) setup time
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
od
Pr
Command (/CS0, /RAS, /CAS, /WE,
Z = 50 Ω
Output
50 pF
8
Data Sheet E0115N20
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Remark These specifications are applied to the monolithic device.
MC-458CB642XS
Asynchronous Characteristics
Parameter
Symbol
-A75
MIN.
Unit
MAX.
tRC
67.5
ns
REF to REF/ACT command period (Refresh)
tRC1
67.5
ns
ACT to PRE command period
tRAS
45
PRE to ACT command period
tRP
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
ns
ACT (one) to ACT (another) command period
tRRD
15
ns
Data-in to PRE command
/CAS latency = 3
tDPL3
8
ns
period
/CAS latency = 2
tDPL2
8
ns
Data-in to ACT (REF) command /CAS latency = 3
tDAL3
1CLK+22.5
ns
period (Auto precharge)
tDAL2
1CLK+20
ns
tRSC
2
CLK
tT
0.5
EO
ACT to REF/ACT command period (Operation)
/CAS latency = 2
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
Note
120,000
ns
30
ns
64
ms
1
L
Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
t
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Pr
Data Sheet E0115N20
9
MC-458CB642XS
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
0
Defines the number of bytes written into
80H
1
0
0
0
0
0
0
0
128 bytes
serial PD memory
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
09H
0
0
0
0
1
0
0
1
9 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
6
Data width
40H
0
1
0
0
0
0
0
0
64 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
9
CL = 3 Cycle time
-A75
75H
0
1
1
1
0
1
0
1
7.5 ns
10
CL = 3 Access time
-A75
54H
0
1
0
1
0
1
0
0
5.4 ns
11
DIMM configuration type
00H
0
0
0
0
0
0
0
0
None
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
10H
0
0
0
1
0
0
0
0
×16
14
Error checking SDRAM width
00H
0
0
0
0
0
0
0
0
None
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
22
SDRAM device attributes: General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A75
A0H
1
0
1
0
0
0
0
0
10 ns
24
CL = 2 Access time
-A75
60H
0
1
1
0
0
0
0
0
6 ns
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
20 ns
0
0
0
0
1
1
1
1
15 ns
L
EO
1
27
tRP (MIN.)
-A75
14H
28
tRRD (MIN.)
-A75
0FH
29
tRCD (MIN.)
-A75
14H
0
0
0
1
30
tRAS (MIN.)
-A75
2DH
0
0
1
0
31
Module bank density
10H
0
0
0
1
Data Sheet E0115N20
t
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10
00H
od
Pr
25-26
0
1
0
0
20 ns
1
1
0
0
45 ns
0
0
0
0
64M bytes
MC-458CB642XS
(2/2)
Byte No.
32
Function Described
Command and address
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
-A75
15H
0
0
0
1
0
1
0
1
1.5 ns
-A75
08H
0
0
0
0
1
0
0
0
0.8 ns
signal setup time
33
Command and address
signal hold time
34
Data signal input setup time
-A75
15H
0
0
0
1
0
1
0
1
1.5 ns
35
Data signal input hold time
-A75
08H
0
0
0
0
1
0
0
0
0.8 ns
00H
0
0
0
0
0
0
0
0
36-61
SPD revision
-A75
12H
0
0
0
1
0
0
1
0
63
Checksum for bytes 0 - 62
-A75
A6H
1
0
1
0
0
1
1
0
EO
62
64-71
72
1.2 A
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
91-92
Revision code
93-94
Manufacturing date
95-98
Assembly serial number
99-125
Mfg specific
L
73-90
126
Intel specification frequency
-A75
64H
0
1
1
0
0
1
0
0
127
Intel specification /CAS
-A75
87H
1
0
0
0
0
1
1
1
Timing Chart
Pr
latency support
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
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Data Sheet E0115N20
11
MC-458CB642XS
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
M1 (AREA B)
R
N
Q
EO
M2 (AREA A)
I
M
L
S
A
H
(OPTIONAL HOLES)
U1
U2
C
T
E
B
D
L
A1 (AREA A)
F
Pr
W
D1
A1
B
od
detail of A part
ITEM
A
D2
X
V
MILLIMETERS
67.6
67.6±0.15
23.2
C
29.0
D
4.6
D1
1.5±0.10
D2
4.0
E
F
32.8
3.7
H
0.8 (T.P.)
I
3.3
L
M
20.0
25.4±0.15
3.4
22.0
t
uc
M1
M2
N
12
Data Sheet E0115N20
3.8 MAX.
Q
R2.0
R
S
4.0±0.10
φ 1.8
T
1.0±0.1
U1
U2
3.2 MIN.
4.0 MIN.
V
0.25 MAX.
W
0.6±0.05
X
2.55 MIN.
Y
2.0 MIN.
MC-458CB642XS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
2
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EO
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
3
Pr
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
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Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0115N20
13
MC-458CB642XS
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
EO
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
L
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
M01E0107
t
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Pr
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
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