ONSEMI BCW72LT1

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by BCW72LT1/D
SEMICONDUCTOR TECHNICAL DATA
NPN Silicon
COLLECTOR
3
1
BASE
3
1
2
EMITTER
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector – Emitter Voltage
VCEO
45
Vdc
Collector – Base Voltage
VCBO
50
Vdc
Emitter – Base Voltage
VEBO
5.0
Vdc
IC
100
mAdc
Collector Current — Continuous
2
CASE 318 – 08, STYLE 6
SOT– 23 (TO – 236AB)
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation FR– 5 Board(1)
TA = 25°C
Derate above 25°C
PD
225
mW
1.8
mW/°C
Thermal Resistance, Junction to Ambient
RqJA
556
°C/W
PD
300
mW
2.4
mW/°C
RqJA
417
°C/W
TJ, Tstg
– 55 to +150
°C
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
BCW72LT1 = K2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Collector – Emitter Breakdown Voltage
(IC = 2.0 mAdc, VEB = 0)
V(BR)CEO
45
—
—
Vdc
Collector – Emitter Breakdown Voltage
(IC = 2.0 mAdc, VEB = 0)
V(BR)CES
45
—
—
Vdc
Collector – Base Breakdown Voltage
(IC = 10 mAdc, IE = 0)
V(BR)CBO
50
—
—
Vdc
Emitter – Base Breakdown Voltage
(IE = 10 mAdc, IC = 0)
V(BR)EBO
5.0
—
—
Vdc
—
—
—
—
100
10
nAdc
mAdc
OFF CHARACTERISTICS
Collector Cutoff Current
(VCB = 20 Vdc, IE = 0)
(VCB = 20 Vdc, IE = 0, TA = 100°C)
0.062 in.
0.024 in. 99.5% alumina.
ICBO
1. FR– 5 = 1.0
0.75
2. Alumina = 0.4 0.3
Thermal Clad is a trademark of the Bergquist Company
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 Motorola, Inc. 1996
1
BCW72LT1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
200
—
450
—
—
—
0.21
0.25
—
—
0.85
—
0.6
—
0.75
fT
—
300
—
MHz
Output Capacitance
(IE = 0, VCB = 10 Vdc, f = 1.0 MHz)
Cobo
—
—
4.0
pF
Input Capacitance
(IE = 0, VCB = 10 Vdc, f = 1.0 MHz)
Cibo
—
9.0
—
pF
NF
—
—
10
dB
ON CHARACTERISTICS
DC Current Gain
(IC = 2.0 mAdc, VCE = 5.0 Vdc)
hFE
—
Collector – Emitter Saturation Voltage
(IC = 10 mAdc, IB = 0.5 mAdc)
(IC = 50 mAdc, IB = 2.5 mAdc)
VCE(sat)
Base – Emitter Saturation Voltage
(IC = 50 mAdc, IB = 2.5 mAdc)
VBE(sat)
Base – Emitter On Voltage
(IC = 2.0 mAdc, VCE = 5.0 Vdc)
VBE(on)
Vdc
Vdc
Vdc
SMALL– SIGNAL CHARACTERISTICS
Current – Gain — Bandwidth Product
(IC = 10 mAdc, VCE = 5.0 Vdc, f = 100 MHz)
Noise Figure
(IC = 0.2 mAdc, VCE = 5.0 Vdc, RS = 2.0 kΩ, f = 1.0 kHz,
BW = 200 Hz)
EQUIVALENT SWITCHING TIME TEST CIRCUITS
+ 3.0 V
300 ns
DUTY CYCLE = 2%
+10.9 V
+ 3.0 V
10 < t1 < 500 µs
DUTY CYCLE = 2%
275
t1
+10.9 V
10 k
275
10 k
0
– 0.5 V
<1.0 ns
CS < 4.0 pF*
– 9.1 V
< 1.0 ns
CS < 4.0 pF*
1N916
*Total shunt capacitance of test jig and connectors
Figure 1. Turn–On Time
Figure 2. Turn–Off Time
TYPICAL NOISE CHARACTERISTICS
(VCE = 5.0 Vdc, TA = 25°C)
20
100
BANDWIDTH = 1.0 Hz
RS = 0
50
300 µA
10
In, NOISE CURRENT (pA)
en, NOISE VOLTAGE (nV)
IC = 1.0 mA
100 µA
7.0
5.0
10 µA
3.0
20
300 µA
100 µA
10
5.0
2.0
1.0
30 µA
0.5
30 µA
10 µA
0.2
2.0
0.1
10
20
50
100 200
500 1 k
f, FREQUENCY (Hz)
Figure 3. Noise Voltage
2
BANDWIDTH = 1.0 Hz
RS ≈ ∞
IC = 1.0 mA
2k
5k
10 k
10
20
50
100 200
500 1 k
f, FREQUENCY (Hz)
2k
5k
Figure 4. Noise Current
Motorola Small–Signal Transistors, FETs and Diodes Device Data
10 k
BCW72LT1
NOISE FIGURE CONTOURS
(VCE = 5.0 Vdc, TA = 25°C)
BANDWIDTH = 1.0 Hz
200 k
100 k
50 k
RS , SOURCE RESISTANCE (OHMS)
RS , SOURCE RESISTANCE (OHMS)
500 k
20 k
10 k
5k
2.0 dB
2k
1k
500
3.0 dB 4.0 dB
6.0 dB
10 dB
200
100
50
1M
500 k
BANDWIDTH = 1.0 Hz
200 k
100 k
50 k
20 k
10 k
1.0 dB
5k
2.0 dB
2k
1k
500
5.0 dB
200
100
10
20
30
50 70 100
200 300
IC, COLLECTOR CURRENT (µA)
500 700
1k
8.0 dB
10
20
Figure 5. Narrow Band, 100 Hz
500 k
RS , SOURCE RESISTANCE (OHMS)
3.0 dB
30
50 70 100
200 300
IC, COLLECTOR CURRENT (µA)
500 700
1k
Figure 6. Narrow Band, 1.0 kHz
10 Hz to 15.7 kHz
200 k
100 k
50 k
ǒ
Noise Figure is defined as:
20 k
10 k
5k
NF
1.0 dB
2k
1k
500
3.0 dB
5.0 dB
8.0 dB
10
20
30
50 70 100
200 300
500 700
en2
Ǔ
) 4KTRS ) In 2RS2 1ń2
4KTRS
en = Noise Voltage of the Transistor referred to the input. (Figure 3)
In = Noise Current of the Transistor referred to the input. (Figure 4)
K = Boltzman’s Constant (1.38 x 10–23 j/°K)
T = Temperature of the Source Resistance (°K)
RS = Source Resistance (Ohms)
2.0 dB
200
100
50
+ 20 log10
1k
IC, COLLECTOR CURRENT (µA)
Figure 7. Wideband
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
BCW72LT1
TYPICAL STATIC CHARACTERISTICS
h FE, DC CURRENT GAIN
400
TJ = 125°C
25°C
200
– 55°C
100
80
60
VCE = 1.0 V
VCE = 10 V
40
0.004 0.006 0.01
0.02 0.03
0.05 0.07 0.1
0.2 0.3
0.5 0.7 1.0
2.0
IC, COLLECTOR CURRENT (mA)
3.0
5.0 7.0 10
20
30
50
70 100
100
1.0
TJ = 25°C
IC, COLLECTOR CURRENT (mA)
VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 8. DC Current Gain
0.8
IC = 1.0 mA
0.6
10 mA
50 mA
100 mA
0.4
0.2
0
0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0
IB, BASE CURRENT (mA)
TA = 25°C
PULSE WIDTH = 300 µs
80 DUTY CYCLE ≤ 2.0%
300 µA
200 µA
40
100 µA
20
0
5.0 10
0
20
5.0
10
15
20
25
30
35
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
θV, TEMPERATURE COEFFICIENTS (mV/°C)
TJ = 25°C
V, VOLTAGE (VOLTS)
1.2
1.0
VBE(sat) @ IC/IB = 10
0.6
VBE(on) @ VCE = 1.0 V
0.4
0.2
VCE(sat) @ IC/IB = 10
0
0.2
2.0
5.0
10
20
0.5 1.0
IC, COLLECTOR CURRENT (mA)
Figure 11. “On” Voltages
4
40
Figure 10. Collector Characteristics
1.4
0.1
400 µA
60
Figure 9. Collector Saturation Region
0.8
IB = 500 µA
50
100
1.6
*APPLIES for IC/IB ≤ hFE/2
0.8
25°C to 125°C
0
*qVC for VCE(sat)
– 55°C to 25°C
– 0.8
25°C to 125°C
– 1.6
qVB for VBE
– 2.4
0.1
0.2
– 55°C to 25°C
0.5
1.0 2.0
5.0 10 20
IC, COLLECTOR CURRENT (mA)
50
Figure 12. Temperature Coefficients
Motorola Small–Signal Transistors, FETs and Diodes Device Data
100
BCW72LT1
TYPICAL DYNAMIC CHARACTERISTICS
1000
VCC = 3.0 V
IC/IB = 10
TJ = 25°C
100
70
50
700
500
ts
300
200
t, TIME (ns)
t, TIME (ns)
300
200
tr
30
20
td @ VBE(off) = 0.5 Vdc
10
7.0
5.0
100
70
50
tf
30
VCC = 3.0 V
IC/IB = 10
IB1 = IB2
TJ = 25°C
20
3.0
1.0
2.0
20 30
5.0 7.0 10
3.0
IC, COLLECTOR CURRENT (mA)
50 70
10
1.0
100
2.0
3.0
500
70 100
10
TJ = 25°C
f = 100 MHz
TJ = 25°C
f = 1.0 MHz
7.0
300
VCE = 20 V
200
5.0 V
100
Cib
5.0
Cob
3.0
2.0
70
50
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
1.0
0.05
50
0.1
0.2
0.5
1.0
2.0
5.0
IC, COLLECTOR CURRENT (mA)
VR, REVERSE VOLTAGE (VOLTS)
Figure 15. Current–Gain — Bandwidth Product
Figure 16. Capacitance
hfe ≈ 200 @ IC = 1.0 mA
7.0
5.0
VCE = 10 Vdc
f = 1.0 kHz
TA = 25°C
3.0
2.0
1.0
0.7
0.5
0.3
hoe, OUTPUT ADMITTANCE (m mhos)
10
0.2
0.1
10
20
50
200
20
hie , INPUT IMPEDANCE (k Ω )
50
Figure 14. Turn–Off Time
C, CAPACITANCE (pF)
f T, CURRENT–GAIN BANDWIDTH PRODUCT (MHz)
Figure 13. Turn–On Time
20 30
5.0 7.0 10
IC, COLLECTOR CURRENT (mA)
100
70
50
VCE = 10 Vdc
f = 1.0 kHz
TA = 25°C
hfe ≈ 200 @ IC = 1.0 mA
30
20
10
7.0
5.0
3.0
0.2
0.5
20
1.0 2.0
5.0
10
IC, COLLECTOR CURRENT (mA)
50
100
Figure 17. Input Impedance
Motorola Small–Signal Transistors, FETs and Diodes Device Data
2.0
0.1
0.2
0.5
20
1.0 2.0
5.0
10
IC, COLLECTOR CURRENT (mA)
50
100
Figure 18. Output Admittance
5
r(t) TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
BCW72LT1
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
FIGURE 19A
0.05
P(pk)
0.02
0.03
0.02
t1
0.01
0.01
0.01 0.02
SINGLE PULSE
0.05
0.1
0.2
0.5
t2
1.0
2.0
5.0
10
20
50
t, TIME (ms)
100 200
DUTY CYCLE, D = t1/t2
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1 (SEE AN–569)
ZθJA(t) = r(t) • RθJA
TJ(pk) – TA = P(pk) ZθJA(t)
500 1.0 k 2.0 k
5.0 k 10 k 20 k
50 k 100 k
Figure 19. Thermal Response
104
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
IC, COLLECTOR CURRENT (nA)
VCC = 30 Vdc
A train of periodical power pulses can be represented by the model
as shown in Figure 19A. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 19 was calculated for various duty cycles.
To find Z θJA(t), multiply the value obtained from Figure 19 by the
steady state value RθJA.
103
102
ICEO
101
Example:
The MPS3904 is dissipating 2.0 watts peak under the following
conditions:
t1 = 1.0 ms, t2 = 5.0 ms. (D = 0.2)
Using Figure 19 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
ICBO
AND
ICEX @ VBE(off) = 3.0 Vdc
100
10–1
10–2
–4
0
–2
0
0
+ 20 + 40 + 60 + 80 + 100 + 120 + 140 + 160
TJ, JUNCTION TEMPERATURE (°C)
The peak rise in junction temperature is therefore
∆T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see AN–569.
Figure 19A.
IC, COLLECTOR CURRENT (mA)
400
1.0 ms
200
100
60
40
TC = 25°C
dc
dc
TJ = 150°C
10
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
6.0
2.0
The safe operating area curves indicate IC–VCE limits of the
transistor that must be observed for reliable operation. Collector load
lines for specific circuits must fall below the limits indicated by the
applicable curve.
The data of Figure 20 is based upon T J(pk) = 150°C; TC or TA is
variable depending upon conditions. Pulse curves are valid for duty
cycles to 10% provided TJ(pk) ≤ 150°C. TJ(pk) may be calculated from
the data in Figure 19. At high case or ambient temperatures, thermal
limitations will reduce the power that can be handled to values less
than the limitations imposed by second breakdown.
10 µs
1.0 s
TA = 25°C
20
4.0
100 µs
4.0
6.0 8.0 10
20
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
40
Figure 20.
6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
BCW72LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T J(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA . Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
7
BCW72LT1
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
B S
1
V
2
G
C
H
D
K
J
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
DIM
A
B
C
D
G
H
J
K
L
S
V
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013
0.100
0.085
0.177
0.45
0.60
0.89
1.02
2.10
2.50
0.45
0.60
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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8
◊
Motorola Small–Signal Transistors, FETs and Diodes Device
Data
BCW72LT1/D