IDT IDT7130LA35JGI High speed 1k x 8 dual-port static sram Datasheet

IDT7130SA/LA
IDT7140SA/LA
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
◆
◆
◆
◆
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140
◆
◆
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSYL
(1,2)
A9L
A0L
(1,2)
BUSYR
Address
Decoder
MEMORY
ARRAY
10
CEL
OEL
R/WL
Address
Decoder
A9R
A0R
10
ARBITRATION
and
INTERRUPT
LOGIC
CER
OER
R/WR
(2)
(2)
INTR
INTL
2689 drw 01
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
APRIL 2006
1
©2006 Integrated Device Technology, Inc.
DSC-2689/13
,
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance tech-nology,
these devices typically operate on only 550mW of power. Lowpower (LA) versions offer battery backup data retention capability,
with each Dual-Port typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
and STQFP. Military grade products are manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on chip circuitry
Pin Configurations(1,2,3)
01/08/02
CEL
R/WL
BUSYL
INTL
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8 IDT7130/40 41
P or C
9
(4) 40
10 P48-1
39
&
11 C48-2(4) 38
12 48-Pin 37
DIP
13
36
14 Top View(5) 35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VCC
CER
R/WR
BUSYR
INTR
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
01/
IN
,
2689 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
A0L
OEL
N/C
INTL
BUSYL
R/WL
CEL
VCC
Pin Configurations(1,2,3) (con't.)
01/08/02
INDEX
7 6 5 4 3 2
8
9
10
11
12
13
14
15
16
17
18
19
20
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
1
CER
R/WR
BUSYR
INTR
N/C
Military, Industrial and Commercial Temperature Ranges
52 51 50 49 48 47
IDT7130/40J
J52-1(4)
52-Pin PLCC
Top View(5)
46
45
44
43
42
41
40
39
38
37
36
35
34
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
,
N/C
N/C
N/C
INT L
BUSYL
R/W L
CE L
V CC
V CC
CE R
R/WR
BUSYR
INTR
N/C
N/C
N/C
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
2689 drw 04
01/08/02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT7130/40TF or PF
PP64-1 & PN64-1(4)
64-Pin STQFP
64-Pin TQFP
Top View(5)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
INDEX
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
N/C
A7R
A8R
A9R
N/C
N/C
I/O7R
I/O6R
,
I/O3L
N/C
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
GND
I/O0R
I/O1R
I/O2R
I/O3R
N/C
I/O4R
I/O5R
2689 drw 05
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Symbol
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
TSTG
Storage
Temperature
-65 to +150
-65 to +150
o
C
Parameter
VCC
Supply Voltage
GND
Ground
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
VIH
Input High Voltage
2.2
____
VIL
Input Low Voltage
-0.5(1)
____
(2)
6.0
V
0.8
V
2689 tbl 02
DC Output
Current
IOUT
Recommended DC Operating
Conditions
50
50
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
mA
2689 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Military
Ambient
Temperature
GND
Vcc
-55OC to +125OC
0V
5.0V + 10%
0V
5.0V + 10%
0V
5.0V + 10%
O
0 C to +70 C
Commercial
Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
O
Conditions
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
O
-40 C to +85 C
Industrial
STQFP and TQFP Packages Only
O
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2689 tbl 03
2689 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7130SA
7140SA
Symbol
|ILI|
Parameter
(1)
Input Leakage Current
(1)
Test Conditions
Min.
7130LA
7140LA
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
10
___
5
µA
0.4
___
0.4
V
0.5
V
___
V
|ILO|
Output Leakage Current
VCC - 5.5V,
CE = VIH, VOUT = 0V to VCC
___
VOL
Output Low Voltage (I/O0-I/O7)
IOL = 4mA
___
0.5
___
___
2.4
VOL
Open Drain Output
Low Voltage (BUSY, INT)
IOL = 16mA
___
VOH
Output High Voltage
IOH = -4mA
2.4
2689 tbl 04
NOTE:
1. At Vcc < 2.0V leakages are undefined.
4
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%)
7130X20(2)
7140X20(2)
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CEL and CER = VIL,
Outputs Disabled
f = fMAX(3)
CEL and CER = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(6)
Active Port OutputsDisabled,
f=fMAX(3)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
mA
COM'L
SA
LA
110
110
250
200
110
110
220
170
110
110
165
120
MIL &
IND
SA
LA
____
____
____
____
110
110
280
220
110
110
230
170
COM'L
SA
LA
30
30
65
45
30
30
65
45
25
25
65
45
MIL &
IND
SA
LA
____
____
____
____
30
30
80
60
25
25
80
60
COM'L
SA
LA
65
65
165
125
65
65
150
115
50
50
125
90
MIL &
IND
SA
LA
____
____
____
____
65
65
160
125
50
50
150
115
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
30
10
MIL &
IND
SA
LA
____
____
30
10
____
____
1.0
0.2
____
____
____
____
COM'L
SA
LA
60
60
155
115
60
60
145
105
45
45
110
85
MIL &
IND
SA
LA
____
____
____
____
60
60
155
115
45
45
145
105
mA
mA
mA
mA
2689 tbl 06a
7130X55
7140X55
Com'l, Ind
& Military
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CEL and CER = VIL,
Outputs Disabled
f = fMAX(3)
CEL and CER = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled,
f=fMAX(3)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
7130X100
7140X100
Com'l, Ind
& Military
Typ.
Max.
Typ.
Max.
Unit
COM'L
SA
LA
110
110
155
110
110
110
155
110
mA
MIL &
IND
SA
LA
110
110
190
140
110
110
190
140
COM'L
SA
LA
20
20
65
35
20
20
55
35
MIL &
IND
SA
LA
20
20
65
45
20
20
65
45
COM'L
SA
LA
40
40
110
75
40
40
110
75
MIL &
IND
SA
LA
40
40
125
90
40
40
125
90
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
SA
LA
40
40
100
70
40
40
95
70
MIL &
IND
SA
LA
40
40
110
85
40
40
110
80
mA
mA
mA
mA
2689 tbl 06b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC , TQFP and STQFP packages only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
5
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics
(LA Version Only)
7130LA/7140LA
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2.0V, CE > VCC -0.2V
tCDR
tR(3)
(3)
Min.
Typ. (1)
Max.
Unit
2.0
___
___
V
MIL. & IND.
___
100
4000
µA
COM'L.
___
100
1500
0
___
___
ns
tRC(2)
___
___
ns
Test Condition
Chip Deselect to Data Retention Time
VIN > VCC -0.2V or VIN < 0.2V
Operation Recovery Time
2689 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR ≥ 2.0V
tCDR
4.5V
tR
VDR
CE
VIH
VIH
2692 drw 06 ,
6
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1,2 and 3
2689 tbl 08
5V
5V
1250Ω
1250Ω
DATAOUT
DATAOUT
775Ω
30pF*
775Ω
5pF*
*100pF for 55 and 100ns versions
Figure 2. Output Test Load
(for t HZ, tLZ , tWZ, and tOW )
* including scope and jig
Figure 1. Output Test Load
5V
270Ω
BUSY or INT
30pF*
*100pF for 55 and 100ns versions
2689 drw 07
Figure 3. BUSY and INT
AC Output Test Load
7
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(3)
7130X20(2)
7140X20(2)
Com'l Only
Symbol
Parameter
7130X35
7140X35
Com'l
& Military
7130X25
7140X25
Com'l, Ind
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
Chip Enable Access Time
____
20
____
25
____
35
ns
Output Enable Access Time
____
11
____
12
____
20
ns
3
____
3
____
3
____
ns
0
____
0
____
0
____
ns
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
20
____
25
____
35
ns
tACE
tAOE
Output Hold from Address Change
tOH
(1,4)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time (1,4)
tPU
Chip Enable to Power Up Time (4)
(4)
Chip Disable to Power Down Time
tPD
____
2689 tbl 09a
7130X55
7140X55
Com'l, Ind
& Military
Symbol
Parameter
7130X100
7140X100
Com'l, Ind
& Military
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
55
____
100
____
ns
Address Access Time
____
55
____
100
ns
tACE
Chip Enable Access Time
____
55
____
100
ns
tAOE
Output Enable Access Time
____
25
____
40
ns
tOH
Output Hold from Address Change
3
____
10
____
ns
tLZ
Output Low-Z Time (1,4)
5
____
5
____
ns
tHZ
(1,4)
____
25
____
40
ns
0
____
0
____
ns
50
____
50
ns
READ CYCLE
tRC
tAA
tPU
tPD
Output High-Z Time
Chip Enable to Power Up Time
(4)
Chip Disable to Power Down Time
(4)
____
2689 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. PLCC, TQFP and STQFP packages only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
.
8
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2689 drw 08
tBDDH (2,3)
NOTES:
1. R/W = VIH, CE = V IL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
tACE
CE
tAOE (4)
tHZ (2)
OE
tHZ (2)
tLZ (1)
DATAOUT
VALID DATA
tLZ
ICC
CURRENT
ISS
(1)
tPD(4)
tPU
50%
50%
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = V IH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE , tACE, tAA, and tBDD.
9
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5)
7130X20(2)
7140X20(2)
Com'l Only
Symbol
Parameter
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
25
____
35
____
ns
20
____
30
____
ns
WRITE CYCLE
Write Cycle Time (3)
tWC
tEW
Chip Enable to End-of-Write
15
____
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width(4)
15
____
15
____
25
____
ns
0
____
0
____
0
____
ns
10
____
12
____
15
____
ns
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
10
____
10
____
15
ns
____
0
____
0
____
ns
tWR
Write Recovery Time
Data Valid to End-of-Write
tDW
tHZ
Output High-Z Time
tDH
(1)
Data Hold Time
(1)
tWZ
Write Enable to Output in High-Z
____
tOW
Output Active from End-of-Write (1)
0
2689 tbl 10a
7130X55
7140X55
Com'l, Ind
& Military
Symbol
Parameter
7130X100
7140X100
Com'l, Ind
& Military
Min.
Max.
Min.
Max.
Unit
55
____
100
____
ns
40
____
90
____
ns
40
____
90
____
ns
0
____
0
____
ns
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time (3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
(4)
tWP
Write Pulse Width
30
____
55
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
40
____
ns
tHZ
Output High-Z Time (1)
____
25
____
40
ns
0
____
0
____
ns
____
25
____
40
ns
0
____
0
____
ns
tDH
tWZ
tOW
Data Hold Time
(1)
Write Enable to Output in High-Z
Output Active from End-of-Write
(1)
2689 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
is not production tested.
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after t BAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data
to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
10
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
tHZ(7)
OE
tAW
CE
tWP(2)
tAS(6)
tWR(3)
tHZ(7)
R/W
tWZ(7)
tOW
(4)
DATA OUT
(4)
tDW
tDH
DATA IN
2689 drw 10
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
tAS(6)
tEW(2)
tWR(3)
R/W
tDW
tDH
DATA IN
2689 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7)
7130X20(1)
7140X20(1)
Com'l Only
Symbol
Parameter
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
20
____
20
ns
20
____
20
ns
20
____
20
ns
BUSY TIMING (For MASTER IDT 7130)
tBAA
BUSY Access Time from Address
____
tBDA
BUSY Disable Time from Address
____
20
____
tBAC
BUSY Access Time from Chip Enable
____
20
____
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20
ns
tWH
Write Hold After BUSY(6)
12
____
15
____
20
____
ns
tWDD
Write Pulse to Data Delay(2)
____
40
____
50
____
60
ns
____
30
____
35
____
35
ns
5
____
5
____
5
____
ns
____
25
____
35
____
35
ns
tDDD
Write Data Valid to Read Data Delay
tAPS
Arbitration Priority Set-up Time (3)
tBDD
BUSY Disable to Valid Data(4)
(2)
BUSY INPUT TIMING (For SLAVE IDT 7140)
tWB
Write to BUSY Input(5)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(6)
12
____
15
____
20
____
ns
____
40
____
50
____
60
ns
____
30
____
35
____
35
ns
(2)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (2)
2689 tbl 11a
7130X55
7140X55
Com'l, Ind
& Military
Symbol
Parameter
7130X100
7140X100
Com'l, Ind
& Military
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 7130)
tBAA
BUSY Access Time from Address]
____
30
____
50
ns
tBDA
BUSY Disable Time from Address
____
30
____
50
ns
tBAC
BUSY Access Time from Chip Enable
____
30
____
50
ns
tBDC
BUSY Disable Time from Chip Enable
____
30
____
50
ns
tWH
Write Hold After BUSY(6)
20
____
20
____
ns
tWDD
Write Pulse to Data Delay(2)
____
80
____
120
ns
____
55
____
100
ns
5
____
5
____
ns
____
55
____
65
ns
tDDD
Write Data Valid to Read Data Delay
tAPS
Arbitration Priority Set-up Time (3)
tBDD
BUSY Disable to Valid Data(4)
(2)
BUSY INPUT TIMING (For SLAVE IDT 7140)
tWB
Write to BUSY Input(5)
0
____
0
____
ns
tWH
Write Hold After BUSY(6)
20
____
20
____
ns
80
____
120
ns
55
____
100
tWDD
tDDD
Write Pulse to Data Delay
(2)
Write Data Valid to Read Data Delay
____
(2)
____
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
12
ns
2689 tbl 11b
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDH
tDW
DATAIN"A"
VALID
tAPS
(1)
ADDR"B"
MATCH
tBDD
tBDA
tBAA
BUSY"B"
tWDD
DATAOUT"B"
VALID
tDDD
2689 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2. CEL = CER = VIL
3. OE = V IL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
tWB
BUSY"B"
tWH(1)
R/W"B"
,
(2)
2689 drw 13
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
13
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
'A'
ADDRESSES MATCH
AND 'B'
CE'B'
tAPS(2)
CE'A'
tBDC
tBAC
BUSY'A'
2689 drw 14
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing(1)
tRC OR tWC
ADDR'A'
ADDRESSES MATCH
tAPS
ADDRESSES DO NOT MATCH
(2)
ADDR'B'
tBAA
tBDA
BUSY'B'
2689 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2)
7130X20(1)
7140X20(1)
Com'l Only
Symbol
Parameter
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tINS
Interrupt Set Time
____
20
____
25
____
25
ns
tINR
Interrupt Reset Time
____
20
____
25
____
25
ns
2689 tbl 12a
NOTES:
1. PLCC, TQFP and STQFP package only.
2. 'X' in part numbers indicates power rating (SA or LA).
14
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical characteristics Over the
Operating Temperature and Supply Voltage Range(1)
7130X55
7140X55
Com'l, Ind
& Military
Symbol
Parameter
7130X100
7140X100
Com'l, Ind
& Military
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
45
____
60
ns
45
____
60
ns
tINS
tINR
Interrupt Set Time
____
Interrupt Reset Time
____
2689 tbl 12b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
Timing Waveform of Interrupt Mode(1)
INT Set:
tWC
ADDR'A'
(2)
INTERRUPT ADDRESS
tWR (4)
tAS(3)
R/W'A'
tINS (3)
INT'B'
2689 drw 16
INT Clear:
tRC
ADDR'B'
INTERRUPT CLEAR ADDRESS
tAS
(3)
OE'B'
tINR
(3)
INT'A'
2689 drw 17
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
15
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Truth Tables
Truth Table I — Non-Contention Read/Write Control(4)
Inputs(1)
R/W
CE
OE
D0-7
X
H
X
Z
Port Disabled and in Power-Down Mode, I SB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
H
L
H
Z
Function
Data on Port Written into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
2689 tbl 13
NOTES:
1. A0L – A10L • A0R – A 10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II — Interrupt Flag(1,4)
Left Port
Right Port
R/WL
CEL
OEL
A9L-A0L
INTL
R/WR
CER
OER
A9R-A0R
L
L
X
3FF
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L(3)
L
(2)
X
X
L
L
3FE
H
Function
X
L(2)
Set Right INTR Flag
L
3FF
H(3)
Reset Right INTR Flag
L
X
3FE
X
Set Left INTL Flag
X
X
X
X
Reset Left INTL Flag
2689 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSY L = VIL, then No Change.
3. If BUSY R = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Truth Table III — Address BUSY
Arbitration
Inputs
INTR
Outputs
CEL
CER
A0L-A9L
A0R-A9R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2689 tbl 15
NOTES:
1. Pins BUSY L and BUSYR are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the BUSY X input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSY L or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
16
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Functional Description
RAMs are being expanded in depth, then the BUSY indication for the
resulting array does not require the use of an external AND gate.
The IDT7130/IDT7140 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7130/IDT7140 has an
automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
Width Expansion with Busy Logic
Master/Slave Arrays
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth
Table II. The left port clears the interrupt by access address location
3FE access when CEL = OEL = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location 3FF. The message (8 bits)
at 3FE or 3FF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations 3FE and
3FF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table II for the interrupt operation.
5V
270Ω
MASTER
Dual Port
RAM
BUSYL
MASTER
Dual Port
RAM
BUSYL
Busy Logic
BUSYL
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
DECODER
When expanding an RAM array in width while using busy logic, one
master part is used to decide which side of the RAM array will receive
a busy indication, and to output that indication. Any number of slaves
to be addressed in the same address range as the master, use the
busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140
RAMs the BUSY pin is an output if the part is Master (IDT7130), and
the BUSY pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
5V
270Ω
CE
BUSYR
BUSYR
2689 drw 18
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. In slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT7130 RAM (Master) are open drain
type outputs and require open drain resistors to operate. If these
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
If two or more master parts were used when expanding in width,
a split decision could result with one master indicating busy on one side
of the array and another master indicating busy on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
17
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
999
A
Device Type Power Speed Package
A
A
Process/
Temperature
Range
BLANK
I(1)
B
G
(2)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
Green
P (3)
C
J
L48
F
PF
TF
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
20
25
35
55
100
Commercial PLCC, TQFP and STQFP Only
Commercial, Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
LA
SA
Low Power
Standard Power
7130
7140
8K (1K x 8-Bit) MASTER Dual-Port RAM
8K (1K x 8-Bit) SLAVE Dual-Port RAM
,
Speed in
nanoseconds
2689 drw 19
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, pacakges and powers contact your local sales office.
3. For "P", plastic DIP, when ordering green package the suffix is "PDG".
Datasheet Document History
03/15/99:
Pages 2 and 3
06/08/99:
08/02/99:
09/29/99:
11/10/99:
06/23/00:
01/08/02:
Page 2
Page 2
Page 1 & 18
Page 4
Page 5
Page 10
Page 1
Page 2 & 3
Page 4, 5, 8, 10,
12,14 & 15
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
Corrected package number in note 3
Fixed pin 1 in DIP pin configuration
Replaced IDT logo
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±500mV to 0mV in notes
Added Ceramic Flatpack to 48-pin package offerings
Added date revision to pin configurations
Removed industrial temp option footnote from all tables
Continued on page 19
18
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
01/08/02:
01/11/06:
04/14/06:
Page 5, 8, 10, 12, & 14
Page 5, 8, 10, 12, & 14
Page 18
Page 1 & 19
Page 1
Page 18
Page 1 & 19
Page 18
Added industrial temp for 25ns to DC & AC Electrical Characteristics
Removed industrial temp for 35ns to DC & AC Electrical Characteristics
Added industrial temp for 25ns and removed industrial temp for 35ns in ordering information
Updated industrial temp option footnote
Replaced IDT TM logo with IDT ® logo
Added green availability to features
Added green indicator to ordering information
Replaced old IDT TM with new IDT TM logo
Added "PDG" footnote to the ordering information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
19
for Tech Support:
408-284-2794
[email protected]
Similar pages