TI TC285SPD-B0

TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
•
•
•
•
•
•
•
•
•
•
•
Very Low Noise, Very High
Sensitivity, Electronically
Variable Charge Domain Gain
High Resolution, 2/3-in
Format, Solid State ChargeCoupled Device (CCD) Frame
Transfer Image Sensor for low
light level applications with 30Frame/s readout speed.
1,006,008 Pixels per Field
Frame Memory
1004 (H) x 1002 (V) Active
Pixels in Image Sensing Area
Compatible With Electronic
Centering
Multimode Readout Capability
o Progressive Scan
o Line Summing
o Pixel Summing
Serial Register 0-8V Clocking
(except CMG gate)
Continuous Electronic
Exposure Control from 1/30 s
to 1/5,000 s
8.0 um Square Pixels
Advanced Lateral Overflow
Drain
Low Dark Current
DUAL-IN-LINE PACKAGE
(TOP VIEW)
P+
1
28
P-
P+
2
27
P-
SUB
3
26 NC
ODB
4
25 NC
IAG2 5
24 IAG2
IAG1 6
23 IAG1
SAG2 7
22 SAG2
SAG1 8
21 SAG1
SUB
20 FP
9
SRG1 10
19 VCLD
SRG2 11
18 VOUT
CMG 12
17 VDD
RST 13
16 VREFG
SUB 14
15 SUB
•
High Photo response
Uniformity Over a Wide
Spectral Range
•
Solid State Reliability With No
Image Burn-in, Residual
Imaging, Image Distortion,
Image Lag, or Microphonics
•
Package with peltier cooler
Description
The TC285SPD is a 1004x1002 30-Frame/s readout, frame-transfer CCD image sensor
designed for use in black and white, bio-medical, and special-purpose applications
requiring high sensitivity, high speed, high resolution, and low noise.
The TC285SPD is a new device of the IMPACTRONTM family of very-low noise, high
sensitivity, high-speed, and high-resolution image sensors that multiply charge directly in
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the charge domain before conversion to voltage. The charge carrier multiplication (CCM)
is achieved by using a low-noise single-carrier, impact ionization process that occurs
during repeated carrier transfers through high field regions. Applying multiplication
pulses to specially designed gates activates the CCM. The amount of multiplication gain
is adjustable depending on the amplitude of multiplication pulses. The device function
resembles the function of an image intensifier implemented in solid state.
The image-sensing area of the TC285SPD is configured into 1002 lines with 1004 pixels
in each line. 28 pixels are reserved in each line for dark reference. The blooming
protection is based on an advanced lateral overflow drain concept that does not reduce
NIR response. The sensor can be operated in the progressive scan mode and can capture a
full 1,006,008 pixels in one image field. The frame transfer from the image sensing area
to the memory area is accomplished at a high rate that minimizes image smear. The
electronic exposure control is achieved by clearing the unwanted charge from the image
area using a short positive pulse applied to the anti-blooming drain. This marks the
beginning of the integration time, which can be arbitrarily shortened from its nominal
length. After charge is integrated and stored in the memory it is available for readout in
the next cycle. This is accomplished by using a unique serial register design that includes
special charge multiplication pixels.
The TC285SPD sensor is built using TI-proprietary advanced Split-Gate Virtual-Phase
CCD (SGVPCCD) technology, which provides devices with wide spectral response, high
quantum efficiency (QE), low dark current, and high response uniformity.
This MOS device contains limited built-in ESD protection. During storage or handling, the device
leads should be shorted together or the device should be placed in conductive foam. In a circuit,
unused inputs should always be connected to Vss. Under no circumstances should pin voltages
exceed absolute maximum ratings. Avoid shorting OUT to Vss during operation to prevent
damage to the amplifier. The device can also be damaged if the output and ADB terminals are
reverse-biased and excessive current is allowed to flow. Specific guidelines for handling devices
of this type are contained in the publication “Guidelines for Handling Electrostatic-DischargeSensitive (ESD) Devices and Assemblies” available from Texas Instruments.
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F u n c tio n a l b lo c k d ia gra m
SUB
3
ODB
4
D ark R e fe re n c e P ixe ls
IA G 2 5
24
IA G 2
23
IA G 1
Im age S e n sin g A re a
w ith B lo o m in g P ro te c tio n
IA G 1 6
SAG 2 7
SAG 1 8
SUB
9
22 S A G 2
Im age S to rage A re a
21
SAG
1
20
FP
S R G 1 10
S R G 2 11
S e rial R e ad o u t R e giste r
19 V C L D
C le arin g D rain
C h arge M u ltip lie r
C M G 12
18
V out
17
VDD
16 V R E F G
R S T 13
15
SUB
S U B 14
** TC285SPD includes an output bipolar transistor in the package. For a proper operation it is
necessary to connect a 2.2kOhm-loading resistor externally to the VOUT pin.
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TC285SPD-B0
CCD IMAGE SENSOR
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Inside package
VDD
V out
V out
2.2K Ω
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S ensor T opology diagram
27 D ark R eference
P ixels+1H alf P ixel
1H alf P ixel+3 D ark
R eference P ixels
1004 A ctive P ixels
1002 A ctive Lines
D ark R eference P ixels
1010 Lines
6 D ark
pixels
+ 2 Invalid
P ixels
Im age S ensing A rea
w ith B loom ing P rotection
Im age S torage A rea
10 27 1
1 3
1004 A ctive P ixels
H alf P ixels
643 D um m y P ixels
400 M ultiplication
3
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TC285SPD-B0
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Terminal functions
Terminal name
VDD
VCLD
IAG1
IAG2
ODB
OUT
SAG1
SAG2
SRG1
SRG2
CMG
RST
FP
VREFG
SUB
P+
P-
No.
17
19
6,23
5,24
4
18
8,21
7,22
10
11
12
13
20
16
3,9,14,15
1,2
27,28
I/O
I
I
I
I
I
O
I
I
I
I
I
I
I
I
-
Description
Supply voltage for amplifiers
Supply voltage for Clearing drain & ESD circuits
Image area gate-1
Image area gate-2
Supply voltage for anti-blooming drain
Output signal, multiplier channel
Storage area gate-1
Storage area gate-2
Serial register gate-1
Serial register gate-2
Charge multiplication gate
Reset gate
Field plate (See Figure 3)
Amplifier reference gate
Chip substrate
Peltier cooler power supply -positive
Peltier cooler power supply -negative
Detailed description
The TC285SPD consists of five basic functional blocks: The image-sensing area, the
image–storage area, the serial register, the charge multiplier, and the charge detection
node with buffer amplifier. The location of each of these blocks is identified in the
functional block diagram.
Image-sensing and storage areas
Figure 1 and Figure 2 show the pixel cross-section with potential-well diagram and top
views of pixels in the image-sensing and storage areas. As light enters the silicon in the
image-sensing area, electrons are generated and collected in potential wells of the pixels.
Applying a suitable dc bias to the anti blooming drain provides blooming protection. The
electrons that exceed a specific level, determined by the ODB bias, are drained away
from the pixels. If it is necessary to remove all previously accumulated charge from the
wells a short positive pulse is applied to the drain. This marks the beginning of the new
integration period. After the integration cycle is completed, charge is quickly transferred
into the memory where it waits for readout. The lines can be read out from the memory in
a sequential order to implement progressive scan. 28 columns at the left edge and 4
columns at the right edge of the image-sensing area are shielded from the incident light.
These pixels provide the dark reference used in subsequent video-processing circuits to
restore the video-black level. Additionally, 6 dark lines, located between the image
sensing area and the image-storage area, were added to the array for isolation.
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Advanced lateral overflow drain
The advanced lateral overflow drain structure is shared by two neighboring pixels in each
line. By varying the DC bias of the anti-blooming drain it is possible to control the
blooming protection level and trade it for well capacity. Applying a pulse to the drain,
approximately 6V above the nominal level, for a minimum of 100µs(3H), removes all
charge from the pixels. This feature permits precise control of the integration time on a
frame-by-frame basis. The single-pulse clearing capability also reduces smear by
eliminating accumulated charge in pixels before the start of the integration period (single
sided smear).
Serial register and charge multiplier
The serial register of TC285SPD image sensor consists of only poly-silicon gates. It
operates at high speed, being clocked from 0V to 8V. This allows the sensor to work at
30 frames/s. The serial register is used for transporting charge stored in the pixels of the
memory lines to the output amplifier. The TC285SPD device has a serial register with
twice the standard length. The first half has a conventional design that interfaces with the
memory as it would in any other CCD sensor. The second half, however, is unique and
includes 400 charge multiplication stages with a number of dummy pixels that are needed
to transport charge between the active register blocks and the output amplifier. Charge is
multiplied as it progresses from stage to stage in the multiplier toward the charge
detection node. The charge multiplication level depends on the amplitude of the
multiplication pulses (approximately 15V~22V) applied to the multiplication gate. Due to
the double length of the register, first 2 lines in each field or frame scan do not contain
valid data and should be discarded.
Charge detection node and buffer amplifier
The last element of the charge detection and readout chain is the charge detection node
with the buffer amplifier. The charge detection node is using a standard Floating
Diffusion (FD) concept followed by an on-chip dual-stage source-follower buffer.
Another bipolar transistor (third stage) has been included in the sensor package to
improve the driving capability at high speed. A load for the bipolar transistor (2.2kOhm)
needs to be connected externally from the package output pin to SUB. Applying a pulse
to the RST pin resets the detection node. Pixel charge summing function can be easily
implemented by skipping the RST pulses. To achieve the ultimate sensor performance it
is necessary to eliminate kTC noise. This is typically accomplished by using CDS
(correlated double sampling) processing techniques. IMPACTRONTM devices have the
potential for detecting single electrons (photons) when cooled or when sufficiently short
integration times are used.
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CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
Absolute maximum ratings over operating free-air temperature range
(unless otherwise noted)*
Supply voltage range, Vss: VDD, VCLD (see Note1) ………… 0V to + 15V
Supply voltage range, Vss: ODB………………………………… 0V to + 22V
Supply voltage range, Vss: FP, VREFG ………………………… 0V to + 8V
Input voltage range, Vi: IAG, SAG………. …………………… - 8V to + 8V
Input voltage range, Vi: SRG, RST…………………………… 0V to + 10V
Input voltage range, Vi: CMG ………………………………… -5V to + 23V
Supply voltage range, Vcool: P+ (see Note2)………………….. 0V to + 7V
Supply current range, Icool: P+ (see Note2) ………………
0A to 1.8A
Operating free-air temperature range, Ta ……………………… -10°C to 45°C
Storage temperature range, Tstg ……………………………… -30°C to 85°C
Operating case temperature range …………………..…..….……-10°C to 55°C
Dew point of package inside gas (see Note2)……….…..….… Less than -20°C
*
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
Note 1: All voltage values are with respect to substrate terminal.
Note 2: Peltier cooler generates heat during cooling process. To keep the case temperature range, the heat
must be removed through an external heat sink. See Figure 12 for reference of CCD temperature vs Icool.
In order to avoid condensation upon the surface do not cool the CCD to less than -20 degrees C.
Be careful when attaching external heat sink to package. Fastening it too strongly may crack or puncture
the package, making it susceptible to moisture or humidity.
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CCD IMAGE SENSOR
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Recommended operating conditions
Description
Substrate bias, Vss
Supply voltage, Vdd*
ODB
VDD, VCLD
For blooming control
For clearing
FP
VREFG **
High
Low
High
IAG2***
Low
High
SAG1***
Low
High
SAG2***
Low
High
Input voltage, Vi *
SRG1
Low
High
SRG2
Low
High
CMG****
Low
High
RST
Low
IAG1, IAG2, SAG1, SAG2
Clock Frequency, fck
SRG1, SRG2, CMG ,RST
Load capacitance
OUT
Inside dew point of a package*****
Operating free-air temperature
IAG1***
MIN NOM
0
13.5 14.0
4.9
5.2
12.0 12.5
1.5
5.0
5.5
3.2
3.5
-6.0 -5.7
2.9
3.2
-6.0 -5.7
3.2
3.5
-6.0 -5.7
2.9
3.2
-6.0 -5.7
7.5
7.8
0.0
7.5
7.8
0.0
7.0
-4.1 -3.8
5.5
6.0
0.0
1.0
35.0
-10
25
MAX
14.5
5.5
13.0
6.0
3.8
-5.4
3.5
-5.4
3.8
-5.4
3.5
-5.4
8.1
UNIT
V
V
8.1
22.0
-3.5
6.5
MHz
6.0
-20
45
pF
°C
°C
* Fine-tuning of input voltages may be required to obtain the best charge transfer efficiency.
** For proper operation it is necessary to keep VREFG bias lower than RST High voltage
*** Refer to Figure 6 for a description of the waveforms applied to IAG and SAG by typical driver
circuits operated at the H and L voltage settings specified in these recommended operating conditions.
**** Charge multiplication gain depends on high level of the CMG and temperature. See figure 10.
***** -20 degrees should be the minimum temperature of the cooled CCD.
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Electrical characteristics over recommended operating ranges of supply
voltage at operating free-air temperature (unless otherwise noted)
PARAMETER
Charge multiplication gain**
Excess noise factor for typical CCM gain (Note 3)
Dynamic range without CCM gain
Dynamic range with typical CCM gain (Note 4)
Charge conversion gain without CCM gain (Note 5)
τ
Signal-response delay time (Note6)
Output resistance(Note 7)
Amp. Noise-equivalent signal without CCM gain *
Amp. Noise-equivalent signal with typ. CCM gain *
Response linearity with no CCM gain
Response linearity with typ. CCM gain
Charge-transfer efficiency
Parallel transfer
(Note 8)
Serial transfer
Supply current without output bipolar transistor current
IAG1
IAG2
IAG1-IAG2
SAG1
SAG2
SAG1-SAG2
SRG1
Ci Input capacitance
SRG2
CMG
ODB
RST
FP
VREFG
MIN
1
1
TYP MAX
200
2000**
1.4
66
72
14
16
320
20
1.0
1
1
0.99994
1.0
0.99994
1.0
2.7
4
12.8
13.5
6.8
13.9
14.5
7.78
86.0
69.0
24.0
3,000
10
127
10
UNIT
dB
dB
uV/e
ns
Ω
e
e
mA
nF
pF
All typical values are at Ta = 25 °C unless otherwise noted.
** Maximum CCM gain is not guaranteed.
* The values in the table are quoted using CDS = Correlated Double Sampling. CDS is a signal
processing technique that improves performance by minimizing undesirable effects of reset noise.
Notes: 3. Excess Noise Factor “F” is defined as the ratio of noise sigma after multiplication divided by M
times the noise sigma before multiplication where M is the charge multiplication gain.
4. Dynamic Range is –20 times the logarithm of the noise sigma divided by the saturation–output
signal amplitude.
5. Charge conversion factor is defined as the ratio of output signal to input number of electrons.
6. Signal-response delay time is the time between the falling edge of the SRG1 pulse and the
output-signal valid state.
7. Since the output bipolar transistor is carried out to the package, output resistance cannot be
measured.
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8. Charge transfer efficiency is one minus the charge loss per transfer in the CCD register. The test is
performed in the dark using either electrical or optical input.
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Optical characteristics
Ta = 25°C, Integration time = 16.67ms(unless otherwise noted)
PARAMETER
MIN TYP MAX
UNIT
No IR filter
Sensitivity with typical CCM gain (Note 9)
5600
With IR filter
700
No IR filter
28
With IR filter
3.5
Saturation signal output no CCM gain (Note 10)
Saturation signal output Anti blooming Enable no CCM
gain(Note 10)
Saturation signal output with typ. CCM gain (Note10)
Zero input offset output (Note 11)
Blooming overload ratio (Note 12)
Image area well capacity
Smear (Note 13)
Dark current (Note 14)*
Dark signal (Note 15)*
Dark-signal uniformity (Note 16)
Dark-signal shading (Note 17)
Spurious
Dark
non-uniformity
Illuminated
Column uniformity (Note 18)
Electronic-shutter capability
600
180
Sensitivity without CCM gain (Note 9)
Notes:
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
1100
90
1000:1
40k
-44
0.005 0.02
0.005 0.02
0.3
0.2
10.0
-30%
30%
1.5%
1/5000 1/30
V/Lx*s
V/Lx*s
mV
dB
nA/cm2
mV
mV
mV
mV
s
Light source temperature is 2856 °K. The IR filter used is CM500 1mm thick.
Saturation is the condition in which further increase in exposure does not lead to further
increases in output signal.
Zero input offset is the residual output signal measured from the reset level with no input
charge present. This level is not caused by the dark current and remains approximately
constant independent of temperature. It may vary with the amplitude of SRG1.
Blooming is the condition in which charge induced by light in one element spills over to the
neighboring elements.
Smear is the measure of error signal introduced into the pixels by transferring them through
the illuminated region into the memory. The illuminated region is 1/10 of the image area
height. The value in the table is obtained for the integration time of 16.66ms and 1.0 MHz
vertical clock transfer frequency.
Dark current depends on temperature and approximately doubles every 8 Co. Dark current
is also multiplied by CCM operation. The value given in the table is with the multiplier
turned off and it is a calculated value.
Dark signal is actual device output measured in dark.
Dark signal uniformity is the sigma of difference of two neighboring pixels taking from all
the image area pixels.
Dark signal shading is the difference between maximum and minimum of 5 pixel median
taken anywhere in the array.
Column uniformity is obtain by summing all the lines in the array, finding the maximum of
the difference of two neighboring columns anywhere in the array, and dividing the result by
number of lines.
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8.0 um
8.0 um
IAG2
Antiblooming
Drain
Image Area Pixel
IAG1
Channel Stops
7.6 um
SAG2
Storage Area Pixel
SAG1
8.0 um
FIGURE 2. Image Area and Memory Area Pixel Topologies
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SRG2 (CMG)
FP
Polysilicon Gates
SRG1
Pixel Cross Section
X
φ
Channel Potential
FIGURE 3. Serial Register Pixel Cross Section
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Image area clear
Transfer
to memory
Integrate
ODB
1003 Cycles
IAG1
IAG2
SAG1
Max 300us
SAG2
1018 Pulses
RST
SRG1
SRG2
CMG
1046 Pulses
line#-1(**)
line#1002
line#0(**)
IAG1
RST
IAG2
SRG1
SRG2
SAG1
CMG
SAG2
Expanded section of serial transfer
Expanded section of Parallel transfer
(**) Lines "-1" and "0" does not contain valid data
FIGURE 4. Progressive Scan Timing
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10 Dummy signal
1 Half shielded signal
1 Half shielded signal
3 Dark signal
27 Dark signal
1004 Active signal
5
19*
3
* Due to light leakage into the edge pixels of the 27 dark reference pixels it is recommended
that these 19 pixels be used for true dark reference.
FIGURE 5. Composition of output signal for a line
H
IAG1,SAG1
L
H
IAG2,SAG2
L
FIGURE 6. An example of parallel transfer waveform by typical driver circuit
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For optimum CCM operation, some overlap of CMG HIGH
and SRG1 HIGH is necessary. It is recommended to
design the timing such that phase can be easily adjusted by
at least 5ns.
CM G
SR G 1
SR G 2
RST
V out
Reference
Level
Output Signal(***)
SH
C lam p
(***) Output signal may not go all the way to zero. A zero offset of up to 100 mV may be present.
FIGURE 7. Detailed Serial Register Clock Timing for CDS Implementation.
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Vout [mV]
Vsat
14*M uV/e
Zero Offset
Ith
Built in Threshold Level
Input Light intensity [Lux]
FIGURE 8. Photon Transfer Characteristic of CCD Outputs
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0.50
0.45
QE=80%
QE=60%
Responsivity - A/W
0.40
0.35
QE=40%
0.30
0.25
QE=30%
0.20
0.15
0.10
0.05
0.00
400
600
800
Wavelength - nm
1000
FIGURE 9. Typical Spectral Response
FIGURE 10. Typical CM gain as function of CMG high voltage
1600
1400
25°C
15°C
0°C
-15°C
-25°C
Absolute Gain
1200
1000
800
600
400
200
0
18.5
19
19.5
20
20.5
CMG Hi[V]
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30
Ambience : 22°C foeced air flow
CCD drive : on
Temperature of CCD(℃)
20
10
0
-10
-20
-30
0
200
400
600
800
1000
1200
Peltier cooler current [mA]
FIGURE 12. Typical cooling capability
60.0
Please observe the absolute minimum
temperature of the CCD, -20 °C.
Temperature of CCD(℃)
40.0
Peltier off
20.0
Peltier current0.28A
0.0
-20.0
Dew point
-40.0
Peltier current1.5A
-60.0
-20
-10
0
10
20
30
40
50
Open air temperature(℃)
FIGURE 13. TC285-B0 Typical cooling characteristic
TEXAS
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TC285SPD-B0
CCD IMAGE SENSOR
TM
1004 x 1002 PIXEL IMPACTRON
SOCS093 – JANUARY 2006
A heat dissipation board was attached to the back of the CCD package for measurement
purposes.
Vcc
-Viag2 +Viag2 -Viag1 +Viag1
-Vsag2 +Vsag2 -Vsag1 +Vsag1
1
Vcc
Vcc
+
0.1
Oscillator
10k
IAG1
IAG2
SAG1
SAG2
33
2
SAG2
3
-Vsag1
4
SRG1
SRG2
RSG
CMG
CLK
VS+
VH
OE
OUT
IN
VL
GND
VS-
8
+Vsag2
7
SAG2_O
6
-Vsag2
5
0.1 EL7156CS
0.1
1
10k
2
SAG1
3
-Vsag2
4
VS+
VH
OE
OUT
IN
VL
GND
8
+Vsag1
7
SAG1_O
6
-Vsag1
5
VS-
0.1 EL7156CS
0.1
0.1
0.1
ODB1
ODB2
GND
CLMP
S/H
SYNC
LCLMP
CLEAR
1
10k
Us e r De fine d Tim e r
VS+
2
IAG2
3
-Viag2
4
VH
OE
OUT
IN
VL
GND
VS-
8
+Viag2
7
IAG2_O
6
-Viag2
5
0.1 EL7156CS
0.1
1
10k
2
IAG1
3
-Viag1
4
VS+
VH
OE
OUT
IN
VL
GND
8
+Viag1
7
IAG1_O
6
-Viag1
5
VS-
0.1 EL7156CS
0.1
FP
0.1
0.1
Vcld VDD VREFG
ODB_O
Curre nt Buffe r Circuit Block
IAG2_O
IAG1_O
SAG2_O
SAG1_O
0.01
IAG2
IAG2_OUT
IAG1
IAG1_OUT
SAG2 SAG2_OUT
SAG1 SAG1_OUT
SRG1_O
SRG2_O
CMG_O
RSG_O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SRG2
NC
NC
NC
NC
IAG2
IAG1
SAG2
SAG1
FP
VCLD
VOUT
VDD
VREFG
SUB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TC285SPD
+Vrsg
-Vrsg
RSG
NC
NC
SUB
ODB
IAG2
IAG1
SAG2
SAG1
SUB
SRG1
SRG2
CMG
RST
SUB
IAG2_O
IAG1_O
SAG2_O
SAG1_O
OUT
2.2k
0.1
0.1
0.1
0.1
+Vsrg2
-Vsrg2
GND
SRG2out
RSG_O
RSG Drive r
Vcmdh
Vcmdl
Vodb
ODB1
ODB2
ODB1
Vodb
CMG
CMG
ODB2
GND
SRG1
Vcmgh
+Vsrg1
-Vsrg1
SRG1
Vcmgl
ODBout
ODB Drive r
ODB_O
GND
CMGout
CM G Drive r
SRG2
+Vsrg1
+Vsrg2
-Vsrg2
SRG2
-Vsrg1
CMG_O
GND
SRG1out
+Vsrg2
-Vsrg2
SRG1_O
SRG1 Drive r
GND
SRG2out
SRG2_O
SRG2 Drive r
Notes: A. All values are in Ohms and Microfarads unless otherwise noted.
B. TI recommends AC coupled system for coupling to the next video processing circuits.
C. Damping resister on each driver lines are defined by the condition of user designed board (1.0 ~ 10 ohm
recommended).
D. Please shift the GND levels of IAG and SAG at the output of "User Defined Timer" from GND to their
appropriate -V as specified in the data sheet before inputting those signals into the EL7156CS driver ICs.
TEXAS
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
FIGURE 15. Typical Application Circuit Diagram
Vcmgh
+
100
0.1
2200p
1SS226
10k
1SS193
Vcc (~ 5.5V)
CMG
TP2104N3
10
CMG_O
Keep short
10
3.3
1.0
2.7k
10
1.0
Keep short
10
15
TN2106N3
LINE DRIVER
(ex.74AC244)
1SS193
+
100
0.1
2200p
10k
1SS226
Vcmgl
CMG Driver Circuit
+Vsrg,rsg
+
100
0.1
2200p
1SS226
10k
1SS193
Vcc (~ 5.5V)
SRG,RSG
TP2104N3
10
SRG_O,RSG_O
Keep short
10
3.3
0.1
2.7k
10
0.1
Keep short
10
3.3
TN2106N3
LINE DRIVER
(ex.74AC244)
1SS193
+
100
0.1
2200p
10k
1SS226
-Vsrg,rsg
SRG,RSG Driver Circuit
Notes:
A. All values are in Ohms and Microfarads unless otherwise noted.
B. These circuits are implemented on TI's EVM285SPD with negative-swing.
C. In these circuits, line driver IC before AC couple should drive over 5.5V swing because of
certain switching for discrete MOS-FETs (TP2104,TN2106).
D. In these circuits, pre-driver line distance from line driver IC output to AC couple input
should keep as short as it can.
E. The EL7156CS (Intersil/Elantec) driver is an acceptable alternative to the discreet
SRG circuit shown.
FIGURE 16. Typical CMG and SRG Driver Circuits
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
TEXAS
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POST OFFICE BOX 655303 * DALLAS TEXAS 75265
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
Vdd = 15V
3.3k
0.1
1.0k
VR
2.0k
Q1
ODBout
10
1.5k
ODB1
1.5k
5.6k
Q2
3.3k
Q3
3.3k
ODB2
3.3k
ODB Driver Circuit
+12V
+
0.1
100uF/16V
2SC3671B
2SC3671B
10
4.7
0.1
10
4.7
IAG1_IN
IAG1_OUT (To the device input pin)
4.7
4.7
10
10
2SA1431Y
2SA1431Y
-12V
+
100uF/16V
Current Bufferr Circuit
(For IAG1, same as the other gate)
Notes: A. All values are in Ohms and Microfarads unless otherwise noted.
FIGURE 17. Typical ODB Driver and Parallel Current Buffer Circuit
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
Mechanical data
The package for the TC285SPD consists of a ceramic base, a glass window, and a 28-pin
lead frame. The glass window is hermetically sealed to the package. The package leads
are configured in a dual-in-line arrangement and fit into mounting holes with 1,78 mm
center-to-center spacing. The TC285SPD sensor also contains a bipolar transistor inside
the package. The transistor load (2.2kOhm) needs to be connected to the VOUT pin
externally.
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
TEXAS
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TM
1004 x 1002 PIXEL IMPACTRON
TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
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TC285SPD-B0
CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
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complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
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