AD ADG3242BRJ-R2 2.5 v/3.3 v, 2-bit common control level translator bus switch Datasheet

2.5 V/3.3 V, 2-Bit Common Control
Level Translator Bus Switch
ADG3242
FUNCTIONAL BLOCK DIAGRAM
225 ps propagation delay through the switch
4.5 Ω switch connection between ports
Data rate 1.5 Gbps
2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small signal bandwidth 710 MHz
8-lead SOT-23 package
A0
B0
A1
B1
04309-001
FEATURES
BE
Figure 1.
APPLICATIONS
3.3 V to 2.5 V voltage translation
3.3 V to 1.8 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications
GENERAL DESCRIPTION
The ADG3242 is a 2.5 V or 3.3 V, 2-bit, 2-port, common control
digital switch. It is designed on a low voltage CMOS process, and
provides low power dissipation, yet gives high switching speed
and very low on resistance. This allows the inputs to be connected
to the outputs without additional propagation delay or generating
additional ground bounce noise.
These switches are enabled by means of a common bus enable
(BE) input signal. This digital switch allows a bidirectional signal
to be switched when on. In the off condition, signal levels up
to the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device
translates the outputs to 1.8 V. In addition, a level translating
select pin (SEL) is included. When SEL is low, VCC is reduced
internally, allowing for level translation between 3.3 V inputs
and 1.8 V outputs. This makes the device suitable for applications
requiring level translation between different supplies, such as
converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
1.
3.3 V or 2.5 V supply operation.
2.
Extremely low propagation delay through switch.
3.
4.5 Ω switches connect inputs to outputs.
4.
Level/voltage translation.
5.
Tiny SOT-23 package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADG3242
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Measurement Information .............................................. 11
Applications....................................................................................... 1
Bus Switch Applications ................................................................ 12
Functional Block Diagram .............................................................. 1
Mixed Voltage Operation, Level Translation.......................... 12
General Description ......................................................................... 1
3.3 V to 2.5 V Translation ......................................................... 12
Product Highlights ........................................................................... 1
2.5 V to 1.8 V Translation ......................................................... 12
Revision History ............................................................................... 2
3.3 V to 1.8 V Translation ......................................................... 12
Specifications..................................................................................... 3
Bus Isolation................................................................................ 13
Absolute Maximum Ratings............................................................ 4
Hot Plug and Hot Swap Isolation............................................. 13
ESD Caution.................................................................................. 4
Analog Switching ....................................................................... 13
Pin Configurations and Function Descriptions ........................... 5
High Impedance during Power-Up/Power-Down................. 13
Typical Performance Characteristics ............................................. 6
Outline Dimensions ....................................................................... 14
Terminology .................................................................................... 10
Ordering Guide............................................................................... 14
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added Table 4.................................................................................... 5
Changes to the Ordering Guide.................................................... 14
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG3242
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Symbol
Conditions
Min
VINH
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
Input Low Voltage
VINL
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage
II
IOZ
CAPACITANCE 3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD 4
Propagation Delay Matching 5
Bus Enable Time BE to A or B 6
Bus Disable Time BE to A or B6
Maximum Data Rate
Channel Jitter
DIGITAL SWITCH
On Resistance
On Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input 7
VP
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = SEL = 3.3 V, IO = −5 μA
VA/VB = VCC = SEL = 2.5 V, IO = −5 μA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = −5 μA
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
tPHL, tPLH
CL = 50 pF, VCC = SEL = 3 V
tPZH, tPZL
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
tPHZ, tPLZ
RON
∆RON
2.0
1.5
1.5
B Version 1
Typ 2
Max
±0.01
±0.01
±0.01
2.5
1.8
1.8
3.5
3.5
7
4
1
1
1
1
1
1
3.2
3
3
3
2.5
2.5
1.5
45
4.5
12
5
9
5
12
0.1
0.1
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA
2.3
ICC
∆ICC
Digital inputs = 0 V or VCC; SEL = VCC
Digital inputs = 0 V or VCC ; SEL = 0 V
VCC = 3.6 V, BE = 3.0 V; SEL = VCC
1
0.8
0.7
±1
±1
±1
2.9
2.1
2.1
0.01
0.1
0.15
Unit
V
V
V
V
μA
μA
μA
V
V
V
pF
pF
pF
pF
0.225
5
4.6
4
4
4
3.8
3.4
ns
ps
ns
ns
ns
ns
ns
ns
Gbps
ps p-p
8
28
9
18
8
0.5
0.5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
3.6
1
0.2
8
V
μA
mA
μA
Temperature range is as follows: B version: −40°C to +85°C.
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
2
Rev. A | Page 3 of 16
ADG3242
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VCC to GND
Digital Inputs to GND
DC Input Voltage
DC Output Current
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
Rating
−0.5 V to +4.6 V
−0.5 V to +4.6 V
−0.5 V to +4.6 V
25 mA per channel
−40°C to +85°C
−65°C to +150°C
150°C
206°C/W
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Rev. A | Page 4 of 16
ADG3242
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SEL
VCC
BE
ADI DIE MARK
ADG3242
VCC
7
SEL
TOP VIEW
A1 3 (Not to Scale) 6 B0
GND 4
5
B1
A0
ADG3242
TOP VIEW
(Not to Scale)
B0
A1
B1
Figure 2. Pin Configuration
GND
Figure 3. Die Pad Configuration (Die size: 550 μm × 820 μm)
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
BE
A0
A1
GND
B1
B0
SEL
VCC
Description
Bus Enable (Active Low).
Port A0, Input or Output.
Port A1, Input or Output.
Ground (0 V) Reference.
Port B1, Input or Output.
Port B0, Input or Output.
Level Translation Select.
Positive Power Supply Voltage.
Table 4. Die Pad Coordinates (Measured from the Center of the Die)
Mnemonic
BE
A0
A1
GND
B1
B0
SEL
VCC
X(μm)
+93
+102
+168
+126
−88
−168
−111
−7
Table 5. Truth Table
BE
SEL 1
Function
L
L
H
L
H
X
A0 = B0, A1 = B1, 3.3 V to 1.8 V Level Shifting.
A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting.
Disconnect.
1
04309-100
A0 2
8
04309-002
BE 1
SEL = 0 V only when VDD = 3.3 V ± 10%.
Rev. A | Page 5 of 16
Y(μm)
+303
+150
−139
−266
−247
+121
+279
+303
ADG3242
TYPICAL PERFORMANCE CHARACTERISTICS
40
20
TA = 25°C
SEL = VCC
35
VCC = 3.3V
SEL = VCC
VCC = 3V
15
30
VCC = 3.3V
RON (Ω)
RON (Ω)
25
20
10
+85°C
15
+25°C
10
5
VCC = 3.6V
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VA/VB (V)
0.5
0
1.0
1.5
2.0
VA/VB (V)
Figure 4. On Resistance vs. Input Voltage
04309-006
–40°C
0
04309-003
0
Figure 7. On Resistance vs. Input Voltage for Different Temperatures
40
15
TA = 25°C
SEL = VCC
35
VCC = 2.5V
SEL = VCC
VCC = 2.3V
30
10
VCC = 2.5V
RON (Ω)
RON (Ω)
25
20
15
+85°C
–40°C
5
VCC = 2.7V
+25°C
10
0
0.5
1.0
1.5
2.0
2.5
3.0
VA/VB (V)
0
04309-004
0
1.2
Figure 8. On Resistance vs. Input Voltage for Different Temperatures
40
3.0
35
1.0
VA/VB (V)
Figure 5. On Resistance vs. Input Voltage
TA = 25°C
SEL = 0V
0.5
0
04309-007
5
TA = 25°C
SEL = VCC
IO = –5µA
VCC = 3V
2.5
VCC = 3.6V
30
2.0
VCC = 3.3V
VOUT (V)
VCC = 3.3V
20
15
VCC = 3V
1.5
1.0
VCC = 3.6V
10
0
0
0.5
1.0
1.5
2.0
2.5
VA/VB (V)
3.0
3.5
0
Figure 6. On Resistance vs. Input Voltage
0
0.5
1.0
1.5
2.0
2.5
VA/VB (V)
Figure 9. Pass Voltage vs. VCC
Rev. A | Page 6 of 16
3.0
3.5
04309-008
0.5
5
04309-005
RON (Ω)
25
ADG3242
2.5
3.0
TA = 25°C
SEL = VCC
IO = –5µA
2.0
TA = 25°C
VA = 0V
BE = 0
VCC = 2.7V
2.5
VCC = 2.5V
VOUT (V)
VOUT (V)
2.0
1.5
VCC = 2.3V
1.0
VCC = 3.3V; SEL = 0V
1.5
VCC = SEL = 3.3V
1.0
0.5
0.5
1.0
1.5
2.0
2.5
3.0
VA/VB (V)
04309-009
0.5
0
0
0
0.02
0.04
0.06
0.10
0.08
IO (A)
Figure 10. Pass Voltage vs. VCC
04309-012
VCC = SEL = 2.5V
0
Figure 13. Output Low Characteristic
3.0
2.5
TA = 25°C
SEL = 0V
IO = –5µA
2.0
TA = 25°C
VA = VCC
BE = 0
VCC = 3.6V
2.5
VOUT (V)
VCC = 3.3V
VCC = 3V
1.0
VCC = SEL = 3.3V
1.5
1.0
0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VA/VB (V)
–0.06
–0.04
0
–0.02
Figure 14. Output High Characteristic
0
500
TA = 25°C
SEL = VCC
ON→OFF
CL = 1nF
TA = 25°C
450
–0.2
400
350
QINJ (pC)
VCC = SEL = 3.3V
300
VCC = 3.3V;
SEL = 0V
250
VCC = 2.5V
–0.4
200
VCC = 3.3V
–0.6
–0.8
150
100
–1.0
VCC = SEL = 2.5V
50
0
5
10
15
20
25
30
35
ENABLE FREQUENCY (MHz)
40
45
50
04309-011
ICC (µA)
–0.08
IO (A)
Figure 11. Pass Voltage vs. VCC
0
VCC = 3.3V; SEL = 0V
04309-013
0.5
0
0
–0.10
04309-010
0
VCC = SEL = 2.5V
Figure 12. ICC vs. Enable Frequency
–1.2
0
0.5
1.0
1.5
2.0
2.5
VA/VB (V)
Figure 15. Charge Injection vs. Source Voltage
Rev. A | Page 7 of 16
3.0
04309-014
VOUT (V)
2.0
1.5
ADG3242
2
4.0
1
ENABLE
VCC = SEL = 3.3V
3.5
0
2.5
TIME (ns)
–2
–3
–4
–6
–7
–8
0.03
VCC = 3.3V; SEL = 0V
1.5
TA = 25°C
VCC = 3.3V/2.5V
SEL = VCC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50Ω
0.1
DISABLE
2.0
1.0
0.5
1
10
100
1000
FREQUENCY (MHz)
0
–40
0
–30
20
40
60
80
Figure 19. Enable/Disable Time vs. Temperature
4.0
TA = 25°C
VCC = 3.3V/2.5V
SEL = VCC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50Ω
3.5
ENABLE
3.0
VCC = SEL = 2.5V
2.5
–40
TIME (ns)
ATTENUATION (dB)
–20
0
TEMPERATURE (°C)
Figure 16. Bandwidth vs. Frequency
–10
–20
04309-018
–5
04309-015
ATTENUATION (dB)
3.0
–1
–50
–60
DISABLE
2.0
1.5
–70
1.0
–80
1
10
100
1000
FREQUENCY (MHz)
0
–40
–30
90
80
–50
–60
80
VCC = SEL = 3.3V
VIN = 1.5V p-p
20dB ATTENUATION
60
50
40
–70
30
–80
20
–90
10
1
60
70
–40
–100
0.1
40
100
TA = 25°C
VCC = 3.3V/2.5V
SEL = VCC
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50Ω
10
100
FREQUENCY (MHz)
1000
04309-017
ATTENUATION (dB)
–20
20
Figure 20. Enable/Disable Time vs. Temperature
JITTER (ps p-p)
–10
0
TEMPERATURE (°C)
Figure 17. Crosstalk vs. Frequency
0
–20
0
0.5
0.7
0.9
1.1
1.3
1.5
1.7
DATA RATE (Gbps)
Figure 21. Jitter vs. Data Rate; PRBS 31
Figure 18. Off Isolation vs. Frequency
Rev. A | Page 8 of 16
1.9
04309-020
0.1
04309-016
–100
0.03
04309-019
0.5
–90
ADG3242
100
95
90
80
75
70
60
20mV/DIV
200ps/DIV
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) × 100%
50
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
DATA RATE (Gbps)
Figure 22. Eye Width vs. Data Rate; PRBS 31
50mV/DIV
200ps/DIV
VCC = 3.3V
SEL = 3.3V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25°C
VCC = 2.5V
SEL = 2.5V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25°C
04309-021
55
Figure 24. Eye Pattern; 1.244 Gbps, VCC = 2.5 V; PRBS 31
Figure 23. Eye Pattern; 1.5 Gbps, VCC = 3.3 V; PRBS 31
Rev. A | Page 9 of 16
04309-023
65
04309-022
EYE WIDTH (%)
85
VCC = SEL = 3.3V
VIN = 1.5V p-p
20dB ATTENUATION
ADG3242
TERMINOLOGY
VCC
Positive power supply voltage.
CIN
Control input capacitance. This consists of BE and SEL.
GND
Ground (0 V) reference.
ICC
Quiescent power supply current. This current represents the
leakage current between the VCC and ground pins. It is measured
when all control inputs are at logic high or low level and the
switches are off.
VINH
Minimum input voltage for Logic 1.
VINL
Maximum input voltage for Logic 0.
ΔICC
Extra power supply current component for the EN control input
when the input is not driven at the supplies.
II
Input leakage current at the control inputs.
IOZ
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
tPLH, tPHL
Data propagation delay through the switch in the on state. Propagation delay is related to the RC time constant RON × CL, where CL
is the load capacitance.
IOL
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
tPZH, tPZL
Bus enable times. These are the times taken to cross the VT in
response to the control signal, BE.
VP
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
tPHZ, tPLZ
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
They are measured as the time taken for the output voltage to
change by VΔ from the original quiescent level, with reference
to the logic level transition at the control input. (See Figure 27
for enable and disable times.)
RON
Ohmic resistance offered by a switch in the on state. It is measured
at a given voltage by forcing a specified amount of current through
the switch.
ΔRON
On resistance match between any two channels, that is, RON max
to RON min.
CX OFF
Off switch capacitance.
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
CX ON
On switch capacitance.
Rev. A | Page 10 of 16
ADG3242
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that
is used is VIN and VOUT where:
0V
PULSE
GENERATOR
VOUT
VIN
tPZL
2 × VCC
CL
VOUT
SW1 @ 2VCC
VIN = VCC
VOUT
SW1 @ GND
GND
RL
VCC
VCC
VT
VL + VΔ
VL
tPZH
DUT
RT
VIN = 0V
tPLZ
tPHZ
VH
VH – VΔ
VT
0V
0V
RL
Figure 27. Enable and Disable Times
NOTES
1. PULSE GENERATOR FOR ALL PULSES: tR ≤ 2.5ns, tF ≤ 2.5ns,
FREQUENCY ≤ 10MHz.
2. CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
3. RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT
OF THE PULSE GENERATOR.
04309-024
Table 6. Switch Position
Figure 25. Load Circuit
Test
tPLZ, tPZL
tPHZ, tPZH
S1
2 × VCC
GND
VIH
CONTROL
INPUT BE
VT
tPLH
VH
VT
VOUT
VL
04309-025
tPLH
0V
Figure 26. Propagation Delay
Table 7. Test Conditions
Symbol
RL
VΔ
CL
VT
VCC = 3.3 V ± 0.3 V (SEL = VCC)
VCC = 2.5 V ± 0.2 V (SEL = VCC)
VCC = 3.3 V ± 0.3 V (SEL = 0 V)
500
300
50
1.5
500
150
30
0.9
500
150
30
0.9
Rev. A | Page 11 of 16
Unit
Ω
mV
pF
V
04309-026
SW1
VINH
VT
CONTROL INPUT BE
VIN = VA and VOUT = VB, or VIN = VB and VOUT = VA
VCC
DISABLE
ENABLE
ADG3242
BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL
TRANSLATION
2.5 V TO 1.8 V TRANSLATION
Bus switches provide an ideal solution for interfacing between
mixed voltage systems. The ADG3242 is suitable for applications
where voltage translation from 3.3 V technology to a lower voltage
technology is needed. This device translates from 3.3 V to 1.8 V,
from 2.5 V to 1.8 V, or from a bidirectional 3.3 V directly to 2.5 V.
When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to VCC, the maximum output signal is also clamped within
a voltage threshold below the VCC supply. In this case, the output
is limited to approximately 1.8 V, as shown in Figure 32.
2.5V
Figure 28 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor does not have 3.3 V tolerant inputs,
therefore, placing the ADG3242 between the two devices allows
the devices to communicate easily. The bus switch directly connects
the two blocks, therefore introducing minimal propagation delay,
timing skew, or noise.
3.3V
ADG3242
Figure 31. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC
VOUT
2.5V SUPPLY
SEL = 2.5V
2.5V
3.3V
1.8V
04309-030
2.5V
Figure 28. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
VIN
0V
3.3 V TO 2.5 V TRANSLATION
When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to VCC, the maximum output signal is clamped to within a
voltage threshold below the VCC supply. In this case, the output
is limited to 2.5 V, as shown in Figure 30. This device can be used
for translation from 2.5 V to 3.3 V devices and also between two
3.3 V devices.
3.3V
3.3V
2.5V
2.5V
2.5V
04309-028
ADG3242
SWITCH
INPUT
2.5V
04309-031
2.5V
MICROPROCESSOR
SWITCH
OUTPUT
3.3V ADC
04309-027
ADG3242
1.8V
Figure 32. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V TO 1.8 V TRANSLATION
The ADG3242 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the SEL
pin. The SEL pin is an active low control pin. SEL activates internal circuitry in the ADG3242 that allows voltage translation
between 3.3 V devices and 1.8 V devices.
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal is clamped to 1.8 V, as shown in Figure 34.
To do this, the SEL pin must be tied to Logic 0. If SEL is unused,
it can be tied directly to VCC.
3.3V
Figure 29. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
VOUT
3.3V SUPPLY
SEL = 3.3V
ADG3242
3.3V
1.8V
SWITCH
OUTPUT
04309-032
2.5V
Figure 33. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
3.3V
VOUT
3.3V SUPPLY
SEL = 0V
1.8V
SWITCH
OUTPUT
Figure 30. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
VIN
0V
SWITCH
INPUT
3.3V
04309-033
SWITCH
INPUT
04309-029
VIN
0V
Figure 34. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Rev. A | Page 12 of 16
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the specifications. Because the ADG3242 is designed specifically for
applications that do not need drive, yet require simple logic functions, it solves this requirement. The device isolates access to
the bus, thus minimizing capacitance loading.
CPU
RAM
PLUG-IN
CARD (1)
CARD I/O
PLUG-IN
CARD (2)
CARD I/O
04309-035
BUS ISOLATION
ADG3242 ADG3242
ADG3242
BUS
Figure 36. ADG3242 in a Hot Plug Application
LOAD A
LOAD C
BUS SWITCH
LOCATION
LOAD B
LOAD D
04309-034
BUS/
BACKPLANE
Figure 35. Location of Bus Switched in a Bus Isolation Application
HOT PLUG AND HOT SWAP ISOLATION
The ADG3242 is suitable for hot swap and hot plug applications.
The output signal of the ADG3242 is limited to a voltage that
is below the VCC supply, as shown in Figure 30, Figure 32, and
Figure 34. Thus, the switch acts like a buffer to take the impact
from the hot insertion, protecting vital and expensive chipsets
from damage.
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 36 shows a typical example of this type of application.
There are many systems, such as docking stations, PCI boards for
servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be isolated
prior to insertion or removal, there is more control over the hot
swap event. This isolation can be achieved using bus switches. The
bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the
hot swap card must connect to the ground pin of the backplane
before connecting to any other signal or power pins.
ANALOG SWITCHING
Bus switches are used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller on and off channel capacitance, and better
frequency performance than their analog counterparts. The
bus switch channel itself, consisting solely of an NMOS switch,
limits the operating voltage (see Figure 4 for a typical plot), but
in many cases, this does not present an issue.
HIGH IMPEDANCE DURING POWER-UP/POWERDOWN
To ensure the high impedance state during power-up or powerdown, BE must be tied to VCC through a pull-up resistor. The
minimum value of the resistor is determined by the current sinking capability of the driver.
Rev. A | Page 13 of 16
ADG3242
OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.38
0.22
0.15 MAX
0.22
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 37. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG3242BRJ-R2
ADG3242BRJ-REEL
ADG3242BRJ-REEL7
ADG3242BRJZ-REEL71
ADG3242BCZ-SF31
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Small Outline Transistor [SOT-23]
8-Lead Small Outline Transistor [SOT-23]
8-Lead Small Outline Transistor [SOT-23]
8-Lead Small Outline Transistor [SOT-23]
Die
Z = Pb-free part.
Rev. A | Page 14 of 16
Package Option
RJ-8
RJ-8
RJ-8
RJ-8
Chip
Branding
SCA
SCA
SCA
SOU
ADG3242
NOTES
Rev. A | Page 15 of 16
ADG3242
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04309-0-9/06(A)
Rev. A | Page 16 of 16
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