SPANSION MBM29F017A-70PFTN Flash memory cmos 16m (2m x 8) bit Datasheet

TM
SPANSION Flash Memory
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20843-4E
FLASH MEMORY
CMOS
16M (2M × 8) BIT
MBM29F017A-70/-90/-12
■ DESCRIPTION
The MBM29F017A is a 16M-bit, 5.0 V-Only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes
of data is divided into 32 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ7 to
DQ0. The MBM29F017A is offered in a 48-pin TSOP package. This device is designed to be programmed insystem with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations.
The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F017A offers access times between 70 ns and 120 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29F017A
VCC = 5.0 V ±5%
-70
—
—
VCC = 5.0 V ±10%
—
-90
-12
Max Address Access Time (ns)
70
90
120
Max CE Access Time (ns)
70
90
120
Max OE Access Time (ns)
40
40
50
Ordering Part No.
■ PACKAGES
48-pin Plastic TSOP (1)
40-pin Plastic SON
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(LCC-40P-M02)
MBM29F017A-70/-90/-12
(Continued)
The MBM29F017A is command set compatible with JEDEC standard single-supply Flash standard. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 12.0 V Flash or EPROM devices.
The MBM29F017A is programmed by executing the program command sequence. This will invoke the Embedded
ProgramTM Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This will invoke the Embedded EraseTM Algorithm which is an
internal algorithm that automatically preprograms the array if it is not already programmed before executing the
erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margin.
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within one
second (if already completely preprogrammed). The MBM29F017A is erased when shipped from the factory.
The MBM29F017A device also features hardware sector group protection. This feature will disable both program
and erase operations in any combination of eight sector groups of memory. A sector group consists of four
adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
The device features single 5.0 V power supply operation for both read and program functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of
DQ7, or by the Toggle Bit I feature on DQ6 or RY/BY output pin. Once the end of a program or erase cycle has
been completed, the device automatically resets to the read mode.
The MBM29F017A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F017A memory electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
2
MBM29F017A-70/-90/-12
■ FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
• 48-pin TSOP, 40-pin SON
• Minimum 100,000 write/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Uniform sectors of 64K bytes each
Any combination of sectors can be erased. Also supports full chip erase
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/BUSY output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
• Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 4 adjacent sectors of 64K bytes each)
• Temporary sector groups unprotection
Hardware method temporarily enable any combination of sectors from write or erase operations
3
MBM29F017A-70/-90/-12
■ PIN ASSIGNMENT
TSOP(1)
N.C.
N.C.
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
N.C.
RESET
A11
A10
A9
A8
A7
A6
A5
A4
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
MBM29F017A
Normal Bend
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
N.C.
A20
N.C.
WE
OE
RY/BY
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
N.C.
N.C.
(FPT-48P-M19)
N.C.
N.C.
A4
A5
A6
A7
A8
A9
A10
A11
RESET
N.C.
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
N.C.
N.C.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29F017A
Reverse Bend
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
N.C.
N.C.
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
RY/BY
OE
WE
N.C.
A20
N.C.
N.C.
(FPT-48P-M20)
(Continued)
4
MBM29F017A-70/-90/-12
(Continued)
(TOP VIEW)
N.C.
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
DQ4
DQ5
DQ6
DQ7
RY/BY
OE
WE
A20
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(Marking side)
MBM29F017A
SON-40
A4
A5
A6
A7
A8
A9
A10
A11
RESET
VCC
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
N.C.
(LCC-40P-M02)
■ PIN DESCRIPTION
Pin name
Function
A20 to A0
Address Inputs
DQ7 to DQ0
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready-Busy Output
RESET
Hardware Reset Pin/Sector Protection Unlock
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
5
MBM29F017A-70/-90/-12
■ BLOCK DIAGRAM
RY/BY
Buffer
DQ7 to DQ0
RY/BY
VCC
VSS
WE
Input/Output
Buffers
Erase Voltage
Generator
State
Control
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Low VCC Detector
A20 to A0
6
Timer for
Program/Erase
Address
Latch
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29F017A-70/-90/-12
■ LOGIC SYMBOL
21
A20 to A0
8
DQ7 to DQ0
CE
OE
WE
RESET
RY/BY
7
MBM29F017A-70/-90/-12
■ DEVICE BUS OPERATION
MBM29F017A User Bus Operations Table
CE
OE
WE
A0
A1
A6
A9
Auto-Select Manufacturer Code *1
L
L
H
L
L
L
VID
Code
H
Auto-Select Device Code *1
L
L
H
H
L
L
VID
Code
H
Read *
L
L
H
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
Write
L
H
L
A0
A1
A6
A9
DIN
H
Enable Sector Group Protection *2
L
VID
X
X
X
VID
X
H
Verify Sector Group Protection *2
L
L
H
L
H
L
VID
Code
H
Temporary Sector Group Unprotection
X
X
X
X
X
X
X
X
VID
Reset (Hardware)
X
X
X
X
X
X
X
High-Z
L
Operation
3
Legend: L = VIL, H = VIH, X = VIL or VIH,
DQ7 to DQ0 RESET
= Pulse Input. See ■DC CHARACTERISTICS for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
“MBM29F017A Command Definitions”.
*2 : Refer to the section on Sector Group Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
8
MBM29F017A-70/-90/-12
MBM29F017A Command Definitions Table
Command
Sequence
Bus
Write
Cycles
Req'd
Bus
First Bus Second Bus Third Bus Fourth
Fifth Bus
Sixth Bus
Read/Write
Write Cycle Write Cycle Write Cycle
Write
Cycle
Write
Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
1
1
XXXh
—
—
—
—
—
Reset/Read*1
3
XXXh AAh XXXh
55h
XXXh
F0h
RA*2
RD*2
Autoselect
3
XXXh AAh XXXh
55h
XXXh
Byte Program
4
XXXh AAh XXXh
55h
Chip Erase
6
XXXh AAh XXXh
Sector Erase
6
XXXh AAh XXXh
Sector Erase
Suspend
1
Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0h)
Sector Erase
Resume
1
Erase can be resumed after suspend with Addr (“H” or “L”). Data (30h)
Read/Reset*
F0h
—
—
—
—
—
—
—
—
—
90h
IA*
2
ID*
2
—
—
—
—
XXXh
A0h
PA
PD
—
—
—
—
55h
XXXh
80h
XXXh AAh XXXh
55h
XXXh
10h
55h
XXXh
80h
XXXh AAh XXXh
55h
SA
30h
*1 : Either of the two reset commands will reset the device.
*2 : The fourth bus cycle is only for read.
Notes : • Bus operations are defined in “MBM29F017A User Bus Operations”.
• RA = Address of the memory location to be read.
IA= Autoselect read address that sets A6, A1, A0.
PA= Address of the memory location to be programmed. Addresses are latched on the falling edge
of the WE pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select
any sector.
• RD = Data read from location RA during read operation.
ID= Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.
• The command combinations not described in “MBM29F017A Command Definitions” are illegal.
MBM29F017A Sector Protection Verify Autoselect Codes Table
A18 to A20
Type
A6
A1
A0
Code
(HEX) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture’s
Code
X
X
X
VIL
VIL
VIL
04h
0
0
0
0
0
1
0
0
Device Code
X
X
X
VIL
VIL
VIH
3Dh
0
0
1
1
1
1
0
1
Sector Group
Protection
Sector Group
Addresses
VIL
VIH
VIL
01h*
0
0
0
0
0
0
0
1
* : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
9
MBM29F017A-70/-90/-12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• Thirty two 64K byte sectors
• 8 sector groups each of which consists of 4 adjacent sectors in the following pattern; sectors 0-3, 4-7, 8-11,
12-15, 16-19, 20-23, 24-27, and 28-31
• Individual-sector or multiple-sector erase capability
• Sector group protection is user-definable
SA31
64K byte
SA30
64K byte
SA29
64K byte
SA28
64K byte
1FFFFFh
1EFFFFh
1DFFFFh
Sector
Group 7
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
32 Sectors Total
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
10
SA3
64K byte
SA2
64K byte
SA1
64K byte
SA0
64K byte
03FFFFh
02FFFFh
01FFFFh
00FFFFh
000000h
Sector
Group 0
MBM29F017A-70/-90/-12
Sector Address Table
A20
A19
A18
A17
A16
Address Range
SA0
0
0
0
0
0
000000h to 00FFFFh
SA1
0
0
0
0
1
010000h to 01FFFFh
SA2
0
0
0
1
0
020000h to 02FFFFh
SA3
0
0
0
1
1
030000h to 03FFFFh
SA4
0
0
1
0
0
040000h to 04FFFFh
SA5
0
0
1
0
1
050000h to 05FFFFh
SA6
0
0
1
1
0
060000h to 06FFFFh
SA7
0
0
1
1
1
070000h to 07FFFFh
SA8
0
1
0
0
0
080000h to 08FFFFh
SA9
0
1
0
0
1
090000h to 09FFFFh
SA10
0
1
0
1
0
0A0000h to 0AFFFFh
SA11
0
1
0
1
1
0B0000h to 0BFFFFh
SA12
0
1
1
0
0
0C0000h to 0CFFFFh
SA13
0
1
1
0
1
0D0000h to 0DFFFFh
SA14
0
1
1
1
0
0E0000h to 0EFFFFh
SA15
0
1
1
1
1
0F0000h to 0FFFFFh
SA16
1
0
0
0
0
100000h to 10FFFFh
SA17
1
0
0
0
1
110000h to 11FFFFh
SA18
1
0
0
1
0
120000h to 12FFFFh
SA19
1
0
0
1
1
130000h to 13FFFFh
SA20
1
0
1
0
0
140000h to 14FFFFh
SA21
1
0
1
0
1
150000h to 15FFFFh
SA22
1
0
1
1
0
160000h to 16FFFFh
SA23
1
0
1
1
1
170000h to 17FFFFh
SA24
1
1
0
0
0
180000h to 18FFFFh
SA25
1
1
0
0
1
190000h to 19FFFFh
SA26
1
1
0
1
0
1A0000h to 1AFFFFh
SA27
1
1
0
1
1
1B0000h to 1BFFFFh
SA28
1
1
1
0
0
1C0000h to 1CFFFFh
SA29
1
1
1
0
1
1D0000h to 1DFFFFh
SA30
1
1
1
1
0
1E0000h to 1EFFFFh
SA31
1
1
1
1
1
1F0000h to 1FFFFFh
11
MBM29F017A-70/-90/-12
Sector Group Addresses Table
12
A20
A19
A18
Sectors
SGA0
0
0
0
SA0 to SA3
SGA1
0
0
1
SA4 to SA7
SGA2
0
1
0
SA8 to SA11
SGA3
0
1
1
SA12 to SA15
SGA4
1
0
0
SA16 to SA19
SGA5
1
0
1
SA20 to SA23
SGA6
1
1
0
SA24 to SA27
SGA7
1
1
1
SA28 to SA31
MBM29F017A-70/-90/-12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F017A has two control functions which must be satisfied in order to obtain data at the outputs. CE
is the power control and should be used for a device selection. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.)
Standby Mode
There are two ways to implement the standby mode on the MBM29F017A device, one using both the CE and
RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.
Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE and
RESET pins held at VIH. Under this condition the current is reduced to approximately 1 mA. During Embedded
Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard
access time (tCE) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ±0.3 V
(CE = “H” or “L”). Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved
with RESET pin held at VIL (CE = “H” or “L”). Under this condition the current required is reduced to approximately
1 mA. Once the RESET pin is taken high, the device requires tRH ns of wake up time before outputs are valid for
read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All
addresses are DON'T CARES except A0, A1, and A6. (See “MBM29F017A Sector Protection Verify Autoselect
Codes” in ■DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F017A is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in “MBM29F017A Command Definitions” in ■DEVICE BUS OPERATION. (Refer to
Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04h) and byte 1 (A0 = VIH) the device identifier
code for MBM29F017A = ADh. These two bytes are given in the “MBM29F017A Sector Protection Verify
Autoselect Codes” in ■DEVICE BUS OPERATION. All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect,
A1 must be VIL. (See “MBM29F017A Sector Protection Verify Autoselect Codes” in ■DEVICE BUS OPERATION.)
The Autoselect mode also facilitates the determination of sector group protection in the system. By performing
a read operation at the address location XX02h with the higher order address bits A18, A19, and A20 set to the
desired sector group address, the device will return 01h for a protected sector group and 00h for a non-protected
sector group.
13
MBM29F017A-70/-90/-12
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29F017A features hardware sector group protection. This feature will disable both program and erase
operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see
“Sector Group Addresses” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE). The sector group protection
feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups
unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL. The sector addresses (A20, A19, and A18) should be set to the sector to be protected.
“Sector Address Table” and “Sector Group Addresses” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE
define the sector address for each of the thirty two (32) individual sectors, and the sector group address for each
of the eight (8) individual group sectors. Programming of the protection circuitry begins on the falling edge of
the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during
the WE pulse. Refer to figures 14 and 21 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A20, A19, and A18) while (A6, A1, A0) = (0,
1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce
00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are don’t care.
Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, and
A18) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See
“MBM29F017A Sector Protection Verify Autoselect Codes” in ■DEVICE BUS OPERATION for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29F017A device
in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high
voltage (12 V). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to “AC Waveforms for Sector Group Protection” in ■TIMING DIAGRAM
and “Sector Group Protection Algorithm” in ■FLOW CHART.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. “MBM29F017A Command Definitions” in ■DEVICE BUS OPERATION defines the valid register
command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only
while the Sector Erase operation is in progress. Moreover, both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
14
MBM29F017A-70/-90/-12
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h returns the device code ADh. (See “MBM29F017A Sector Protection Verify Autoselect
Codes” in ■DEVICE BUS OPERATION.)
All manufacturer and device codes will exhibit odd parity with the DQ7 defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02h.
Scanning the sector group addresses (A18, A19, A20) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at
device output DQ0 for a protected sector group.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded ProgramTM Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
This automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags”.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“DQ2 vs. DQ6” in ■TIMING DIAGRAM illustrates the Embedded Programming Algorithm using typical command
strings and bus operations.
15
MBM29F017A-70/-90/-12
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
“Embedded Programming Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using
typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29F017A Command
Definitions” in ■DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command
to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50
µs otherwise that command will not be accepted and erasure will start. It is recommended that processor
interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the
last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE will initiate the
execution of the Sector Erase command (s). If another falling edge of the WE occurs within the 50 µs time-out
window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer.) Any commands other than Sector Erase or Erase Suspend during this time-out period
will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution
has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and allow them to
complete. (Refer to the Write Operation Status section for DQ3, Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 31).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector (s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased.
“Embedded Programming Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using
typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded ProgramTM Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
16
MBM29F017A-70/-90/-12
Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase operation. The addresses are “don't-cares” when writing
the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 15 ms to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY
output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the
erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Byte Program mode except that the data
must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended
sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I
(DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from the byte
program address while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Write Operation Status
Hardware Sequence Flags Table
Status
DQ7
DQ6
DQ5
DQ3
DQ2
Embedded ProgramTM Algorithm
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle*1
0
0
1*2
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Embedded EraseTM Algorithm
In progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Suspended
Mode
Embedded ProgramTM Algorithm
Exceeded
Time Limits
Embedded EraseTM Algorithm
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Notes : • DQ0 and DQ1 are reserved pins for future use.
• DQ4 is Fujitsu internal use only.
17
MBM29F017A-70/-90/-12
DQ7
Data Polling
The MBM29F017A device features Data Polling as a method to indicate to the host that the embedded algorithms
are in progress or completed. During the Embedded ProgramTM Algorithm, an attempt to read the device will
produce the complement of the data last written to DQ7. Upon completion of the Embedded ProgramTM Algorithm,
an attempt to read the device will produce the true data last written to DQ7. During the Embedded EraseTM
Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded
EraseTM Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data
Polling (DQ7) is shown in “Embedded EraseTM Algorithm” in ■FLOW CHART.
Data polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend
mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector group. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See “Hardware Sequence
Flags”.)
See “AC Waveforms Chip/Sector Erase Operations” in ■TIMING DIAGRAM for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29F017A also features the “Toggle Bit I” as a method to indicate to the host system that the embedded
algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the
six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase
WE pulse. The Toggle Bit I is active during the sector erase time out.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See “AC Waveforms for Data Polling During Embedded Algorithm Operations” in ■TIMING
DIAGRAM for the Toggle Bit I timing specifications and diagrams.
18
MBM29F017A-70/-90/-12
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in “MBM29F017A User Bus Operations” in ■DEVICE BUS
OPERATION.
The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded ProgramTM Algorithm. Hence, the
system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing
limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3
were high on the second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags”
DQ2
Toggle Bit II
This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded EraseTM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded EraseTM Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase Suspend Read *1
(Erase-Suspended Sector)
1
1
Toggle
DQ7 *2
Toggle
1 *2
Mode
Program
Erase Suspend Program
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
19
MBM29F017A-70/-90/-12
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles
while DQ6 does not.) See also “Hardware Sequence Flags” and “Temporary Sector Group Unprotection” in
■TIMING DIAGRAM.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F017A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29F017A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull-up resistor to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during RESET pulse. Refer to “AC Waveforms for Toggle Bit I During Embedded Algorithm
Operations” in ■TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset
The MBM29F017A device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL)
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20 ms after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires tRH ns of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F017A is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
20
MBM29F017A-70/-90/-12
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Handling of SON Package
The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.
21
MBM29F017A-70/-90/-12
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Storage Temperature
Ambient Temperature with Power Applied
Voltage with respect to Ground All pins
except A9, OE, and RESET *1, *2
Power Supply Voltage *1
1, 3
A9, OE, and RESET * *
Rating
Unit
Min
Max
Tstg
–55
+125
°C
TA
–40
+85
°C
VIN, VOUT
–2.0
+7.0
V
VCC
–2.0
+7.0
V
VIN
–2.0
+13.5
V
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins is VCC +0.5 V. During voltage
transitions, outputs may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE, and
RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and
power supply voltage (VIN − VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, and RESET
pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Ambient Temperature
TA
Power Supply Voltages *
VCC
Condition
Value
Min
Max
-70
–20
+70
-90/-12
–40
+85
-70
+4.75
+5.25
-90/-12
+4.50
+5.50
Unit
°C
V
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
22
MBM29F017A-70/-90/-12
■ MAXIMUM OVERSHOOT/ MAXIMUM UNDERSHOOT
+0.8 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
VCC+2.0 V
VCC+0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform
20 ns
+14.0 V
+13.0 V
VCC+0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Maximum Overshoot Waveform
23
MBM29F017A-70/-90/-12
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Test Conditions
Unit
Min
Max
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 12.5 V
—
50
µA
VCC Active Current *1
ICC1
CE = VIL, OE = VIH
—
40
mA
VCC Active Current *2
ICC2
CE = VIL, OE = VIH
—
45
mA
VCC = VCC Max, CE = VIH, RESET = VIH
—
1
mA
VCC = VCC Max, CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
1
5
µA
VCC = VCC Max, RESET = VIL
—
1
mA
VCC = VCC Max RESET = VSS ±0.3 V
1
5
µA
VCC Current (Standby)
VCC Current (Standby, Reset)
ICC3
ICC4
Input Low Level
VIL
—
–0.5
0.8
V
Input High Level
VIH
—
2.0
VCC+0.5
V
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *3, *4
VID
—
11.5
12.5
V
Output Low Voltage Level
VOL
IOL = 12.0 mA, VCC = VCC Min
—
0.45
V
VOH1
IOH = –2.5 mA, VCC = VCC Min
2.4
—
V
VOH2
IOH = –100 µA
VCC–0.4
—
V
3.2
4.2
V
Output High Voltage Level
Low VCC Lock-Out Voltage
VLKO
—
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Applicable to sector protection function.
*4 : (VID –VCC) do not exceed 9 V.
24
MBM29F017A-70/-90/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value
Symbol
Parameter
Test
Setup
-70*
JEDEC Standard
1
-90*2
-12*2
Unit
Min Max Min Max Min Max
70

90

120

ns
CE = VIL
OE = VIL

70

90

120
ns
OE = VIL

70

90

120
ns
—

40

40

50
ns
tDF
—

20

20

30
ns
tGHQZ
tDF
—

20

20

30
ns
tAXQX
tOH
—
0

0


0
ns
—
tREADY
—

20

20

20
µs
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
tOE
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
Output Hold Time From Addresses,
CE or OE, whichever occurs first
RESET Pin Low to Read Mode
—
*2 : Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V or 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 0.8 V and 2.0 V
*1 : Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
5.0 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes : • CL = 30 pF including jig capacitance
• CL = 100 pF including jig capacitance
Test Conditions
25
MBM29F017A-70/-90/-12
• Write (Erase/Program) Operations
MB29F017A
Symbol
Parameter
-70
-90
-12
JEDEC Standard Min Typ Max Min Typ Max Min
Unit
Typ Max
Write Cycle Time
tAVAV
tWC
70


90


120


ns
Address Setup Time
tAVWL
tAS
0


0


0


ns
Address Hold Time
tWLAX
tAH
45


45


50


ns
Data Setup Time
tDVWH
tDS
30


45


50


ns
Data Hold Time
tWHDX
tDH
0


0


0


ns
Output Enable Setup Time
—
tOES
0


0


0


ns
Read
Output
Enable
Hold Time Toggle and Data Polling
0


0


0


ns
—
tOEH
10


10


10


ns
Read Recover Time Before Write
(OE High to WE Low)
tGHWL
tGHWL
0


0


0


ns
Read Recover Time Before Write
(OE High to CE Low)
tGHEL
tGHEL
0


0


0


ns
CE Setup Time
tELWL
tCS
0


0


0


ns
WE Setup Time
tWLEL
tWS
0


0


0


ns
CE Hold Time
tWHEH
tCH
0


0


0


ns
WE Hold Time
tEHWH
tWH
0


0


0


ns
Write Pulse Width
tWLWH
tWP
35


45


50


ns
CE Pulse Width
tELEH
tCP
35


45


50


ns
Write Pulse Width High
tWHWL
tWPH
20


20


20


ns
CE Pulse Width High
tEHEL
tCPH
20


20


20


ns
Programming Operation
tWHWH1
tWHWH1

8


8


8

µs
Sector Erase Operation *1
tWHWH2
tWHWH2

1


1


1

s


8


8


8
s
Delay Time from Embedded
Output Enable
—
tEOE


40


40


50
ns
VCC Setup Time
—
tVCS
50


50


50


µs
—
tVLHT
4


4


4


µs
—
tWPP
100


100


100


µs
OE Setup Time to WE Active *2
—
tOESP
4


4


4


µs
2
CE Setup Time to WE Active *
—
tCSP
4


4


4


µs
Recover Time From RY/BY
—
tRB
0


0


0


ns
Voltage Transition Time *
2
Write Pulse Width *2
(Continued)
26
MBM29F017A-70/-90/-12
(Continued)
MB29F017A
Symbol
Parameter
-70
-90
-12
Unit
Min Typ Max Min Typ Max Min Typ Max
JEDEC
Standard
RESET Hold Time Before
Read
—
tRH
50


50


50


ns
Program/Erase Valid to RY/
BY Delay
—
tBUSY


70


90


120
ns
Rise Time to VID *2
—
tVIDR
500


500


500


ns
RESET Pulse Width
—
tRP
500


500


500


ns
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection operation.
27
MBM29F017A-70/-90/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min
Typ
Max
Sector Erase Time
—
1
8
s
Excludes 00h programming
prior to erasure
Byte Programming Time
—
8
150
µs
Excludes system-level
overhead
Chip Programming Time
—
16.8
40
s
Excludes system-level
overhead
100,000
—
—
cycle
Erase/Program Cycle
■ TSOP PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
Max
Input Capacitance
CIN
VIN = 0
8
10
pF
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
9
10
pF
Note : Test conditions TA = +25°C, f = 1.0 MHz
■ SON PIN CAPACITANCE
Value
Parameter
Symbol
Unit
Typ
Max
Input Capacitance
CIN
VIN = 0
8
10
pF
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
9
10
pF
Note : Test conditions TA = +25°C, f = 1.0 MHz
28
Test Setup
MBM29F017A-70/-90/-12
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
H or L
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
tRC
Address Stable
A20 to A0
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
DQ7 to DQ 0
High-Z
Output Valid
AC Waveforms for Read Operations
29
MBM29F017A-70/-90/-12
tRC
Address Stable
A20 to A0
tACC
tRH
RESET
tOH
DQ7 to DQ0
High-Z
Output Valid
AC Waveforms for Read Operations
30
MBM29F017A-70/-90/-12
3rd Bus Cycle
Data Polling
XXXh
A20 to A0
tWC
PA
tAS
PA
tAH
tRC
CE
tCS
tCH
tCE
OE
tWP
tWHWH1
tWPH
tOE
tGHWL
WE
tDS
tOH
tDH
A 0h
Data
PD
DQ 7
DOUT
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles of four bus cycle sequence.
Alternate WE Controlled Program Operation Timings
31
MBM29F017A-70/-90/-12
3rd Bus Cycle
Data Polling
PA
XXXh
A20 to A0
tAS
tWC
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
tDH
A0h
PD
DQ 7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles of four bus cycle sequence.
Alternate CE Controlled Program Operation Timings
32
MBM29F017A-70/-90/-12
XXXh
A20 to A0
XXXh
tWC
tAS
XXXh
XXXh
XXXh
SA*
tAH
CE
tCS
tCH
OE
tWP
tGHWL
tWPH
WE
tDS
10h for Chip Erase
tDH
AAh
Data
55h
80h
AAh
55h
10h/30h
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = ×××h for Chip Erase.
AC Waveforms Chip/Sector Erase Operations
33
MBM29F017A-70/-90/-12
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
High-Z
DQ7 =
Valid Data
DQ7
tWHWH1 or 2
DQ6 to DQ0
DQ6 to DQ0 = Invalid
High-Z
DQ6 to DQ0
Valid Data
tOE
* : DQ7 = Valid Data (The device has completed the Embedded operation).
AC Waveforms for Data Polling During Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
Data
(DQ7 to DQ0)
DQ6 = Toggle
DQ6 =
Stop Toggling
DQ6 = Toggle
DQ7 to DQ0
Valid
tOE
* : DQ6 = Stops Toggling (The device has completed the Embedded operation).
AC Waveforms for Toggle Bit I During Embedded Algorithm Operations
34
MBM29F017A-70/-90/-12
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
RY/BY Timing Diagram During Program/Erase Operations
WE
RESET
tRB
tRP
RY/BY
tREADY
RESET Timing Diagram
35
MBM29F017A-70/-90/-12
A20, A19, A18
SGAX
SGAY
A0
A1
A6
VID
5V
A9
tVLHT
OE
tVLHT
V ID
5V
tOESP
tWPP
tVLHT
tVLHT
WE
tCSP
CE
01h
Data
tVCS
VCC
SGAX = Sector Group Address for initial sector
SGAY = Sector Group Address for next sector
AC Waveforms for Sector Group Protection
36
tOE
MBM29F017A-70/-90/-12
VCC
tVIDR
tVCS
tVLHT
VID
5V
5V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
Temporary Sector Group Unprotection
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
DQ2 vs. DQ6
37
MBM29F017A-70/-90/-12
■ FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
×××h/AAh
×××h/55h
×××h/A0h
Program Address/Program Data
Embedded Programming Algorithm
38
MBM29F017A-70/-90/-12
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
×××h/AAh
×××h/AAh
×××h/55h
×××h/55h
×××h/80h
×××h/80h
×××h/AAh
×××h/AAh
×××h/55h
×××h/55h
×××h/10h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
* : To insure the command has been accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
Embedded EraseTM Algorithm
39
MBM29F017A-70/-90/-12
Start
VA = Byte address for programming
= Any of the sector addresses
within the sector being erased
during sector erase operation
= Any of the sector group address
within the sector not being
protected during chip erase
operation.
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
Fail
Pass
Note : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Data Polling Algorithm
40
MBM29F017A-70/-90/-12
Start
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1?
Yes
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
DQ6 = Toggle
?
*1, *2
*1, *2
No
Yes
Fail
Pass
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5
changing to “1”.
Toggle Bit I Algorithm
41
MBM29F017A-70/-90/-12
Start
Set Up Sector Addr.
(A20, A19, A18)
PLSCNT = 1
OE = VID, A9 = VID,
CE = VIL, RESET = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = VIH, CE = OE = VIL
A9 should remain VID
Read from Sector
Addr. (A20, A19, A18)
A1 = 1, A0 = A6 = 0
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01h?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
Sector Group Protection Algorithm
42
MBM29F017A-70/-90/-12
Start
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
*2
*1 : All Protected sector groups unprotected.
*2 : All previously protected sector groups are protected once again.
Temporary Sector Group Unprotection Algorithm
43
MBM29F017A-70/-90/-12
■ ORDERING INFORMATION
Part No.
Package
Access Time
MBM29F017A-70PFTN
MBM29F017A-90PFTN
MBM29F017A-12PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
70
90
120
MBM29F017A-70PFTR
MBM29F017A-90PFTR
MBM29F017A-12PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
70
90
120
MBM29F017A-70PNS
MBM29F017A-90PNS
MBM29F017A-12PNS
40-pin plastic SON
(LCC-40P-M02)
70
90
120
MBM29F017
A
-70
Remarks
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP (1) ) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP (1) ) Reverse Bend
PNS = 40-Pin Small Outline Nonleaded
Package (SON)
SPEED OPTION
See Product Selector Guide
A = Device Revision
DEVICE NUMBER/DESCRIPTION
MBM29F017
16 Mega-bit (2M × 8-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
64K Bytes (32 Sectors)
44
MBM29F017A-70/-90/-12
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin Plastic TSOP (1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
(.472±.008)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting
height)height)
(Mounting
+0.03
0.17 –0.08
+.001
.007 –.003
C
2003 FUJITSU LIMITED F48029S-c-6-7
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
0.22±0.05
(.009±.002)
0.10(.004)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
45
MBM29F017A-70/-90/-12
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin Plastic TSOP (1)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
+0.03
0.17 –0.08
+.001
0.10(.004)
.007 –.003
0.50(.020)
0.22±0.05
(.009±.002)
M
0.10±0.05
(.004±.002)
(Stand off height)
+0.10
"A"
1.10 –0.05
+.004
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
0.10(.004)
2003 FUJITSU LIMITED F48030S-c-6-7
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
(Mounting height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
46
MBM29F017A-70/-90/-12
(Continued)
40-pin Plastic SON
(LCC-40P-M02)
Note 1) Resin residue for * marked dimensions is 0.15 Max on a single side.
Note 2) Die pad geometry may change with the models.
* 10.75±0.10(.423±.004)
0.75(.030)MAX
(TOTAL HEIGHT)
40
0.50(.020)TYP
"A"
21
10.10±0.20
(.398±.008)
10.00±0.10
(.394±.004)
20
1
INDEX
0.05(.002)
M
Details of "B" part
Details of "A" part
*0.625(.025)TYP
"B"
0.10(.004)TYP
0.05(.002)
C
1997 FUJITSU LIMITED C40052S-4C-3
0(0)MIN
(STAND OFF)
0.50(.020)TYP
0.32±0.05
(.013±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
47
MBM29F017A-70/-90/-12
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0306
 FUJITSU LIMITED Printed in Japan
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