AMIC A63L7332E-45 128k x 32 bit synchronous high speed sram with burst counter and pipelined data output Datasheet

A63L7332 Series
128K X 32 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No.
History
Issue Date
Remark
0.0
Initial issue
June 02, 1998
Preliminary
1.0
Change fast access times from 4.5/5 ns to 4.2/4.5/5.0 ns
August 27, 1998
1.1
Change DC and operating characteristics -
December 18, 1998
ICC1 (Max.) : 300mA to 350mA
ISB1 (Max.) : 25mA to 38mA
1.2
Modify 100-pin LQFP symbol y dimensions -
December 31, 1998
Max. in mm :0.08 → 0.1
Max. in inches : 0.003 → 0.004
PRELIMINARY
(December, 1998, Version 1.2)
AMIC Technology, Inc.
A63L7332 Series
128K X 32 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Features
n
n
n
n
n
n Three separate chip enables allow wide range of
options for CE control, address pipelining
n Selectable BURST mode
n SLEEP mode (ZZ pin) provided
n Available in 100-pin LQFP package
Fast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ)
Single +3.3V+10% or +3.3V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
General Description
The A63L7332 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63L7332 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 128K X 32 SRAM core to provide
a wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip
enable ( CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global
Write ( GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
PRELIMINARY
(December, 1998, Version 1.2)
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L7332
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3
controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
1
AMIC Technology, Inc.
A63L7332 Series
PRELIMINARY
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Pin Configuration
NC
1
80
NC
I/O17
2
79
I/O16
I/O18
3
78
I/O15
VCCQ
4
77
VCCQ
GNDQ
5
76
GNDQ
I/O19
6
75
I/O14
I/O20
7
74
I/O13
I/O21
8
73
I/O12
I/O22
9
72
I/O11
GNDQ
10
71
GNDQ
VCCQ
11
70
VCCQ
I/O23
12
69
I/O10
I/O24
13
68
I/O9
NC
14
67
GND
VCC
15
66
NC
NC
16
65
VCC
ZZ
A63L7332
51
NC
(December, 1998, Version 1.2)
50
30
A16
I/O1
NC
49
52
A15
29
48
I/O2
I/O32
A14
53
47
28
A13
VCCQ
I/O31
46
54
A12
27
45
GNDQ
VCCQ
A11
55
44
26
A10
I/O3
GNDQ
43
56
NC
25
42
I/O4
I/O30
NC
57
41
24
VCC
I/O5
I/O29
40
58
GND
23
39
I/O6
I/O28
NC
59
38
22
NC
GNDQ
I/O27
37
60
A0
21
36
VCCQ
GNDQ
A1
61
35
20
A2
I/O7
VCCQ
34
62
A3
19
33
I/O8
I/O26
A4
63
32
18
31
I/O25
A5
17
64
MODE
GND
2
AMIC Technology, Inc.
A63L7332 Series
Block Diagram
ZZ
MODE
LOGIC
MODE
ADV
CLK
CLK
LOGIC
BURST
LOGIC
ADDRESS
COUNTER
CLR
ADSC
ADSP
A0-A16
ADDRESS
REGISTERS
17
8
8
GW
BWE
BW1
BW2
BYTE
WRITE
ENABLE
LOGIC
BW3
8
BYTE2
WRITE
DRIVER
8
128KX8X4
MEMORY
8
8
BW4
BYTE1
WRITE
DRIVER
BYTE3
WRITE
DRIVER
8
BYTE4
WRITE
DRIVER
8
32
OUTPUT
REGISTERS
ARRAY
32
4
DATA-IN
REGISTERS
4
CE
CE2
CE2
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC
OE
OUTPUT
ENABLE
LOGIC
I/O1 - I/O32
PRELIMINARY
(December, 1998, Version 1.2)
3
AMIC Technology, Inc.
A63L7332 Series
Pin Description
Pin No.
Symbol
32 - 37, 44 - 50, 81, 82,
99, 100
A0 - A16
89
CLK
87, 93 - 96
BWE , BW1 - BW4
88
GW
Global Write
86
OE
Output Enable
92, 97, 98
CE2 ,CE2, CE
Chip Enables
83
ADV
84
ADSP
Processor Address Status
85
ADSC
Controller Address Status
31
MODE
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64
ZZ
2, 3, 6 - 9, 12, 13, 18, 19,
22 - 25, 28, 29, 52, 53,
56 - 59, 62, 63, 68, 69,
72 - 75, 78, 79
I/O1- I/O32
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
NC
No Connection
15, 41, 65, 91
VCC
Power Supply
17, 40, 67, 90
GND
Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ
Isolated Output Buffer Ground
PRELIMINARY
(December, 1998, Version 1.2)
Description
Address Inputs
Clock
Byte Write Enables
Burst Address Advance
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
Data Inputs/Outputs
4
AMIC Technology, Inc.
A63L7332 Series
Synchronous Truth Table (See Notes 1 Through 5)
Operation
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
READ Cycle,
Begin Burst
READ Cycle,
Begin Burst
WRITE Cycle,
Begin Burst
READ Cycle,
Begin Burst
READ Cycle,
Begin Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
PRELIMINARY
Address
Used
CE
CE2
CE2
ADSP
ADSC
ADV
WRITE
OE
NONE
H
X
X
X
L
X
X
X
L-H
High-Z
NONE
L
X
L
L
X
X
X
X
L-H
High-Z
NONE
L
H
X
L
X
X
X
X
L-H
High-Z
NONE
L
X
L
H
L
X
X
X
L-H
High-Z
NONE
L
H
X
H
L
X
X
X
L-H
High-Z
External
L
L
H
L
X
X
X
L
L-H
Dout
External
L
L
H
L
X
X
X
H
L-H
High-Z
External
L
L
H
H
L
X
L
X
L-H
Din
External
L
L
H
H
L
X
H
L
L-H
Dout
External
L
L
H
H
L
X
H
H
L-H
High-Z
Next
X
X
X
H
H
L
H
L
L-H
Dout
Next
X
X
X
H
H
L
H
H
L-H
High-Z
Next
H
X
X
X
H
L
H
L
L-H
Dout
Next
H
X
X
X
H
L
H
H
L-H
High-Z
Next
X
X
X
H
H
L
L
X
L-H
Din
Next
H
X
X
X
H
L
L
X
L-H
Din
Current
X
X
X
H
H
H
H
L
L-H
Dout
Current
X
X
X
H
H
H
H
H
L-H
High-Z
Current
H
X
X
X
H
H
H
L
L-H
Dout
Current
H
X
X
X
H
H
H
H
L-H
High-Z
Current
X
X
X
H
H
H
L
X
L-H
Din
Current
H
X
X
X
H
H
L
X
L-H
Din
(December, 1998, Version 1.2)
5
CLK
I/O
Operation
AMIC Technology, Inc.
A63L7332 Series
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx ( BW1 , BW2 , BW3 , or BW4 ) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
PRELIMINARY
(December, 1998, Version 1.2)
6
AMIC Technology, Inc.
A63L7332 Series
Linear Burst Address Table (MODE = LOW)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
Absolute Maximum Ratings*
*Comments
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Recommended DC Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage (Operating Voltage Range)
3.1
3.3
3.6
V
Isolated Input Buffer Supply
3.1
3.3
VCC
V
Supply Voltage to GND
0.0
-
0.0
V
VIH
Input High Voltage
2.0
-
VCC+0.3
V
VIHQ
Input High Voltage (I/O Pins)
2.0
-
VCC+0.3
V
VIL
Input Low Voltage
-0.3
-
0.8
V
VCC
VCCQ
GND
PRELIMINARY
Parameter
(December, 1998, Version 1.2)
7
Note
1, 2
1, 2
AMIC Technology, Inc.
A63L7332 Series
DC Electrical Characteristics
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
ILI
Input Leakage Current
-
±2.0
µA
All inputs VIN = GND to VCC
ILO
Output Leakage Current
-
±2.0
µA
OE = VIH, Vout = GND to VCC
Supply Current
-
350
mA
Device selected; VCC = max.
Iout = 0mA, all inputs = VIH or VIL
Cycle time = tKC min.
ICC1
ISB1
Standby Current
ISB2
-
38
mA
Device deselected; VCC = max.
All inputs are fixed.
All inputs ≥ VCC - 0.2V
or ≤ GND + 0.2V
Cycle time = tKC min.
-
10
mA
ZZ ≥ VCC - 0.2V
VOL
Output Low Voltage
-
0.4
V
IOL = 8 mA
VOH
Output High Voltage
2.4
-
V
IOH = -4 mA
Note
3, 11
11
Capacitance
Symbol
Parameter
Typ.
Max.
Unit
CIN
Input Capacitance
3
4
pF
CI/O
Input/Output Capacitance
4
5
pF
Conditions
TA = 25 C; f = 1MHz
VCC = 3.3V
* These parameters are sampled and not 100% tested.
PRELIMINARY
(December, 1998, Version 1.2)
8
AMIC Technology, Inc.
A63L7332 Series
AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%)
Symbol
-4.2
Parameter
-4.5
-5.0
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
tKC
Clock Cycle Time
7
-
7.5
-
10
-
ns
tKH
Clock High Time
1.9
-
1.9
-
3.2
-
ns
tKL
Clock Low Time
1.9
-
1.9
-
3.2
-
ns
tKQ
Clock to Output Valid
-
4.2
-
4.5
-
5.0
ns
tKQX
Clock to Output Invalid
1.5
-
1.5
-
1.5
-
ns
tKQLZ
Clock to Output in Low-Z
1.5
-
1.5
-
1.5
-
ns
5, 6
tKQHZ
Clock to Output in High-Z
1.5
4.2
1.5
4.5
1.5
5.0
ns
5, 6
tOEQ
OE to Output Valid
-
4.2
-
4.5
-
5.0
ns
8
tOELZ
OE to Output in Low-Z
0
-
0
-
0
-
ns
5, 6
tOEHZ
OE to Output in High-Z
-
4.2
-
4.5
-
5.0
ns
5, 6
Address
2.0
-
2.0
-
2.0
-
ns
7, 9
tADSS
Address Status
( ADSC , ADSP )
2.0
-
2.0
-
2.0
-
ns
7, 9
tADVS
Address Advance ( ADV )
2.0
-
2.0
-
2.0
-
ns
7, 9
tWS
Write Signals
( BW1 , BW2 , BW3 ,
BW4 , BWE , GW )
2.0
-
2.0
-
2.0
-
ns
7, 9
tDS
Data-in
2.0
-
2.0
-
2.0
-
ns
7, 9
tCES
Chip Enable
( CE , CE2, CE2 )
2.0
-
2.0
-
2.0
-
ns
7, 9
Setup Times
tAS
PRELIMINARY
(December, 1998, Version 1.2)
9
AMIC Technology, Inc.
A63L7332 Series
AC Characteristics (continued)
Symbol
-4.2
Parameter
-4.5
-5.0
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Address
0.5
-
0.5
-
0.5
-
ns
7, 9
tADVH
Address Status
( ADSC , ADSP )
0.5
-
0.5
-
0.5
-
ns
7, 9
tAAH
Address Advance ( ADV )
0.5
-
0.5
-
0.5
-
ns
7, 9
tWH
Write Signal
( BW1 , BW2 , BW3 ,
BW4 , BWE , GW )
0.5
-
0.5
-
0.5
-
ns
7, 9
tDH
Data-in
0.5
-
0.5
-
0.5
-
ns
7, 9
tCEH
Chip Enable
( CE , CE2, CE2 )
0.5
-
0.5
-
0.5
-
ns
7, 9
Hold Times
tAH
Notes:
1. All voltages refer to GND.
2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2.
Undershoot: VIH ≥ -0.7V for t ≤ tKC/2.
Power-up: VIH ≤ +3.6 and VCC ≤ 3.1V
for t ≤ 200ms
3. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
PRELIMINARY
(December, 1998, Version 1.2)
10
AMIC Technology, Inc.
A63L7332 Series
Timing Waveforms
tKC
CLK
tKH
tKL
tADSS
tADSH
ADSP
tADSS
tADSH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWS
A3
Burst continued with
new base address
tWH
GW,BWE
BW1-BW4
tCES
Delselected
cycle
tCEH
CE
(NOTE *2)
(NOTE *4)
tADVS
tADVH
ADV
ADV suspends
burst
OE
tOEHZ
(NOTE *3)
tKQLZ
DOUT
High-Z
Q(A1)
tOEQ
tOELZ
Q(A2)
tKQHZ
tKQ
tKQX
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A3)
Burst wraps around
to its initial state
(NOTE *1)
tKQ
Single READ
BURST READ
Read Timing
Notes:
*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to
be driven until after the rising edge of the following clock.
PRELIMINARY
(December, 1998, Version 1.2)
11
AMIC Technology, Inc.
A63L7332 Series
Timing Waveforms (continued)
tKC
CLK
tKH
tKL
tADSS
tADSH
ADSP
tADSS
ADSC extends burst
tADSS
tADSH
tADSH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
tWS
tWH
BWE,BW1-BW4
(NOTE *5)
tWS
tWH
GW
tCES
tCEH
CE
(NOTE *2)
tADVS
tADVH
ADV
(NOTE *4)
OE
(NOTE *3)
tDS
DIN
ADV suspends burst
High-Z
tDH
D(A1)
D(A2)
tOEHZ
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(NOTE *1)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4. ADV must be HIGH to permit a Write to the loaded address.
*5. Byte Write enables are decided by means of a Write truth table.
PRELIMINARY
(December, 1998, Version 1.2)
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AMIC Technology, Inc.
A63L7332 Series
Timing Waveforms (continued)
tKC
CLK
tKH
tKL
tADSS
tADSH
ADSP
ADSC
tAS
ADDRESS
A1
tAH
A2
A3
A4
tWS
tWH
tDS
tDH
A5
A6
GW,BWE,
BW1-BW4
(NOTE *3)
tCES
tCEH
CE
(NOTE *2)
ADV
OE
tKQ
DIN
High-Z
tOELZ
D(A3)
t KQLZ
D(A5)
tOEHZ
D(A6)
tKQ
(NOTE *1)
DOUT
High-Z
Q(A1)
Back-to-Back READs
Q(A2)
Q(A3)
Single WRITE
Pass-through
READ
(NOTE *4)
Q(A4)
Q(A4+1)
Q(A4+2)
BURST READ
Q(A4+3)
Back-to-Back
WRITEs
Read/Write Timing
Notes:
*1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately
following A4.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Byte Write enables are decided by means of a Write truth table.
*4. Pass-through occurs when data is first written, then Read in sequence.
PRELIMINARY
(December, 1998, Version 1.2)
13
AMIC Technology, Inc.
A63L7332 Series
AC Test Conditions
Q
Input Pulse Levels
RL=50Ω
ZO=50Ω
GND to 3V
VT=1.5V
Input Rise and Fall Times
1.5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Figure 1. Output Load Equivalent
+3.3V
320Ω
Output Load
See Figures 1 and 2
Q
350Ω
5pF
Figure 2. Output Load Equivalent
PRELIMINARY
(December, 1998, Version 1.2)
14
AMIC Technology, Inc.
A63L7332 Series
Ordering Information
Part No.
Access Times (ns)
Package
A63L7332E-4.2
4.2
100L LQFP
A63L7332E-4.5
4.5
100L LQFP
A63L7332E-5
5.0
100L LQFP
PRELIMINARY
(December, 1998, Version 1.2)
15
AMIC Technology, Inc.
A63L7332 Series
Package Information
LQFP 100L Outline Dimensions
unit: inches/mm
HE
A2
A1
D
E
80
51
50
100
31
1
L1
L
HD
D
81
y
30
b
e
c
θ
Symbol
Dimensions in inches
Min.
Nom.
Dimensions in mm
Max.
Min.
Nom.
Max.
A1
0.002
-
-
0.05
-
-
A2
0.053
0.055
0.057
1.35
1.40
1.45
b
0.011
0.013
0.015
0.27
0.32
0.37
c
0.005
-
0.008
0.12
-
0.20
HE
0.860
0.866
0.872
21.85
22.00
22.15
E
0.783
0.787
0.791
19.90
20.00
20.10
HD
0.624
0.630
0.636
15.85
16.00
16.15
D
0.547
0.551
0.555
13.90
14.00
14.10
0.030
0.45
e
L
0.026 BSC
0.018
L1
0.024
0.65 BSC
0.039 REF
0.60
0.75
1.00 REF
y
-
-
0.004
-
-
0.1
θ
0°
3.5°
7°
0°
3.5°
7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(December, 1998, Version 1.2)
16
AMIC Technology, Inc.
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