STMicroelectronics L6574 Cfl/tl ballast driver preheat and dimming Datasheet

L6574
CFL/TL BALLAST DRIVER PREHEAT AND DIMMING
■
■
■
■
■
■
■
■
■
■
■
■
■
HIGH VOLTAGE RAIL UP TO 600V
dV/dt IMMUNITY ± 50 V/ns IN FULL
TEMPERATURE RANGE
DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
SWITCHING TIMES 80/40ns RISE/FALL
WITH 1nF LOAD
CMOS SHUT DOWN INPUT
UNDER VOLTAGE LOCK OUT
PREHEAT AND FREQUENCY SHIFTING
TIMING
SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PROTECTION FEATURES
HIGH ACCURACY CURRENT CONTROLLED
OSCILLATOR
INTEGRATED BOOTSTRAP DIODE
CLAMPING ON VS.
SO16, DIP 16 PACKAGES
SO16N
DIP16
ORDERING NUMBERS:
L6574D
L6574
The device is intended to drive two power MOSFETS, in the classical half bridge topology, ensuring all the features needed to drive and properly
control a fluorescent bulb.
A dedicated timing section in the L6574 allows the
user set the necessary parameters for proper preheat and ignition of the lamp.
Also, an OP AMP is available to implement closed
loop control of the lamp current during normal
lamp burning.
DESCRIPTION
In order to ensure voltage ratings in excess of
600V, the L6574 is manufactured with BCD OFF
LINE technology, which makes it well suited for
lamp ballast applications.
An integrated bootstrap section, eliminating the normally required bootstrap diode and the zener clamping on Vs, makes the L6574 well suited for low cost
applications where few additional components are
needed to build a high performance ballast.
BLOCK DIAGRAM
H.V.
VS
OP AMP
OPOUT
VBOOT
+
-
BOOTSTRAP
DRIVER
UV
DETECTION
OPIN-
HVG
HVG
DRIVER
OPIN+
OUT
Imin
VREF
DEAD
TIME
DRIVING
LOGIC
LEVEL
SHIFTER
CBOOT
LOAD
VS
LVG
RING
Ifs
Imax
LVG DRIVER
Ipre
VREF
GND
+
-
RPRE
CONTROL
LOGIC
Vthpre
+
VTHE
EN1
-
+
-
+
VTHE
EN2
-
VCO
Cf
CPRE
September 2003
D97IN493A
1/10
L6574
PIN CONNECTION (top view)
CPRE
1
16
VBOOT
RPRE
2
15
HVG
CF
3
14
OUT
RING
4
13
N.C.
OPOUT
5
12
VS
OPIN-
6
11
LVG
OPIN+
7
10
GND
EN1
8
9
EN2
D97IN492
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to ambient
Max.
DIP16
SO16N
Unit
80
120
°C/W
PIN DESCRIPTION
N°
Pin
Function
1
CPRE
Preheat Timing Capacitor. The capacitor CPRE sets the preheating and the frequency shift time,
according to the relations: tPRE = KPRE · CPRE and tSH = KFS · CPRE (typ. KPRE = 1.5s/µF, KFS =
0.15s/µF). This feature is obtained by charging CPRE with two different currents. During tPRE
this current is independent of the external components, so CPRE is charged up to 3.5V (preheat
timing comparator threshold). During tSH the current depends on RPRE value (i.e. on the difference between fPRE and fIGN). In this way tSH is always set at 0.1tPRE. In steady state the voltage
at pin 1 is 5V.
2
RPRE
Maximum Oscillation Frequency Setting. The resistance connected between this pin and ground
sets the fPRE value, fixing the difference between fPRE and fIGN (fPRE > fIGN). At the end of the
Start-up procedure, the effect current drown from RPRE is over. The voltage at this pin is fixed at
VREF =2V.
3
CF
Oscillator Frequency Setting. The capacitor CF, along with to RPRE and RIGN, sets fPRE and fING.
In normal operation this pin shows a triangular wave.
4
RIGN
Minimum Oscillation Frequency Setting. The resistance connected between this pin and ground
sets the fIGN value. The voltage at this pin is fixed at VREF =2V.
5
OPout
Out of the operational amplifier. To implement a feedback control loop this pin can be connected
to the RIGN pin by means an appropriate circuitry.
6
OPin-
Inverting Input of the operational amplifier.
7
OPin+
Non Inverting Input of the operational amplifier.
8
EN1
2/10
Enable 1. This pin (active high), forces the device in a latched shutdown state (like in the under
voltage conditions). There are two ways to resume normal operation:
– the first is to reduce the supply voltage below the undervoltage threshold and then
increase it again until the valid supply is recognised.
– the second is activating EN2 input.
The enable 1 is especially designed for strong fault (e.g. in case of lamp disconnection).
L6574
PIN DESCRIPTION (continued)
N°
Pin
Function
9
EN2
Enable 2. EN2 input (active high) restarts the start-up procedure (preheating and ignition
sequence). This features is useful if the lamp does not turn-on after the first ignition sequence .
10
GND
Ground.
11
LVG
Low Side Driver Output. This pin must be connected to the low side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
12
VS
Supply Voltage. This pin, connected to the supply filter capacitor, is internally clamped (15.6V
typical).
13
N.C.
Non Connected. This pin set a distance between the pins related to the HV and those related to
the LV side.
14
OUT
High Side Driver Floating Reference. This pin must be connected close to the source of the high
side power MOS or IGBT.
15
HVG
High Side Driver Output. This pin must be connected to the high side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
16
VBOOT
Bootstrapped Supply Voltage. Between this pin and VS must be connected the bootstrap capacitor. A patented integrated circuitry replaces the external bootstrap diode, by means of a high
voltage DMOS, synchronously driven with the low side power MOSFET.
ABSOLUTE MAXIMUM RATINGS
Symbol
IS
Parameter
Supply Current (*)
VLVG
Low Side Output
VOUT
High Side Reference
VHVG
High Side Output
VBOOT
Floating Supply Voltage
dVBOOT/dt
VBOOT pin Slew rate (repetitive)
Value
Unit
25
mA
-0.3 to Vs +0.3
V
-1 to VBOOT -18
V
-1 to VBOOT
V
-1 to 618
V
±50
V/ns
±50
V/ns
Vir
Forced Input Voltage (pins Ring, Rpre)
-0.3 to 5
V
Vic
Forced Input Voltage (pins Cpre, Cf)
-0.3 to 5
V
VEN1, VEN2
Enable Input Voltage
-0.3 to 5
V
IEN1, IEN2
Enable Input Current
±3
mA
dVOUT/dt
OUT pin Slew Rate (repetitive)
Vopc
Sense Op Amp Common Mode Range
-0.3 to 5
V
Vopd
Sense Op Amp Differential Mode Range
±5
V
Vopo
Sense Op Amp Output Voltage (forced)
4.6
V
Tstg, Tj
Storage Temperature
-40 to +150
°C
Tamb
Ambient Temperature
-40 to +125
°C
(*) The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by
a Low Impedance Voltage Source.
Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V (Human Body Model)
3/10
L6574
RECOMMENDED OPERATING CONDITIONS
Symbol
VS
Parameter
Value
Unit
10 to VCL
V
-1 to VBOOT-VCL
V
500
V
Supply Voltage
VOUT (*)
High Side Reference
VBOOT (*)
Floating Supply Voltage
(*) If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580V.
ELECTRICAL CHARACTERISTCS
(VS = 12V; VBOOT-VOUT = 12V; Tamb = 25°C)
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vs Turn On Threshold
9.5
10.2
10.9
V
Vsuvn
Vs Turn Off Threshold
7.3
8
8.7
V
Vsuvh
Supply Voltage Under Voltage
Hysteresys
Supply Voltage
Vsuvp
12
2.2
Vcl
Supply Voltage Clamping
14.6
Isu
Start Up Current
VS < Vsuvn
Iq
Quiescent Current, fout = 60kHz,
no load.
VS > Vsupv
15.6
V
16.6
V
250
µA
2
mA
High voltage Section
Ibootleak
16
BOOT pin leakage current
VBOOT = 580V
5
µA
Ioutleak
14
OUT pin Leakage Current
VOUT = 562V
5
µA
High/Low Side Drivers
Ihvgso
15
High Side Driver Source Current
VHVG-VOUT = 0
170
250
mA
Ihvgsi
15
High Side Driver Sink Current
VHVG-VBOOT = 0
300
450
mA
Ihvgso
11
Low Side Drive Source Current
VLVG-GND = 0
170
250
mA
Ilvgsi
11
Low Side Drive Source Current
VLVG-VS = 0
300
450
mA
trise
15,
11
Low/High Side Output Rise Time
Cload = 1nF
80
120
ns
Low/High Side Output Fall Time
Cload = 1nF
50
80
ns
48
50
52
%
tfall
Oscillator
DC
14
Output Duty Cycle
fing
14
Minimum Output Oscillation
Frequency
CF = 470pF;
Ring = 50kΩ
58.2
60
61.8
kHz
fpre
14
Maximum Output Oscillation
Frequency
CF = 470pF;
Ring = 50kΩ;
Rpre = 47kΩ
114
120
126
kHz
Vref
2,4
Voltage to current converters
threshold
1.9
2
2.1
V
IVref
2,4
Reference Current
120
µA
td
14
Dead Time between Low and
High Side Conduction
1.7
µs
4/10
0
0.8
1.25
L6574
ELECTRICAL CHARACTERISTCS (continued)
(VS = 12V; VBOOT-VOUT = 12V; Tamb = 25°C)
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Timing Section
kpre
1
kfs
Vthpre
Pre Heat Timing constant
Cpre = 330nF
1.15
1.5
1.85
s/µF
Frequency Shift Timing Constant
Cpre = 330nF
0.115
0.15
0.185
s/µF
3.3
3.5
3.7
V
0.1
µA
Pre Heat Timing Comparator
Threshold
Sense OP AMP
lib
6,7
Vio
Rout
5
Input Bias current
Input Offset Voltage
-10
10
mV
Ouput Resistance
200
300
Ω
Iout +
Sink Output Current
Vout = 0.2V
0.5
mA
Iout -
Source Output Current
Vout = 4.5V
0.5
mA
Vic
6,7
Common Mode Input Range
-0.2
3
V
GBW
Sense Op Amp Gain Band Width
Product
1
MHz
Gdc
DC Open Loop Gain
80
dB
Comparators
Enabling Comparators Threshold
0.56
Vhye
Enabling Comparators Hysteresis
20
tpulse
Minimum Pulse lenght
Vthe
8,9
0.6
200
0.64
V
100
mV
ns
High/Low Side Driving Section:
High and low side driving sections provide the proper drive to the external power MOSFET. A high sink/
source driving current (450/250 mA typical) ensures fast switching times when a size 4 external power
MOSFET needs to be driven.
Bootstrap Section:
A patented integrated bootstrap section replaces an external bootstrap diode. This section together with
a bootstrap capacitor provides the bootstrap voltage to drive the high side power MOSFET. This function
is achieved using a high voltage DMOS driver which is driven synchronously with the low side external
power MOSFET.
For a safe operation, current flow into the Vboot pin is inhibited, even though ZVS operation may not be
ensured.
Timing Section:
To set the proper preheat time (tpre=kpre*Cpre) for the bulb, a capacitor is connected to the Cpre pin
which is charged with a fixed current. During tpre, the output is switching at fpre (see Oscillator Section).
When the tpre expires, the Cpre capacitor is discharged and then recharged with a different current. This
sets a second time interval tsh (0.1 times the selected preheat time tpre) during which frequency shifting
from fpre to fing is performed to ensure lamp ignition.
5/10
L6574
Oscillator Section:
A voltage controlled oscillator, with the selected frequencies fpre and fing, drives the output half bridge.
Independently selected, fpre is effective during tpre and fing is effective during normal lamp burning. When
working open loop, fpre and fing are the highest and lowest allowed oscillation frequencies.
Closed loop control of the lamp current under normal operation can be achieved with the L6574. This is
accomplished by automatic adjustment of the oscillator frequency. The OP AMP output is fed through a
resistor diode network to the Ring pin. See AN 993.
OP AMP Section:
The integrated OP AMP offers low output impedance, wide bandwidth, high input impedance and wide
common mode range. It can be readily used to implement closed loop control (see Oscillator Section) of
the lamp current.
EN1, EN2 Comparators:
Two CMOS comparators, with thresholds set at 0.6 V (typical) are available to implement protection methods (such as overvoltage, lamp removal, etc.). Short pulses (>200nsec) at the comparator inputs are recognized.
The EN1 input (active high) forces the L6574 in the shut down state (e.g. LVG low, HVG low, oscillator
stopped) in the event of an undervoltage condition. Normal operating condition is resumed after a poweroff power-on sequence or when EN2 input is high.
The EN2 input (active high) also restarts a preheat sequence (see timing diagrams).
TIMING DIAGRAMS
VSUVP
VCC
LVG
HVG
EN1
D97IN490
VCC
fOUT
VSUVP
fPRE
fING
EN2
D97IN491B
6/10
tPRE
tSH
tPRE
tSH
L6574
Figure 4. ∆f vs. RPRE, with R ING = 100kΩ
Figure 1. fING vs. RING.
fING
(KHz)
D98IN867
∆f
(KHz)
D98IN870
RING=100KΩ
100
100
80
80
60
60
40
40
20
20
20
40
60
80
Figure 2. ∆f vs. RPRE, with R ING = 33kΩ
∆f
(KHz)
20
100 RING(KΩ)
D98IN868
40
60
80
100 RPRE(KHΩ)
Figure 5. fING vs. temperature.
fING
(KHz)
D98IN871
RING=33KΩ
80
70
60
60
40
50
20
20
40
60
80
100 RPRE(KΩ)
Figure 3. ∆f vs. RPRE, with R ING = 50kΩ
∆f
(KHz)
D98IN869
40
-50
0
50
100
T(˚C)
Figure 6. fPRE vs. temperature.
fPRE
(KHz)
D98IN872
RING=50KΩ
100
130
80
120
60
110
40
100
20
20
40
60
80
100 RPRE(KΩ)
-50
0
50
100
T(˚C)
7/10
L6574
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.009
1.6
0.063
b
0.35
0.46
0.014
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
c1
45˚ (typ.)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F (1)
3.8
4
0.150
0.157
G
4.6
5.3
0.181
0.209
L
0.4
1.27
0.016
0.050
S
Weight: 0.20gr
0.020
D (1)
M
OUTLINE AND
MECHANICAL DATA
0.62
0.024
SO16 Narrow
8˚(max.)
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
0016020
8/10
L6574
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP16
Z
1.27
0.050
9/10
L6574
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
10/10
Similar pages