Renesas M61533FP 4ch electronic volume with agc Datasheet

M61533FP
4ch Electronic Volume with AGC
REJ03F0059-0100Z
Rev.1.0
Sep.19.2003
Features
Function
Feature
Electric Volume
• 0 to -87dB, -∞/1dBstep
• 4ch SL/SR/C/SW independent Electric Volume
• Controlled by trim volume data + master volume data.
AGC
Vc=1.8Vrms<SWch>
LPF
Output Gain Control
Can be set externally <SWch>
0, +6, +9, +12dB 4step <SWch>
MUC I/F
Controlled by serial data from microcomputer
Application
Mini Stereo etc.
Recommended Operating Condition
Supply Voltage Range
VCC= 8 to 10V Typ:VCC=9V
System Block Diagram
SLIN
SLch volume
SRIN
SRch volume
CIN
SWIN
SLOUT
SROUT
Cch volume
SWch volume
COUT
AGC
SW-LPF
0,+6, +9,+12dB
Rev.1.0, Sep.19.2003, page 1 of 12
SWOUT
M61533FP
Block Diagram and Pin Configuration (Top view)
SLIN
1
20
SWLPF2
19
N.C.
18
SWOUT
17
REFIN
16
REFOUT
15
SLOUT
14
SROUT
13
COUT
12
SWLPF1
11
AGC
LPF amp
N.C.
2
SLch Volume
N.C.
3
SRIN
4
5
0 to -87dB,-∞
Cch Volume
40k
SWIN
VREF amp
SRch Volume
40k
CIN
0 to -87dB,-∞
40k
0 to -87dB,-∞
6
SWch Volume
0 to -87dB,-∞
VCC
7
DATA
8
40k
MCU I/F
CLOCK
9
AGC
SW Output
Gain Control
GND
10
Rev.1.0, Sep.19.2003, page 2 of 12
0,+6,+9,+12dB
M61533FP
Pin Description
Pin No.
Name
Function
1
SLIN
SLch volume input pin
2
N.C.
N.C.
3
4
N.C.
SRIN
N.C.
SRch volume input pin
5
6
CIN
SWIN
Cch volume input pin
SWch volume input pin
7
8
VCC
DATA
Power supply (Typ:9V)
Input pin of Control data
9
10
CLOCK
GND
Input pin of Control clock
Ground
11
12
AGC
SWLPF1
Attack/Recovery time control pin (by capacitor)
SWch LPF (connected with resistance and capacitor)
13
14
COUT
SROUT
Cch output pin
SRch output pin
15
16
SLOUT
REFOUT
SLch output pin
Vref output pin
17
18
REFIN
SWOUT
Vref input pin
SWch output pin
19
20
N.C.
SWLPF2
N.C.
SWch LPF (connected with resistance and capacitor)
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Power Supply
Vcc
10.5
V
Power dissipation
Thermal derating
Pd
Kθ
648
6.48
mW
mW/°C
Operating temperature
Storage temperature
Topr
Tstg
−20 to 75
−40 to 125
°C
°C
Rev.1.0, Sep.19.2003, page 3 of 12
Condition
Ta ≤ 25°C
Ta > 25°C
M61533FP
THERMAL DERATINGS
(MAXIMUM RATING)
POWER DISSIPATION pd (W)
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
0
40
75
80
120
150
AMBIENT TEMPERATURE Ta ( C)
Recommended Conditions
(Ta=25°C, Unless otherwise noted)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply
Logic “H” level input voltage
Vcc
VIH
8
2.2
9

10
5.5
V
V
Logic “L” level input voltage
VIL
0

0.6
V
Rev.1.0, Sep.19.2003, page 4 of 12
Conditions
VCC=9V
GND reference
VCC=9V
GND reference
M61533FP
Relationship Between Data and Clock
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
CLOCK
D0
D2
D1
D13
D3
D14
D15
DATA
Data signal is read at the rising edge of CLOCK.
Make "H" at the timing which
DATA of D0-D15 make latch.
Clock and Data Timings
(D0
D15)
LATCH
t cr
CLOCK
tSLD
tHLD tSHD tHHD
75%
25%
DATA
tr
tf
tWHC
Rev.1.0, Sep.19.2003, page 5 of 12
tWLC
tSLD
tHLD
M61533FP
Timing Definition of Digital Block
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLOCK cycle time
tcr
4


µs
CLOCK pulse width(“H” level)
CLOCK pulse width (“L” level)
tWHC
tWLC
1.6
1.6




Rising time of clock and data
Falling time of clock and data
tr
tf




0.4
0.4
DATA setup time (Rising time of clock)
DATA setup time (Falling time of clock)
tSHD
tSLD
0.8
0.8




DATA hold time(“H” level)
DATA hold time(“L” level)
tHHD
tHLD
0.8
0.8




Data Control Specification
Four types of input format can be selected by changing the D14/D15 slot setting status.
(Initialize all data of the 4 formats when power supply(VCC) turn on.)
Note : No guarantee except for these code.
(1)
D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 D15
2
2
SLch Trim volume
(2)
Cch Trim volume
(4)
0
0
0
0
0
1
0
0
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14 D15
2
(3)
SRch Trim volume
2
1
SWch Trim volume
SWch
Output gain
control
1
0
0
0
0
1
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15
3
3
SLch Master volume
SRch Master volume
0
0
0
0
1
0
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14 D15
3
3
Cch Master volume
SWch Master volume
Rev.1.0, Sep.19.2003, page 6 of 12
0
0
0
0
1
1
M61533FP
Setting Code
It’s initial setting when VCC turn on.
1 SWch Output gain control
0dB
+6dB
+9dB
+12dB
D10b
0
0
0
1
1
1
0
1
3 SL/SR/C/SWch Master volume
2 SL/SR/C/SWch Trim volume
SLch
SRch
ATT
Cch
SWch
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
D9b
D0a D1a D2a D3a
D4a D5a D6a D7a
D0b D1b D2b D3b
D4b D5b D6b D7b
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note1: Volume ATT controlled by trim volume data +
master volume data.
Note2: When trim volume data + master volume data is
under –87dB setting , volume ATT keep –87dB.
ex) When trim volume data:-15dB / master volume data
-76dB setting , volume ATT keep –87dB.
Rev.1.0, Sep.19.2003, page 7 of 12
ATT
SLch
SRch
Cch
SWch
0dB
-2dB
-4dB
-6dB
-8dB
-10dB
-12dB
-14dB
-16dB
-18dB
-20dB
-22dB
-24dB
-26dB
-28dB
-30dB
-32dB
-34dB
-36dB
-38dB
-40dB
-42dB
-44dB
-48dB
-52dB
-56dB
-60dB
-64dB
-68dB
-72dB
-76dB
-∞ dB
D0c D1c D2c D3c D4c
D5c D6c D7c D8c D9c
D0d D1d D2d D3d D4d
D5d D6d D7d D8d D9d
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
M61533FP
Electrical characteristics
Unless otherwise noted, Ta=25°C, Vcc=9V, f=1kHz, Trim/Master Volume=0dB, Output Gain Control=0dB, SWch
LPF fc=300Hz
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test conditions
Power circuit current
Input/output
IACC

15
30
mA
when no signal is provided
Maximum input voltage
VIM


2.0*
Vrms
Maximum output voltage
VOM1
1.4
1.8

Vrms
(1,4,5,6)PIN input,(13,14,15,18)PIN output,
RL=10kΩ, THD=1%
6PIN input, 18PIN output, RL=10kΩ,
THD=5% , f=100Hz
VOM2
1.6
2.0

Vrms
Pass gain
GV
−2
0
+2
dB
Output noise voltage
Vno1

1.3
4.0
µVrms

1.3
4.0
µVrms

8.0
16
µVrms

8.0
16
µVrms
THD1

0.005
0.1
%
THD2

0.05
0.2
%
THD3

5

%
Maximum attenuation
ATT

−92
−87
dB
Maximum gain
GVM
+10
+12
+14
dB
Cross talk between
channels
CT

−70
−55
dB
AGC
Attack time
TAGCAT

40

ms
6PIN input, 12PIN output, RL=10kΩ, Output
Gain Control =+12dB
Recovery time
TAGCRE

850

ms
6PIN input, 12PIN output, RL=10kΩ, Output
Gain Control =+12dB
Vno2
Distortion
* Note : The signal can not be inputted to more than 2Vrms. Keep this limit.
Rev.1.0, Sep.19.2003, page 8 of 12
(1,4,5)PIN input , (13,14,15)output,
RL=10kΩ, THD=5%
(1,4,5,6)PIN input, (13,14,15,18) output,
Vi=0.5Vrms, FLAT
JIS-A, when no signal is
provided, (1,4,5)PIN
Rg=0 Ω, (13,14,15)PIN
output
SL/SR/Cch
volume =0dB
SL/SR/Cch
volume =-∞dB
JIS-A, when no signal is
provided, 6PIN Rg=0 Ω,
18PIN output,
SWch volume
=0dB
SWch volume =∞dB
(1,4,5)PIN input, (13,14,15)output, BW:400
30kHz, Vo=0.5Vrms, RL=10kΩ
6PIN input,12PIN output, 30kHz L.P.F,
f=100Hz, Output Gain Control =0dB,
Vi=0.5Vrms(AGC:off), RL=10kΩ
6PIN input, 12PIN output, 30kHz L.P.F,
f=100Hz, Output Gain Control =+12dB,
Vi=0.7Vrms(AGC:on), RL=10kΩ
Vo=1Vrms, (12,13,14,15) PIN output, JIS-A,
VOL=-∞
6PIN input, 12PIN output, f=100Hz,
Vi=0.1Vrms, FLAT, Output Gain Control
=+12dB
(1,4,5,6)PIN input, (12,13,14,15)PIN output,
Vi=0.5Vrms, JIS-A, RL=47kΩ, Rg=0kΩ
M61533FP
LPF
Equivalent circuit of LPF
C1
Vin
F(s) =
ω0
=
R2
R1
Vout
=
Vin
C2
1
K
R1R2C1C2
2
S + R11C1 + R21C1 +( 1-K ) R21C2
1
R1R2C1C2
Q=
Vout
+K
S+
1
R1R2C1C2
1
R2C2
R1C2
R1C1
R1 C1 + R2 C1 + ( 1-K ) R2 C2
Frequency characteristics (SWch LPF)
R1=2.2kΩ, R2=4.7kΩ, C1=0.22µF, C2= 0.1µF, K=1
.
.
Q =. 0.68, fc =. 300Hz
*This frequency response is a simulation result.
Rev.1.0, Sep.19.2003, page 9 of 12
M61533FP
AGC
•Note : Less than 2Vrms
SWch Output Gain Control
+26dB(total:0dB) to
+38dB (total:+12dB)
SWIN
Max:2Vrms
SWch
volume
SWOUT
-26dB
AGC out
AGC in
AGC comp
Attack time / Recovery time
EX) C = 1.0 µF
Attack time 40 mS
Recovery time 850 mS
Attack / Recovery time is
controlled by this capacitor.
1.0µ
AGC
AGC characteristics
Output Gain : +6dB
Output Gain : 0dB
+5.1dBV
(1.8Vrms: TYP)
+10
0
10dB
-10
+5.1dBV
(1.8Vrms)
AGCout (dBV)
AGCout (dBV)
+10
+5.1dBV
(1.8Vrms: TYP)
0
10dB
+ 9.1dBV
(2.85Vrms)
-10
-0.9dBV
(0.90Vrms)
+6dBV
(2Vrms)
-20
-20
-20
-10
0
-20
+10
-10
Output Gain : +9dB
+10
Output Gain : +12dB
+5.1dBV
(1.8Vrms: TYP)
0
+10
AGCout (dBV)
+10
0
AGCin (dBV)
AGCin (dBV)
AGCout (dBV)
+6dBV
(2Vrms)
10dB
-10
-4dBV
(0.63Vrms)
0
10dB
+3.1dBV
(1.43Vrms)
-10
-6.9dBV
(0.45Vrms)
+6dBV
(2Vrms)
-20
+5.1dBV
(1.8Vrms: TYP)
+6dBV
(2Vrms)
-20
-20
-10
0
AGCin (dBV)
Rev.1.0, Sep.19.2003, page 10 of 12
+10
-20
-10
0
AGCin (dBV)
+10
M61533FP
Application Example
* Note : The signal can not be inputted to more than 2Vrms.
0.1µ
10µ
SLch IN
1
Max:2Vrms
20
4.7k
LPF amp
N.C.
2
N.C.
19
SLch Volume
N.C.
2.2k
SRch OUT
0.22µ
0 to -87dB,-∞
3
40k
10µ
SRch IN
10µ
VREF amp
SRch Volume
4
Max:2Vrms
18
17
0 to -87dB,-∞
100µ
40k
10µ
Cch IN
5
16
Cch Volume
Max:2Vrms
40k
100µ
0 to -87dB,-∞
10µ
SWch IN
6
10µ
SLch OUT
10µ
SRch OUT
10µ
Cch OUT
15
Max:2Vrms
SWch Volume
0 to -87dB,-∞
VCC:9V
7
40k
14
8
MCU
13
MCU I/F
9
AGC
12
SW Output
Gain Control
0,+6,+9,+12dB
10
11
1µ
Rev.1.0, Sep.19.2003, page 11 of 12
M61533FP
Package Dimensions
Rev.1.0, Sep.19.2003, page 12 of 12
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
Similar pages