ONSEMI M74VHC1GT66DFT1G

MC74VHC1GT66,
NLVHC1GT66
SPST (NO) Normally Open
Analog Switch
Features
•
•
•
•
•
•
•
High Speed: tPD = 20 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
Diode Protection Provided on Inputs and Outputs
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MARKING DIAGRAMS
5
SC−88A
DF SUFFIX
CASE 419A
5
1
M
The MC74VHC1GT66, NLVHC1GT66 is a Single Pole Single
Throw (SPST) analog switch. It achieves high speed propagation
delays and low ON resistances while maintaining low power
dissipation. This bilateral switch controls analog and digital voltages
that may vary across the full power−supply range (from VCC to GND).
The MC74VHC1GT66, NLVHC1GT66 is compatible in function to
a single gate of the High Speed CMOS MC74VHCT4066 and the
metal−gate CMOS MC14066. The device has been designed so that
the ON resistances (RON) are much lower and more linear over input
voltage than RON of the metal−gate CMOS or High Speed CMOS
analog switches.
The newer NLVHC1GT66 offers the same functionality in a
1.2x1.0x0.55 mm UDFN6 package.
The ON/OFF Control input is compatible with TTL−type input
thresholds allowing the device to be used as a logic−level translator
from 3 V CMOS logic to 5 V CMOS logic or from 1.8 V CMOS logic
to 3 V CMOS logic while operating at the high−voltage power supply.
The input protection circuitry on this device allows overvoltage
tolerance on the input, which provides protection when voltages of up
to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC1GT66, NLVHC1GT66 to be used to interface 5 V circuits
to 3 V circuits.
VE M G
G
1
5
TSOP−5
DT SUFFIX
CASE 483
5
1
VE M G
G
1
UDFN6
MU SUFFIX
CASE 517AA
1
WW M
G
VE, W = Device Code
M
= Date Code*
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
Improved Linearity and Lower ON Resistance over Input Voltage
On/Off Control Input Has OVT
PIN ASSIGNMENT
Chip Complexity: FETs = 11; Equivalent Gates = 3
Pb−Free Packages are Available
1
IN/OUT XA
2
OUT/IN YA
3
GND
4
ON/OFF CONTROL
5
VCC
FUNCTION TABLE
On/Off Control Input
State of Analog Switch
L
H
Off
On
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 13
1
Publication Order Number:
MC74VHC1GT66/D
MC74VHC1GT66, NLVHC1GT66
IN/OUT XA
1
OUT/IN YA
2
GND
3
5
4
VCC
IN/OUT XA
1
6
VCC
OUT/IN YA
2
5
NC
GND
3
4
ON/OFF
CONTROL
ON/OFF
CONTROL
(SC−88A, TSOP−5)
(UDFN6)
Figure 1. Pinout Diagrams
ON/OFF CONTROL
X1
1
1
U
U
IN/OUT XA
OUT/IN YA
Figure 2. Logic Symbol
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VIS
Analog Output Voltage
−0.5 to 7.0
V
IIK
Input Diode Current
−20
mA
ICC
DC Supply Current, VCC and GND
+25
mA
*65 to )150
°C
260
°C
)150
°C
SC70−5 (Note 1)
SOT23−5
350
230
°C/W
SC70−5
SOT23−5
150
200
mW
TSTG
Characteristics
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85°C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
ESD Withstand Voltage
Latchup Performance
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
Above VCC and Below GND at 125°C (Note 5)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHC1GT66, NLVHC1GT66
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
Digital Input Voltage
GND
5.5
V
VIS
Analog Input Voltage
GND
VCC
V
TA
Operating Temperature Range
−55
+125
°C
0
0
100
20
ns/V
tr , tf
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Input Rise and Fall Time
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ =100° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ =110 ° C
Time, Years
TJ =120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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3
MC74VHC1GT66, NLVHC1GT66
DC ELECTRICAL CHARACTERISTICS
Symbol
VIH
Parameter
Test Conditions
Minimum High−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
Maximum Low−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
IIN
Maximum Input
Leakage Current
ON/OFF Control Input
ICC
VIL
TA ≤ 85°C
TA = 25°C
VCC
(V)
Min
3.0
4.5
5.5
1.2
2.0
2.0
Max
Min
Max
−55°C ≤ TA ≤ 125°C
Min
Max
Unit
V
1.2
2.0
2.0
1.2
2.0
2.0
V
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
VIN = VCC or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
Maximum Quiescent
Supply Current
VIN = VCC or GND
VIO = 0 V
5.5
1.0
20
40
mA
ICCT
Quiescent
Supply Current
ON/OFF Control at
3.4 V
5.5
1.35
1.5
1.65
mA
RON
Maximum ”ON”
Resistance
VIN = VIH
VIS = VCC or GND
|IIS| ≤ 10 mA (Figure 4)
3.0
4.5
5.5
60
45
40
70
50
45
100
60
55
W
IOFF
Maximum Off−Channel
Leakage Current
VIN = VIL
VIS = VCC or GND
Switch Off (Figure 5)
5.5
0.1
0.5
1.0
mA
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AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation
Delay, Input X to Y
Test Conditions
YA = Open
(Figures 7, 14)
tPLZ,
tPHZ
tPZL,
tPZH
CIN
VCC
(V)
Typ
Max
Max
Unit
1
0.6
0.6
0.6
5
2
1
1
6
3
1
1
7
4
2
1
ns
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
3
10
10
10
pF
4
4
10
10
10
10
10
10
RL = 1000 W
Maximum Propagation
Delay, ON/OFF Control
to Analog Output
RL = 1000 W
Maximum Input
Capacitance
ON/OFF Control Input
0.0
Control Input = GND
Analog I/O
Feedthrough
5.0
(Figures 8, 15)
Min
Min
Max
−55°C ≤ TA ≤ 125°C
2.0
3.0
4.5
5.5
Maximum Propagation
Delay, ON/OFF Control
to Analog Output
(Figures 8, 15)
TA ≤ 85°C
TA = 25°C
Min
Typical @ 25°C, VCC = 5.0 V
CPD
18
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHC1GT66, NLVHC1GT66
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ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
Test Conditions
VCC
Limit 25°C
Unit
BW
Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 10)
fin = 1 MHz Sine Wave
Adjust fin voltage to obtain 0 dBm at VOS
Increase fin = frequency until dB meter reads −3 dB
RL = 50 W
3.0
4.5
5.5
150
175
180
MHz
ISOoff
Off−Channel Feedthrough Isolation
(Figure 11)
fin = Sine Wave
Adjust fin voltage to obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W
3.0
4.5
5.5
−80
−80
−80
dB
Feedthrough Noise Control to
Switch
(Figure 12)
Vin ≤ 1 MHz Square Wave (tr = tf = 2ns)
3.0
4.5
5.5
45
60
130
mVPP
Total Harmonic Distortion
(Figure 13)
fin = 1 kHz, RL = 10 kW
THD = THDMeasured − THDSource
VIS = 3.0 VPP sine wave
VIS = 5.0 VPP sine wave
NOISEfeed
THD
RL = 600 W
%
3.3
5.5
0.30
0.15
PLOTTER
POWER
SUPPLY
−
COMPUTER
DC PARAMETER
ANALYZER
+
VCC
1
VCC
VCC
5
1
2
5
VIH
2
3
4
VCC
VIL
A
3
Figure 4. On Resistance Test Set−Up
VCC
4
Figure 5. Maximum Off−Channel Leakage Current
Test Set−Up
VCC
A
N/C
1
5
2
3
VCC
1
TEST
POINT
VIH
4
2
3
Figure 6. Maximum On−Channel Leakage Current
Test Set−Up
5
VIH
4
Figure 7. Propagation Delay Test Set−Up
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5
MC74VHC1GT66, NLVHC1GT66
Switch to Position 2 when testing tPLZ and tPZL
Switch to Position 1 when testing tPHZ and tPZH
TEST POINT
VCC
VCC
VCC
1
A
1
5
RL
2
2
1
VCC
CL *
3
N/C
1
N/C
2
4
5
3
2
4
*Includes all probe and jig capacitance.
Figure 8. Propagation Delay Output Enable/Disable
Test Set−Up
Figure 9. Power Dissipation Capacitance
Test Set−Up
VIS
VOS
VCC
0.1 mF
fin
1
VOS
VCC
0.1 mF
fin
5
1
2
dB
Meter
2
3
dB
Meter
4
RL
3
*Includes all probe and jig capacitance.
Figure 11. Off−Channel Feedthrough Isolation
Test Set−Up
To Distortion
Meter
(VCC)/2
(VCC)/2
V
VCC
0.1 mF
5
VOS
IS
VIS
VCC
RL
1
4
*Includes all probe and jig capacitance.
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
RL
5
IN
RL
v 1 MHz
VOS
2
t r + t + 2 ns
3
VIH
f
4
fin
1
5
2
3
VIH
4
GND
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
Figure 13. Total Harmonic Distortion Test Set−Up
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6
MC74VHC1GT66, NLVHC1GT66
XA
VCC
1.5 V
1.5 V
tPLH
tPHL
VOH
YA
50% VCC
VOL
Figure 14. Propagation Delay, Analog In to Analog Out Waveforms
tr
tf
VIH
90%
Control
10%
1.5 V
tPZL
tPLZ
High
Impedance
50% VCC
10%
Analog Out
90%
50% VCC
tPHZ
tPZH
VOL
VOH
High
Impedance
Figure 15. Propagation Delay, ON/OFF Control
ORDERING INFORMATION
Device
Package
MC74VHC1GT66DFT1
SC−88A
M74VHC1GT66DFT1G
SC−88A
(Pb−Free)
MC74VHC1GT66DFT2
SC−88A
M74VHC1GT66DFT2G
SC−88A
(Pb−Free)
MC74VHC1GT66DTT1
TSOP−5
M74VHC1GT66DTT1G
TSOP−5
(Pb−Free)
NLVHC1GT66MUR2G
UDFN6
(Pb−Free)
Shipping†
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC74VHC1GT66, NLVHC1GT66
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
mm Ǔ
ǒinches
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1GT66, NLVHC1GT66
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE G
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
D 5X
0.20 C A B
5
1
4
2
3
M
B
S
K
L
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC74VHC1GT66, NLVHC1GT66
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA−01
ISSUE A
PIN ONE
REFERENCE
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
D
ÉÉÉ
ÉÉÉ
E
DIM
A
A1
A3
b
D
E
e
L
L2
TOP VIEW
2X
0.10 C
(A3)
0.10 C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.00 BSC
1.20 BSC
0.40 BSC
0.30
0.40
0.40
0.50
A
10X
0.08 C
SEATING
PLANE
SIDE VIEW
C
A1
5X
1
L
MOUNTING FOOTPRINT*
3
6X
6X
6X
0.42
L2
0.22
b
0.10 C A B
0.05 C
6
4
e
NOTE 3
BOTTOM VIEW
0.40
PITCH
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT66/D