IDT IDT72V845L10PF 3.3 volt cmos dual syncfifo dual 256 x 18, dual 512 x 18, dual 1,024 x 18, dual 2,048 x 18 Datasheet

IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
3.3 VOLT CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
FEATURES:
•
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•
•
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The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
Ideal for the following applications:
– Network switching
– Two level prioritization of parallel data
– Bidirectional data transfer
– Bus-matching between 18-bit and 36-bit data paths
– Width expansion to 36-bit per package
– Depth expansion to 8,192 words per package
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full Flags
•
•
•
•
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•
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 128-pin thin quad flatpack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked) First-in, First-out (FIFO) memories designed to run
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845 device is functionally equivalent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
package with all associated control, data, and flag lines assigned to
independent pins. These devices are very high-speed, low-power First-In,
First-Out (FIFO) memories with clocked read and write controls. These
FUNCTIONAL BLOCK DIAGRAM
HFA/(WXOA)
PAEA
EFA/
ORA
WCLKB
WENB
PAFA
FFA/IRA
WCLKA
WENA
DA0-DA17
INPUT
REGISTER
WRITE
CONTROL
LOGIC
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
WRITE
POINTER
FLA
WXIA
(HFA)/WXOA
RXIA
RXOA
RSA
LDA
OFFSET
REGISTER
INPUT
REGISTER
FLAG
LOGIC
WRITE
CONTROL
LOGIC
READ
POINTER
WRITE
POINTER
READ
CONTROL
LOGIC
EXPANSION
LOGIC
DB0-DB17
EXPANSION
LOGIC
OUTPUT
REGISTER
RESET
LOGIC
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
LDB
OFFSET
REGISTER
FLAG
LOGIC
FFB/IRB
PAFB
EFB/ORB
PAEB
HFB/(WXOB)
READ
POINTER
READ
CONTROL
LOGIC
OUTPUT
REGISTER
RESET
LOGIC
OEA QA0-QA17
RSB
RXOB
RXIB
RCLKA
RENA
OEB
QB0-QB17
RCLKB
RENB
(HFB)/WXOB
WXIB
FLB
4295 drw 01
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2001
1
 2001 Integrated Device Technology, Inc.
DSC-4295/1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
DESCRIPTION (CONTINUED)
by asserting the Load pin (LD). A Half-Full flag (HF) is available for each
FIFO that is implemented as a single device.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through (FWFT) mode. The XI and XO pins are used to
expand the FIFOs. In depth expansion configuration, FL is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
IDT’s high-speed submicron CMOS technology.
FIFOs are applicable for a wide variety of data buffering needs, such as
optical disk controllers, Local Area Networks (LANs), and interprocessor
communication.
Each of the two FIFOs contained in these devices has an 18-bit input
and output port. Each input port is controlled by a free-running clock
(WCLK), and an input enable pin (WEN). Data is read into the synchronous
FIFO on every clock when WEN is asserted. The output port of each FIFO
bank is controlled by another clock pin (RCLK) and another enable pin
(REN). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port
of each FIFO for three-state control of the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VCC
PAFA
RXIA
FFA
WXOA/HFA
RXOA
QA0
QA1
GND
QA2
QA3
VCC
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PAEB
FLB
WCLKB
WENB
WXIB
VCC
PAFB
RXIB
FFB
WXOB/HFB
RXOB
QB0
QB1
GND
QB2
QB3
VCC
QB4
GND
QB5
QB6
QB7
QB8
GND
QB9
QB10
VCC
QB11
QB12
GND
QB13
QB14
VCC
QB15
GND
QB16
QB17
INDEX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
WXIA
WENA
WCLKA
FLA
PAEA
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
GND
RCLKA
RENA
PIN CONFIGURATIONS
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2
LDA
OEA
RSA
VCC
GND
EFA
QA17
QA16
GND
QA15
VCC
QA14
QA13
GND
QA12
QA11
VCC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
OEB
RSB
VCC
GND
EFB
4295 drw 02
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
I/O
Description
DA0–DA17
Data Inputs
DB0-DB17
I
Data inputs for an 18-bit bus.
RSA
Reset
RSB
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLKA
WCLKB
Write Clock
I
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WENA
WENB
Write Enable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
RCLKA
Read Clock
RCLKB
I
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not
empty.
RENA
RENB
Read Enable
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN
is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is low.
OEA
Output Enable
OEB
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
LDA
LDB
Load
I
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
FLA
FLB
First Load
I
In the single device or width expansion configuration, FL together with WXI and RXI etermine if the mode is IDT
Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are synchronous
or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration, FL is grounded on the first
device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXIA
WXIB
Write Expansion
I
In the single device or width expansion configuration, WXI together with FL and RXI Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion
Out) of the previous device.
RXIA
RXIB
Read Expansion
I
In the single device or width expansion configuration, RXI together with FL and WXI, Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read
Expansion Out) of the previous device.
FFA/IRA
FFB/IRB
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.
In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EFA/ORA
EFB/ORB
Empty Flag/
Output Ready
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is
empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at
the outputs.
PAEA
PAEB
Programmable
Almost-Empty flag
O
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset
at reset is 31 from empty for IDT72V805LB, 63 from empty for IDT72V815LB, and 127 from empty for IDT7V2825LB/
72V835LB/72V845LB.
PAFA
PAFB
Programmable
Almost-Full Flag
O
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 from full for IDT72V805LB, 63 from full for IDT72V815LB, and 127 from full for IDT72V825LB/
72V835LB/72V845LB.
WXOA/HFA
WXOB/HFB
Write Expansion
O
In the single device or width expansion configuration, the device is more than half full Out/Half-Full Flag
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device
when the last location in the FIFO is written.
RXOA
RXOB
Read Expansion
Out
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location
in the FIFO is read.
QA0–QA17
QB0-QB17
Data Outputs
O
Data outputs for an 18-bit bus.
VCC
Power
+3.3V power supply pins.
GND
Ground
Ground pins.
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
RECOMMENDED OPERATING DC
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +5
Unit
V
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
mA
Symbol
Parameter
VCC
Supply Voltage
Commercial/Industrial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
0
0
0
V
GND
Supply Voltage
VIH
Input High Voltage
Commercial/Industrial
2.0
—
5.0
V
VIL(1)
Input Low Voltage
Commercial/Industrial
—
—
0.8
V
TA
Operating Temperature
Commercial
0
—
70
°C
TA
Operating Temperature
Industrial
-40

85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Min.
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Typ.
Max.
Unit
Input Leakage Current (any input)
–1
—
1
µA
ILO
Output Leakage Current
–10
—
10
µA
VOH
Output Logic “1” Voltage, IOH = –2 mA
2.4
—
—
V
VOL
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
V
ICC1(4,5,6)
Active Power Supply Current
—
—
60
mA
ICC2(4,7)
Standby Current
—
—
10
mA
Symbol
ILI(2)
(3)
Parameter
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical ICC1 = 2[2.04 + 0.88*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC –0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
Symbol
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
4
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
tXO
tXI
tXIS
tSKEW1
tSKEW2(4)
Parameter
Clock Cycle Frequency—
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Asynchronous Programmable
Almost-Full Flag
Write Clock to Synchronous
Programmable Almost-Full Flag
Clock to Asynchronous Programmable
Almost-Empty Flag
Read Clock to Synchronous
Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Setup Time
Skew time between Read Clock &
Write Clock for FF/IR and EF/OR
Skew time between Read Clock &
Write Clock for PAE and PAF
Commercial
Com’l & Ind’l(2)
Commercial
IDT72V805L10
IDT72V815L10
IDT72V825L10
IDT72V835L10
IDT72V845L10
Min.
Max.
100
—
2
6.5
10
—
4.5
—
4.5
—
3
—
0.5
—
3
—
0.5
—
10
—
8
—
8
—
—
15
0
—
—
6
1
6
—
6.5
—
6.5
—
17
IDT72V805L15
IDT72V815L15
IDT72V825L15
IDT72V835L15
IDT72V845L15
Min.
Max.
66.7
—
2
10
15
—
6
—
6
—
4
—
1
—
4
—
1
—
15
—
10
—
10
—
—
15
0
—
3
8
3
8
—
10
—
10
—
20
IDT72V805L20
IDT72V815L20
IDT72V825L20
IDT72V835L20
IDT72V845L20
Min.
Max.
50
MHz
2
12
20
—
8
—
8
—
5
—
1
—
5
—
1
—
20
—
12
—
12
—
—
20
0
—
3
10
3
10
—
12
—
12
—
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
8
—
10
—
12
ns
—
17
—
20
—
22
ns
—
8
—
10
—
12
ns
—
—
3
3
5
17
6.5
—
—
—
—
—
6.5
5
6
20
10
—
—
—
—
—
8
8
8
22
12
—
—
—
ns
ns
ns
ns
ns
14
—
18
—
20
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Values guaranteed by design, not currently tested.
4. t SKEW2 applies to synchronous PAE and synchronous PAF only.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Unit
510Ω
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
30pF*
4295 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
5
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
FUNCTIONAL DESCRIPTION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
completely empty for IDT72V815, and 127 away from completely empty for
IDT72V825/72V835/72V845. Continuing read operations will cause the
FIFO to be empty. When the last word has been read from the FIFO, the EF
will go LOW inhibiting further read operations. REN is ignored when the
FIFO is empty.
TIMING MODES:
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
The IDT72V805/72V815/72V825/72V835/72V845 support two different
timing modes of operation. The selection of which mode will operate is
determined during configuration at Reset (RS). During a RS operation, the
First Load (FL), Read Expansion Input ( RXI), and Write Expansion Input
(WXI) pins are used to select the timing mode per the truth table shown in
Table 3. In IDT Standard Mode, the first word written to an empty FIFO will
not appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating Read Enable
(REN) and enabling a rising Read Clock (RCLK) edge, will shift the word
from internal memory to the data output lines. In FWFT mode, the first word
written to an empty FIFO is clocked directly to the data output lines after
three transitions of the RCLK signal. A REN does not have to be asserted
for accessing the first word.
Various signals, both input and output signals operate differently depending on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the Empty Offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 130th
(72V805), 258th (72V815), 514th (72V825), 1,026th (72V835), and 2,050th
(72V845) word respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will go LOW after (257-m) writes for the IDT72V805,
(513-m) writes for the IDT72V815, (1,025-m) writes for the IDT72V825,
(2,049–m) writes for the IDT72V835 and (4,097–m) writes for the IDT72V845,
where m is the Full Offset value. The default setting for this value is stated
in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 257 writes for the IDT72V805, 513 for
the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and
4,097 for the IDT72V845. Note that the additional word in FWFT mode is
due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the Empty Offset value. If there is no Empty Offset
specified, the PAE will be LOW when the device is 32 away from completely
empty for IDT72V805, 64 away from completely empty for IDT72V815, and
128 away from completely empty for IDT72V825/72V835/72V845. Continuing read operations will cause the FIFO to be empty. When the last word has
been read from the FIFO, OR will go HIGH inhibiting further read operations.
REN is ignored when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the Empty Offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 129th (72V805), 257th (72V815), 513th (72V825), 1,025th
(72V835), and 2,049th (72V845) word respectively was written into the
FIFO. Continuing to write data into the FIFO will cause the Programmable
Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the
PAF will go LOW after (256-m) writes for the IDT72V805, (512-m) writes for
the IDT72V815, (1,024-m) writes for the IDT72V825, (2,048–m) writes for
the IDT72V835 and (4,096–m) writes for the IDT72V845. The offset “m” is
the Full Offset value. This parameter is also user programmable. See
section on Programmable Flag Offset Loading. If there is no Full Offset
specified, the PAF will be LOW when the device is 31 away from completely
full for IDT72V805, 63 away from completely full for IDT72V815, and 127
away from completely full for the IDT72V825/72V835/72V845.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 256 writes for the IDT72V805, 512 for the
IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096
for the IDT72V845, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and the Half-Full flag (HF) to
go HIGH at the conditions described in Table 1. If further read operations
occur, without write operations, the Programmable Almost-Empty flag
(PAE) will go LOW when there are n words in the FIFO, where n is the Empty
Offset value. If there is no Empty Offset specified, the PAE will be LOW when
the device is 31 away from completely empty for IDT72V805, 63 away from
PROGRAMMABLE FLAG LOADING
Full and Empty flag Offset values can be user programmable. The
IDT72V805/72V815/72V825/72V835/72V845 has internal registers for these
offsets. Default settings are stated in the footnotes of Table 1 and Table 2.
Offset values are loaded into the FIFO using the data input lines D0-D11.
To load the offset registers, the Load (LD) pin and WEN pin must be held
LOW. Data present on D0-D11 will be transferred in to the Empty Offset
register on the first LOW-to-HIGH transition of WCLK. By continuing to hold
the LD and WEN pin low, data present on D0-D11 will be transferred into
the Full Offset register on the next transition of the WCLK. The third
transition again writes to the Empty Offset register. Writing all offset
registers does not have to occur at one time. One or two offset registers can
be written and then by bringing the LD pin HIGH, the FIFO is returned to
6
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
grams, see Figure 13 for asynchronous PAE timing and Figure 14 for
asynchronous PAF timing.
If synchronous PAE/PAF configuration is selected , the PAE is asserted
and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. For
detail timing diagrams, see Figure 22 for synchronous PAE timing and
Figure 23 for synchronous PAF timing.
normal read/write operation. When the LD pin and WEN are again set LOW,
the next offset register in sequence is written.
The contents of the offset registers can be read on the data output lines
Q0-Q11 when the LD pin is set LOW and REN is set LOW. Data can then
be read on the next LOW-to-HIGH transition of RCLK. The first transition
of RCLK will present the Empty Offset value to the data output lines. The
next transition of RCLK will present the Full Offset value. Offset register
content can be read out in the IDT Standard mode only. It cannot be read
in the FWFT mode.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
during the "Configuration at Reset" cycle described in Table 4 with single,
double or triple register-buffered flag output signals. The various combinations available are described in Table 4 and Table 5. In general, going from
single to double or triple buffered flag outputs removes the possibility of
metastable flag indications on boundary states (i.e, empty or full conditions). The trade-off is the addition of clock cycle delays for the respective
flag to be asserted. Not all combinations of register-buffered flag outputs
are supported. Register-buffered outputs apply to the Empty Flag and Full
Flag only. Partial flags are not effected. Table 4 and Table 5 summarize
the options available.
SYNCHRONOUS VS ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
during the "Configuration at Reset" cycle described in Table 3 with either
asynchronous or synchronous timing for PAE and PAF flags.
If asynchronous PAE/PAF configuration is selected (as per Table 3), the
PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is
asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72V805
IDT72V815
0
0
1 to n
(1)
1 to n
Number of Words in FIFO
IDT72V825
0
(1)
1 to n
(1)
IDT72V835
IDT72V845
0
0
1 to n
(1)
1 to n
(1)
FF PAF
HF
H
H
H
PAE EF
L
L
H
H
H
H
L
(n + 1) to 128
(n + 1) to 256
(n + 1) to 512
(n + 1) to 1,024
(n + 1) to 2,048
H
H
H
H
H
129 to (256-(m+1))(2)
257 to (512-(m+1))(2)
513 to (1,024-(m+1))(2)
1,025 to (2,048-(m+1))(2)
2,049 to (4,096-(m+1))(2)
H
H
L
H
H
(256-m) to 255
(512-m) to 511
(1,024-m) to 1,023
(2,048-m) to 2,047
(4,096-m) to 4,095
H
L
L
H
H
256
512
1,024
2,048
4,096
L
L
L
H
H
IDT72V835
IDT72V845
IR
0
0
L
H
H
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n=31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m=31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72V805
IDT72V815
0
0
(1)
Number of Words in FIFO
IDT72V825
0
(1)
(1)
(1)
(1)
PAF HF PAE OR
L
H
L
1 to (n + 1)
1 to (n + 1)
1 to (n + 1)
L
H
H
L
(n + 2) to 129
(n + 2) to 257
(n + 2) to 513
(n + 2) to 1,025
(n + 2) to 2,049
L
H
H
H
L
130 to (257-(m+1))(2)
258 to (513-(m+1))(2)
514 to (1,025-(m+1))(2)
1,026 to (2,049-(m+1))(2)
2,050 to (4,097-(m+1))(2)
L
H
L
H
L
(257-m) to 256
(513-m) to 512
(1,025-m) to 1,024
(2,049-m) to 2,048
(4,097-m) to 4,096
L
L
L
H
L
257
513
1,025
2,049
4,097
H
L
L
H
L
1 to (n + 1)
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n = 31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m = 31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
7
1 to (n + 1)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
0
0
0
0
0
1
0
1
0
0(1)
1
1
1
0
0
1
0
1
1
1
0
1(2)
1
1
EF/OR
Single Register-Buffered
Empty Flag
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
FF/IR
Single Register-Buffered
Full Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
PAE, PAF
FIFO TIMING MODE
Asynchronous
Standard
Asynchronous
FWFT
Asynchronous
Standard
Asynchronous
Standard
Synchronous
Standard
Synchronous
FWFT
Synchronous
Standard
Asynchronous
Standard
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO
and WXO outputs of the preceding device.
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
Empty Flag (EF)
Buffered Output
Full Flag (FF)
Buffered Output
Partial Flags
Timing Mode
Programming at Reset
FL
RXI
WXI
Flag Timing
Diagrams
Single
Single
Asynch
0
0
0
Figure 9, 10
Single
Single
Sync
1
0
0
Figure 9, 10
Double
Double
Asynch
0
1
0
Figure 24, 26
Double
Double
Synch
1
1
0
Figure 24, 26
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
Output Ready (OR)
Input Ready (IR)
Partial Flags
Triple
Double
Asynch
0
0
1
Figure 27
Triple
Double
Sync
1
0
1
Figure 20, 21
8
Programming at Reset
FL
RXI
WXI
Flag Timing
Diagrams
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
SIGNAL DESCRIPTIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EFA/EFB) will go
LOW, inhibiting further read operations. REN is ignored when the FIFO is
empty. Once a write is performed, EF will go HIGH allowing a read to occur.
The EF flag is updated on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RSA/RSB)
Reset is accomplished whenever the Reset (RSA/RSB) input is taken to
a LOW state. During reset, both internal read and write pointers are set to
the first location. A reset is required after power-up before a write operation
can take place. The Half-Full flag (HFA/HFB) and Programmable AlmostFull flag (PAFA/PAFB) will be reset to HIGH after tRSF. The Programmable
Almost-Empty flag (PAEA/PAEB) will be reset to LOW after tRSF. The Full
Flag (FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset
to LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During
reset, the output register is initialized to all zeros and the offset registers
are initialized to their default values.
LD
WEN
0
0
WCLK
Selection
Writing to offset registers:
Empty Offset
Full Offset
WRITE CLOCK (WCLKA/WCLKB)
A write cycle is initiated on the LOW-to-HIGH transition of the Write
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
WRITE ENABLE (WENA/WENB)
When the WENA/WENB input is LOW, data may be loaded into the
FIFO RAM array on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF flag is updated on
the rising edge of WCLK.
To prevent data overflow in the FWFT mode, Input Ready (IRA,IRB) will
go HIGH, inhibiting further write operations. Upon the completion of a valid
read cycle, IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
Figure 2. Writing to Offset Registers
17
0
11
EMPTY OFFSET REGISTER
DEFAULT VALUE
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
17
11
0
FULL OFFSET REGISTER
DEFAULT VALUE
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
READ CLOCK (RCLKA/RCLKB)
Data can be read on the outputs on the LOW-to-HIGH transition of the
Read Clock (RCLKA/RCLKB), when Output Enable (OEA/OEB) is set
LOW.
The Write and Read Clocks can be asynchronous or coincident.
4295 drw 04
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
READ ENABLE (RENA/RENB)
When Read Enable (RENA/RENB) is LOW, data is loaded from the RAM
array into the output register on the rising edge of every RCLK cycle if the
device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0Qn maintain the previous data value.
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (ORA/ORB) will go HIGH with a true read (RCLK with
REN = LOW), inhibiting further read operations. REN is ignored when the
FIFO is empty.
9
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
OUTPUT ENABLE (OEA/OEB)
When Output Enable (OEA/OEB) is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is disabled (HIGH),
the Q output data bus is in a high-impedance state.
LOAD (LDA/LDB)
The IDT72V805/72V815/72V825/72V835/72V845 devices contain two
12-bit offset registers with data on the inputs, or read on the outputs. When
the Load (LDA/LDB) pin is set LOW and WEN is set LOW, data on the
inputs D0-D11 is written into the Empty offset register on the first LOW-toHIGH transition of the Write Clock (WCLK). When the LD pin and WEN are
held LOW then data is written into the Full offset register on the second
LOW-to-HIGH transition of WCLK. The third transition of WCLK again
writes to the Empty offset register.
However, writing all offset registers does not have to occur at one time.
One or two offset registers can be written and then by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When the LD
pin is set LOW, and WEN is LOW, the next offset register in sequence is
written.
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when
the LD pin is set LOW and REN is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read Clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The
read and write pointers operate independently). Offset register content
can be read out in the IDT Standard mode only. It is inhibited in the FWFT
mode.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FLA/FLB)
For the single device mode, see Table I for additional information. In
the Daisy Chain Depth Expansion configuration, FLA/FLB is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXIA/WXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. WXIA/WXIB is connected to Write Expansion Out
(WXOA/WXOB) of the previous device in the Daisy Chain Depth Expansion mode.
READ EXPANSION INPUT (RXIA/RXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. RXIA/RXIB is connected to Read Expansion Out
(RXOA/RXOB) of the previous device in the Daisy Chain Depth Expansion
mode.
OUTPUTS:
FULL FLAG/INPUT READY (FFA/IRA, FFB/IRB)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FFA/
FFB) function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no reads
are performed after a reset, FF will go LOW after D writes to the FIFO.
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D = 256 writes for the IDT72V805, 512 for the IDT72V815, 1,024 for the
IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845.
In FWFT mode, the Input Ready (IRA/IRB) function is selected. IR goes
LOW when memory space is available for writing in data. When there is
no longer any free space left, IR goes HIGH, inhibiting further write
operations.
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72V205LB, 513 for the IDT72V215LB, 1,025 for the IDT72V225LB,
2,049 for the IDT72V235LB and 4,097 for the IDT72V245LB. Note that the
additional word in FWFT mode is due to the capacity of the memory plus
output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (EFA/ORA, EFB/ORB)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not
empty.
In FWFT mode, the Output Ready (ORA/ORB) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAFA/PAFB)
The Programmable Almost-Full flag (PAFA/PAFB) will go LOW when
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (RS), the PAF will go LOW after (256-m) writes
for the IDT72V805, (512-m) writes for the IDT72V815, (1,024-m) writes for
the IDT72V825, (2,048–m) writes for the IDT72V835 and (4,096-m) writes
for the IDT72V845. The offset “m” is defined in the FULL offset register.
In FWFT mode, if no reads are performed, PAF will go LOW after (257m) writes for the IDT72V805, (513-m) writes for the IDT72V815, (1,025-m)
writes for the IDT72V825, (2,049-m) writes for the IDT72V835 and (4,097m) writes for the IDT72V845. The default values for m are noted in Table
1 and 2.
If asynchronous PAF configuration is selected, the PAF is asserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK).
If synchronous PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA/PAEB)
The PAE flag will go LOW when the FIFO reads the almost-empty
condition. In IDT Standard mode, PAE will go LOW when there are n words
or less in the FIFO. In FWFT mode, the PAE will go LOW when there are
n+1 words or less in the FIFO. The offset “n” is defined as the Empty offset.
The default values for n are noted in Table 1 and 2.
If asynchronous PAE configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
WRITE EXPANSION OUT/HALF-FULL FLAG
(WXOA/HFA, WXOB/HFB)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (WXIA/WXIB) and/or Read Expansion In
(RXIA/RXIB) are grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled, and at the LOW-to-HIGH transition of
the next write cycle, the Half-Full flag goes LOW and will remain set until
the difference between the write pointer and read pointer is less than or
equal to one half of the total memory of the device. The Half-Full flag (HFA/
HFB) is then reset to HIGH by the LOW-to-HIGH transition of the Read
Clock (RCLK). The HF is asynchronous.
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO
of the previous device. This output acts as a signal to the next device in
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
the Daisy Chain by providing a pulse when the previous device writes to
the last location of memory.
READ EXPANSION OUT (RXOA/RXOB)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the
previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device reads from the last
location of memory.
DATA OUTPUTS (Q0-Q17, QB0-QB17)
Q0-Q17 are data outputs for 18-bit wide data.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
tRS
RS
t RSR
REN, WEN, LD
tRSS
FL, RXI, WXI
(1)
RCLK, WCLK
t RSR
CONFIGURATION SETTING
(2)
t RSF
FF/IR
t RSF
FWFT Mode
EF/OR
IDT Standard Mode
t RSF
PAF, WXO/
HF, RXO
t RSF
PAE
t RSF
(3)
OE = 1
Q0 - Q17
OE = 0
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to V CC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
4295 drw 05
Figure 5. Reset Timing(2)
t CLKH
t CLK
t CLKL
WCLK
t DS
t DH
D0 - D17
DATA IN VALID
t ENS
t ENH
NO OPERATION
WEN
t WFF
t WFF
FF
t SKEW1 (1)
RCLK
REN
4295 drw 06
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than t SKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
12
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
t CLK
t CLKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t CLKL
RCLK
t ENS
t ENH
NO OPERATION
REN
t REF
t REF
EF
tA
Q0 - Q17
VALID DATA
t OLZ
t OHZ
t OE
OE
t SKEW1
(1)
WCLK
WEN
4295 drw 07
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than t SKEW1, then EF may not change state until the next RCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
WCLK
t DS
D0 (first valid write)
D0 - D17
D1
D2
D3
tA
tA
D4
t ENS
WEN
t SKEW1
t FRL(1)
RCLK
t REF
EF
tENS
REN
Q0 - Q17
D0
t OLZ
D1
t OE
OE
4295 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
NO WRITE
NO WRITE
WCLK
t SKEW1(1)
t SKEW1(1)
t DS
D0 - D17
t DS
DATA
WRITE
DATA WRITE
t WFF
t WFF
t WFF
FF
WEN
RCLK
t ENS
t ENS
t ENH
t ENH
REN
OE
LOW
tA
Q0 - Q17
tA
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4295 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
WCLK
tDS
tDS
DATA WRITE 1
D0 - D17
tENS
DATA WRITE 2
tENS
tENH
tENH
WEN
(1)
tFRL
tFRL
(1)
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN
OE LOW
tA
Q0 - Q17
DATA READ
DATA IN OUTPUT REGISTER
4295 drw 10
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The
Latency Timing apply only at the Empty Boundary (EF = LOW).
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
14
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0—D15
PAE OFFSET
PAF OFFSET
D0—D11
4295 drw 11
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN
tA
Q0—Q15
PAE OFFSET
UNKNOWN
PAE OFFSET
PAF OFFSET
4295 drw 12
Figure 12. Read Programmable Registers (IDT Standard Mode)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
tPAEA
n words in FIFO(2),
n + 1 words in FIFO(3)
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
RCLK
tENS
REN
4295 drw 13
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
tCLKH
tCLKL
WCLK
tENS
(1)
tENH
WEN
tPAFA
PAF
D - m words
in FIFO
D - (m + 1) words in FIFO
D - (m + 1) words
in FIFO
tPAFA
RCLK
tENS
REN
4295 drw 14
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
D/2 + 1 words in FIFO(2),
D/2 words in FIFO(2),
[
D-1
2 +1
(3)
[D-1
2 + 2] words in FIFO
] words in FIFO(3)
D/2 words in FIFO(2),
[D-1
2
]
+ 1 words in FIFO(3)
tHF
RCLK
tENS
REN
4295 drw 15
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
16
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
WCLK
Note 1
tXO
tXO
WXO
tENS
WEN
4295 drw 16
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
tCLKH
RCLK
Note 1
tXO
tXO
RXO
tENS
REN
4295 drw 17
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
t XI
WXI
t XIS
WCLK
4295 drw 18
Figure 18. Write Expansion In Timing
t XI
RXI
t XIS
RCLK
4295 drw 19
Figure 19. Read Expansion In Timing
17
18
tDS
W1
tENS
W2
2
DATA IN OUTPUT REGISTER
1
tSKEW1
tDH
W3
3
tREF
tA
W4
tDS
W1
W[n +2]
1
W[n+3]
tPAES
tSKEW2 (2)
W[n+4]
W[
tDS
]
D-1 +1
2
W[
]
D-1 +2
2
tHF
W[
2
]
D-1 +3
W[D-m-2]
tDS
W[D-m-1]
W[D-m]
W[D-m+1]
tPAFS
1
W[D-m+2]
W[D-1]
WD
Figure 20. Write Timing with Synchronous Programmable Flags (FWFT Mode)
tENH
4295 drw 20
tWFF
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WLCK and the rising edge of RCLK is less than
tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 257 words for the IDT72V805, 513 words for the IDT72V815, 1,025 words for the IDT72V825, 2,049 words for the IDT72V835 and 4,097 words for the IDT72V845.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,1) during Reset.
IR
PAF
HF
PAE
OR
Q0 - Q17
REN
RCLK
D0 - D17
WEN
WCLK
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
tDS
tENS
W1
tOHZ
WD
tENS
tWFF
tDH
tENH
W1
tOE
tA
W2
1
(1)
tSKEW1
tA
2
tWFF
W3
Wm+2
(2)
tSKEW2
tPAFS
W[m+3]
tA
W[m+4]
W[
]
D-1 + 1
2
tHF
W[
tA
]
D-1 + 2
2
W[D-n-1]
tA
W[D-n]
1
tPAES
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
4295 drw 21
tREF
Figure 21. Read Timing with Synchronous Programmable Flags (FWFT Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK plus tWFF. If the time between the rising edge of RLCK and the rising edge of WCLK is
less than tSKEW1, then the IR assertion may be delayed an extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
3. LD = HIGH
4. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 257 words for the IDT72V805, 513 words for the IDT72V815, 1,025 words for the IDT72V825, 2,049 words for IDT72V835 and 4,097 words for IDT72V845.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,1) during Reset.
IR
PAF
HF
PAE
OR
Q0 - Q17
OE
REN
RCLK
D0 - D17
WEN
WCLK
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO(2),
n + 1words in FIFO(3)
n Words in FIFO(2),
n + 1 words in FIFO(3)
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
tSKEW2 (4)
tPAES
tPAES
RCLK
tENS
tENH
REN
4295 drw 22
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAFS
PAF
D-(m+1) Words in FIFO
D -(m+1) Words
in FIFO
D - m Words in FIFO
tSKEW2(3)
tPAFS
RCLK
tENS
tENH
4295 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
20
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
NO WRITE
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
WCLK
2
1
1
tDS
(1)
tSKEW1
2
tDS
(1)
tSKEW1
D0 - D17
DATA WRITE
Wd
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
tENS
tENH
tENS
REN
OE LOW
tA
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
NEXT DATA READ
DATA READ
4295 drw 24
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t WFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
tCLK
t CLKH
WCLK
1
tCLKL
2
tDS
tDH
D0 - D17
DATAIN VALID
tENS
tENH
NO OPERATION
WEN
tWFF
tWFF
FF
tSKEW1(1)
RCLK
REN
4295 drw 25
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t RFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
tCLK
tCLKH
1
RCLK
tCLKL
2
tENH
tENS
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 - Q17
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
tSKEW1
WCLK
tENH
tENS
WEN
tDS
D0 - D17
tDH
FIRST WORD
4295 drw 26
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)
WCLK
tENH
tENS
WEN
tDS
D0
- D17
tDH
W1
tDS
W2
t SKEW1
RCLK
W3
W4
W[n+3]
W[n +2]
(1)
1
2
3
REN
tA
Q0 - Q17
W1
DATA IN OUTPUT REGISTER
tREF
tREF
OR
4295 drw 27
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the
rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
22
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
OPERATING CONFIGURATIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
application requirements are for 256/512/1,024/2,048/4,096 words or less.
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72V805/72V815/
72V825/72V835/72V845 may be used as a stand-alone device when the
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE (WEN)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
IDT
72V805
72V815
72V825
72V835
72V845
DATA IN (D0 - D17)
FULL FLAG/INPUT READY (FF/IR)
DATA OUT (Q0 - Q17)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAE)
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FL
RXI
WXI
4295 drw 28
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(one of the two FIFOs contained in the IDT72V805/72V815/72V825/72V835/72V845)
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two
IDT72V805/72V815/72V825/72V835/72V845s. Any word width can be
attained by adding additional IDT72V805/72V815/72V825/72V835/72V845s.
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 29). Please see the Application Note AN-83.
RESET (RS)
DATA IN (D)
36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
FF/IR
FULL FLAG/INPUT
READY (FF/IR)
FIFO B
FIFO A
HALF FULL FLAG (HF)
FL
EF/OR
FF/IR
FL
WXI RXI
EMPTY FLAG/OUTPUT
READY (EF/OR)
EF/OR
WXI RXI
18
DATA OUT (Q)
36
18
4295 drw 29
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of the Two FIFOs Contained in One IDT72V805/72V815/72V825/72V835/72V845
Configured for a 36-Bit Width Expansion
23
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72V805/72V815/72V825/72V835/72V845s. Maximum depth is limited only by signal loading. Follow these steps:
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Write Expansion In (WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 30
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
1. The first device must be designated by grounding the First Load (FL)
control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the
IDT72V845
WXOA RXOA
WCLKA
WENA
RCLKA
RSA
RENA
OEA
LDA
FIFO A
4,096 x 18
DAn
QAn
Vcc
FLA
FFA/IRA EFA/ORA
PAEA
PAFA
WXIA
RXIA
DATA IN
DATA OUT
WRITE CLOCK
WRITE ENABLE
WXOB RXOB
WCLKB RCLKB
READ CLOCK
WENB
READ ENABLE
RESET
RSB
DBn
LOAD
LDB
RENB
OEB
QBn
OUTPUT ENABLE
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
FF
PAF
PAFB
WXIB
PAEB
RXIB
EF
PAE
FIRST LOAD (FL)
4295 drw 30
Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags
Used in Depth Expansion Configuration
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72V805/72V815/72V825/72V835/72V845
devices.
24
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the OR flag.
The “ripple down” delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
HF
HF
PAF
PAE
TRANSFER CLOCK
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA IN
WCLK
WCLK
RCLK
OR
WEN
72V805
72V815
72V825
72V835
72V845
IR
OE
n
Dn
Qn
FL
RXI
WEN
REN
REN
READ ENABLE
OR
OUTPUT READY
OE
OUTPUT ENABLE
72V805
72V815
72V825
72V835
72V845
IR
GND
n
n
DATA OUT
Qn
Dn
FL
WXI
READ CLOCK
RCLK
RXI
WXI
4295 drw 31
(0,1)
GND
(0,1)
VCC
GND
VCC
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory
with Programmable Flags Used in Depth Expansion Configuration
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
Thin Quad Flatpack (TQFP, PK128-1)
10
15
20
Commercial Only
Com’l & Ind’l
Commercial Only
L
Low Power
72V805
72V815
72V825
72V835
72V845
256 x 18  3.3V Dual Synchronous FIFO
512 x 18  3.3V Dual Synchronous FIFO
1,024 x 18  3.3V Dual Synchronous FIFO
2,048 x 18  3.3V Dual Synchronous FIFO
4,096 x 18  3.3V Dual Synchronous FIFO
Clock Cycle Time (tCLK)
Speed in Nanoseconds
4295 drw 32
NOTE:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
DATASHEET DOUCUMENT HISTORY
04/26/2001
pgs. 1, 4, 5 and 26.
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26
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