Cypress CY7C1020D 512k (32k x 16) static ram automatic power-down when deselected Datasheet

CY7C1020D
512K (32K x 16) Static RAM
Features
Functional Description [1]
■
Pin- and function-compatible with CY7C1020B
■
High speed
The CY7C1020D is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO0 through IO15) are placed in a high-impedance state when:
— tAA = 10 ns
■
Low active power
— ICC = 80 mA @ 10ns
■
Low complementary metal oxide semiconductor (CMOS)
standby power
— ISB2 = 3 mA
■
2.0 V data retention
■
Automatic power-down when deselected
■
CMOS for optimum speed/power
■
Independent control of upper and lower bits
■
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
BHE and BLE are disabled (BHE, BLE HIGH)
■
When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A14). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A14).
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Logic Block Diagram
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
32K x 16
RAM Array
IO0–IO7
IO8–IO15
BHE
WE
CE
OE
BLE
A14
A12
A13
A8
A9
A10
A11
COLUMN DECODER
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05463 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 7, 2011
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CY7C1020D
Contents
Pin Configurations ............................................................ 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics.................................................. 4
Capacitance ....................................................................... 5
Thermal Resistance........................................................... 5
AC Test Loads and Waveforms........................................ 5
Switching Characteristics................................................. 6
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 9
Document #: 38-05463 Rev. *G
Ordering Information...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY7C1020D
Pin Configurations[2]
SOJ/TSOP II
Top View
NC
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A4
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
NC
Selection Guide
–10 (Industrial)
Unit
Maximum access time
10
ns
Maximum operating current
80
mA
Maximum CMOS standby current
3
mA
Note
2. NC pins are not connected on the die.
Document #: 38-05463 Rev. *G
Page 3 of 15
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CY7C1020D
DC input voltage [3] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into outputs (LOW) ......................................... 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage............................................ >2001 V
(per MIL-STD-883, Method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current ...................................................... >200mA
Ambient temperature with
power applied ........................................... –55 C to +125 C
Operating Range
Supply voltage on VCC to Relative GND [3] ..–0.5 V to +6.0 V
DC voltage applied to outputs
in High Z State [3] ................................. –0.5 V to VCC + 0.5 V
Range
Ambient
Temperature
VCC
Speed
Industrial
–40 °C to +85 °C
5 V  0.5 V
10 ns
Electrical Characteristics (Over the Operating Range)
Parameter
Description
–10 (Industrial)
Test Conditions
VOH
Output HIGH voltage
IOH = –4.0 mA
VOL
Output LOW voltage
IOL = 8.0 mA
VIH
Input HIGH voltage
[3]
Unit
Min
Max
2.4
–
V
–
0.4
V
–
2.2
VCC + 0.5V
V
–
–0.5
0.8
V
VIL
Input LOW voltage
IIX
Input load current
GND < VI < VCC
–1
+1
A
IOZ
Output leakage current
GND < VI < VCC, output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
–
80
mA
83 MHz
–
72
mA
66 MHz
–
58
mA
40 MHz
–
37
mA
ISB1
Automatic CE power-down
current—TTL inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fmax
–
10
mA
ISB2
Automatic CE Power-Down
current—CMOS inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
–
3
mA
Note
3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
Document #: 38-05463 Rev. *G
Page 4 of 15
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CY7C1020D
Capacitance [4]
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Unit
8
pF
8
pF
Thermal Resistance [4]
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ
TSOP II
Unit
59.52
53.91
C/W
36.75
21.24
C/W
AC Test Loads and Waveforms [5]
ALL INPUT PULSES
3.0V
Z = 50
90%
OUTPUT
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5V
Rise Time: 3 ns
(a)
(b)
Fall Time: 3 ns
High-Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R2
255
5 pF
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05463 Rev. *G
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CY7C1020D
Switching Characteristics (Over the Operating Range) [6]
Parameter
Description
–10 (Industrial)
Min
Max
Unit
Read Cycle
tpower [7]
VCC(typical) to the first access
100

s
tRC
Read cycle time
10

ns
tAA
Address to data valid

10
ns
tOHA
Data hold from address change
3

ns
tACE
CE LOW to data valid

10
ns
tDOE
OE LOW to data valid

5
ns
OE LOW to Low Z
tLZOE
tHZOE
[9]
OE HIGH to High Z
tLZCE
CE LOW to Low Z
[9]
CE HIGH to High Z
tHZCE
[8, 9]
[8, 9]
0
ns

5
ns
3

ns

5
ns
tPU
[10]
CE LOW to power-up
0

ns
tPD
[10]
CE HIGH to power-down

10
ns
tDBE
Byte enable to data valid
5
ns
tLZBE
Byte enable to Low Z
0

ns
Byte disable to High Z

5
ns
tWC
Write cycle time
10

ns
tSCE
CE LOW to write end
7

ns
tAW
Address set-up to write end
7

ns
tHA
Address hold from write end
0

ns
tSA
Address set-up to write start
0

ns
tPWE
WE pulse width
7

ns
tSD
Data set-up to write end
6

ns
tHD
Data hold from write end
tHZBE
Write Cycle
[11, 12]
0

ns
WE HIGH to Low Z
[9]
3

ns
tHZWE
WE LOW to High Z
[8, 9]

5
ns
tBW
Byte enable to end of write
7

ns
tLZWE
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 5. Transition is measured when the
outputs enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05463 Rev. *G
Page 6 of 15
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CY7C1020D
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min
Max
Unit

2.0

V

3
mA
VDR
VCC for data retention
ICCDR
Data retention current
tCDR [13]
Chip deselect to data retention time

0

ns
Operation recovery time

tRC

ns
tR
[14]
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Data Retention Waveform
DATA RETENTION MODE
4.5V
VCC
VDR > 2V
4.5V
tCDR
tR
CE
Switching Waveforms
Figure 1. Read Cycle No.1 (Address Transition Controlled) [15, 16]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 2. Read Cycle No.2 (OE Controlled) [16, 17]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tHZBE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
15. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
16. WE is HIGH for read cycle.
17. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05463 Rev. *G
Page 7 of 15
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CY7C1020D
Switching Waveforms(continued)
Figure 3. Write Cycle No. 1 (CE Controlled) [18, 19]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA IO
Figure 4. Write Cycle No. 2 (BLE or BHE Controlled) [18, 19]
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA IO
Notes
18. Data IO is high impedance if OE or BHE and/or BLE= VIH.
19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05463 Rev. *G
Page 8 of 15
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CY7C1020D
Switching Waveforms(continued)
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA IO
tLZWE
Truth Table
CE
OE
WE
H
X
X
X
X
High Z
High Z
Power-down
Standby (ISB)
L
L
H
L
L
Data out
Data out
Read – All bits
Active (ICC)
L
H
Data out
High Z
Read – Lower bits only
Active (ICC)
H
L
High Z
Data out
Read – Upper bits only
Active (ICC)
L
L
Data in
Data in
Write – All bits
Active (ICC)
L
H
Data in
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data in
Write – Upper bits only
Active (ICC)
L
X
L
BLE
BHE
IO0–IO7
IO8–IO15
Mode
Power
L
H
H
X
X
High Z
High Z
Selected, outputs disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
selected, outputs disabled
Active (ICC)
Notes
20. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05463 Rev. *G
Page 9 of 15
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CY7C1020D
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
Package Type
CY7C1020D-10VXI
51-85082
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1020D-10ZSXI
51-85087
44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 02 0
D - 10 XXX I
Temperature Range:
I = Industrial
Package Type: XXX = VX or ZSX
VX = 44-pin Molded SOJ (Pb-free)
ZSX = 44-pin TSOP Type II (Pb-free)
Speed: 10 ns
D = C9, 90 nm Technology
0 = Data width × 16-bits
02 = 512-Kbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05463 Rev. *G
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CY7C1020D
Package Diagrams
Figure 6. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082 *C
Document #: 38-05463 Rev. *G
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CY7C1020D
Package Diagrams(continued)
Figure 7. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087 *C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05463 Rev. *G
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CY7C1020D
Acronyms
Acronym
Description
BGA
ball grid array
CMOS
complementary metal oxide semiconductor
FBGA
very fine ball gird array
I/O
input/output
TSOP
thin small outline package
SRAM
static random access memory
TTL
Transistor transistor logic
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
A
microamperes
mA
milliampere
MHz
megahertz
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Document #: 38-05463 Rev. *G
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CY7C1020D
Document History Page
Document Title: CY7C1020D, 512K (32K x 16) Static RAM
Document #: 38-05463
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
201560
See ECN
SWI
Advance Data sheet for C9 IPP
*A
233695
See ECN
RKF
1) DC parameters modified as per EROS (Spec # 01-0216)
2) Pb-free Offering in the ‘Ordering Information’
*B
263769
See ECN
RKF
1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4
2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram
3) Added Tpower Spec in Switching Characteristics Table
4) Added Data Retention Characteristics Table and Waveforms
5) Shaded ‘Ordering Information’
*C
307594
See ECN
RKF
Reduced Speed bins to –10, –12 and –15 ns
*D
560995
See ECN
VKN
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
*E
802877
See ECN
VKN
Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*F
3109992
12/14/2010
AJU
Added Ordering Code Definitions.
Updated Package Diagrams.
*G
3219056
04/07/2011
PRAS
Document #: 38-05463 Rev. *G
Added TOC
Added Acronyms and Units of Measure table.
Updated Datasheet as per template.
Page 14 of 15
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CY7C1020D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05463 Rev. *G
Revised April 7, 2011
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