Hitachi HM6264BLFPI-12T 64k sram (8-kword x 8-bit) wide temperature range version Datasheet

HM6264BI Series
64k SRAM (8-kword × 8-bit)
Wide Temperature Range version
ADE-203-492C (Z)
Rev. 3.0
May. 8, 2000
Description
The Hitachi HM6264BI is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance and
low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil SOP (foot
print pitch width), 600 mil plastic DIP, is available for high density mounting.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 100/120 ns (max)
• Power dissipation:
 Standby: 10 µW (typ)
 Operation: 15 mW (typ) (f = 1 MHz)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
 Three state output
• Directly TTL compatible
 All inputs and outputs
• Battery backup operation capability
• Operating temperature range: –40˚C to +85˚C
HM6264BI Series
Ordering Information
Type No.
Access time
Package
HM6264BLPI-10
HM6264BLPI-12
100 ns
120 ns
600-mil, 28-pin plastic DIP (DP-28)
HM6264BLFPI-10T
HM6264BLFPI-12T
100 ns
120 ns
450-mil, 28-pin plastic SOP(FP-28DA)
Pin Arrangement
HM6264BLPI/BLFPI Series
NC
A12
A7
A6
A5
A4
A3
1
2
A2
A1
A0
8
9
10
11
12
21
20
19
18
17
VCC
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
13
14
16
15
I/O5
I/O4
I/O1
I/O2
I/O3
VSS
28
27
26
25
24
3
4
5
6
7
23
22
(Top view)
2
HM6264BI Series
Pin Description
Pin name
Function
A0 to A12
Address input
I/O1 to I/O8
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
NC
No connection
VCC
Power supply
VSS
Ground
Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
Row
decoder
I/O1
CS2
CS1
VCC
VSS
Column I/O
Input
data
control
I/O8
Memory array
256 × 256
Column decoder
A1 A2 A0 A10 A3
Timing pulse generator
Read, Write control
WE
OE
3
HM6264BI Series
Function Table
WE
CS1
CS2
OE
Mode
VCC current
I/O pin
Ref. cycle
×
H
×
×
Not selected (power down)
I SB , I SB1
High-Z
—
×
×
L
×
Not selected (power down)
I SB , I SB1
High-Z
—
H
L
H
H
Output disable
I CC
High-Z
—
H
L
H
L
Read
I CC
Dout
Read cycle (1)–(3)
L
L
H
H
Write
I CC
Din
Write cycle (1)
L
L
H
L
Write
I CC
Din
Write cycle (2)
Note: ×: H or L
Absolute Maximum Ratings
Parameter
1
Power supply voltage*
1
Symbol
Value
VCC
–0.5 to +7.0
Unit
V
2
3
Terminal voltage*
VT
–0.5* to V CC + 0.3* V
Power dissipation
PT
1.0
W
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–40 to +85
°C
Notes: 1. Relative to VSS
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
VIH
2.4
—
VCC + 0.3
V
—
0.6
V
Input high voltage
Input low voltage
Note:
4
VIL
1
–0.3*
1. VIL min: –3.0 V for pulse half-width ≤ 50 ns
HM6264BI Series
DC Characteristics (Ta = –40 to +85°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
|ILI|
—
—
2
µA
Vin = VSS to V CC
Output leakage current
|ILO |
—
—
2
µA
CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to V CC
Operating power supply
current
I CCDC
—
7
20
mA
CS1 = VIL, CS2 = VIH, I I/O = 0 mA
others = VIH/VIL
Average operating power I CC1
supply current
—
30
50
mA
Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH, I I/O = 0 mA
others = VIH/VIL
I CC2
—
3
8
mA
Cycle time = 1 µs, duty = 100%, II/O = 0 mA
CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
I SB
—
1
3
mA
CS1 = VIH, CS2 = VIL
I SB1*2
—
2
200
µA
CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
Output low voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
Output high voltage
VOH
2.4
—
—
V
I OH = –1.0 mA
Standby power supply
current
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. VIL min = –0.3V
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
1
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
5
pF
Vin = 0 V
CI/O
—
—
7
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
5
HM6264BI Series
AC Characteristics (Ta = –40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.6 V to 2.4 V
Input and output timing reference level: 1.5 V
Input rise and fall time: 10 ns
Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)
Read Cycle
HM6264BI-10 HM6264BI-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Read cycle time
t RC
100
—
120
—
ns
Address access time
t AA
—
100
—
120
ns
CS1
t CO1
—
100
—
120
ns
CS2
t CO2
—
100
—
120
ns
t OE
—
50
—
60
ns
CS1
t LZ1
10
—
10
—
ns
2
CS2
t LZ2
10
—
10
—
ns
2
Output enable to output in low-Z
t OLZ
5
—
5
—
ns
2
Chip deselection in to output in high-Z CS1
t HZ1
0
35
0
40
ns
1, 2
CS2
t HZ2
0
35
0
40
ns
1, 2
Output disable to output in high-Z
t OHZ
0
35
0
40
ns
1, 2
Output hold from address change
t OH
10
—
10
—
ns
Chip select access time
Output enable to output valid
Chip selection to output in low-Z
Notes
Notes: 1. t HZ is defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. At any given temperature and voltage condition, t HZ maximum is less than tLZ minimum both for a
given device and from device to device.
3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.
6
HM6264BI Series
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tCO1
CS1
tLZ1
tCO2
CS2
tHZ1
tLZ2
tOE
tHZ2
tOLZ
OE
tOHZ
Dout
High Impedance
Valid data
tOH
Read Timing Waveform (2) (WE = VIH, OE = VIL )
Address
Valid address
t AA
t OH
Dout
t OH
Valid data
7
HM6264BI Series
Read Timing Waveform (3) (WE = VIH, OE = VIL )*3
t CO1
CS1
t HZ1
t LZ1
t HZ2
CS2
t CO2
t LZ2
Dout
8
Valid data
HM6264BI Series
Write Cycle
HM6264BI-10 HM6264BI-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t WC
100
—
120
—
ns
Chip selection to end of write
t CW
80
—
85
—
ns
2
Address setup time
t AS
0
—
0
—
ns
3
Address valid to end of write
t AW
80
—
85
—
ns
Write pulse width
t WP
60
—
70
—
ns
1, 9
Write recovery time
t WR
0
—
0
—
ns
4
WE to output in high-Z
t WHZ
0
35
0
40
ns
5
Data to write time overlap
t DW
40
—
40
—
ns
Data hold from write time
t DH
0
—
0
—
ns
Output active from end of write
t OW
5
—
5
—
ns
Output disable to output in high-Z
t OHZ
0
35
0
40
ns
5
Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write begins at
the latest transition among CS1 going low,CS2 going high and WE going low. A write ends at the
earliest transition among CS1 going high CS2 going low and WE going high. Time tWP is measured
from the beginning of write to the end of write.
2. t CW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. t AS is measured from the address valid to the beginning of write.
4. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite phase
to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in high
impedance state.
7. Dout is the same phase of the written data in this write cycle.
8. Dout is the read data of the next address
9. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention
t WP ≥ tWHZ max + tDW min.
9
HM6264BI Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
Valid address
OE
tCW
tWR
CS1
*1
CS2
tAW
tAS
tWP
WE
tOHZ
Dout
Din
10
tDW
High Impedance
High Impedance
tDH
Valid data
HM6264BI Series
Write Timing Waveform (2) (OE Low Fixed) (OE = VIL )
tWC
Address
Valid address
tAW
tWR
tCW
CS1
*1
CS2
tWP
WE
tAS
tOH
tOW
tWHZ
*2
Dout
tDW
*3
tDH
*4
Din
High Impedance
Valid data
11
HM6264BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ*1 Max
Unit
Test conditions*3
VCC for data retention
VDR
2.0
—
—
V
CS1 ≥ VCC –0.2 V,
CS2 ≥ VCC –0.2 V or CS2 ≤ 0.2 V
Vin ≥ 0 V
Data retention current
I CCDR
—
1* 1
100* 2
µA
VCC = 3.0 V, 0 V ≤ Vin ≤ VCC
CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V
or 0 V ≤ CS2 ≤ 0.2 V
Chip deselect to data
retention time
t CDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
5
—
—
ms
Notes: 1. Reference data at Ta = 25°C.
2. 10 µA max at Ta = –40 to + 40°C.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If
CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
12
HM6264BI Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR
Data retention mode
tR
VCC
4.5 V
2.4 V
VDR
CS1 ≥ VCC – 0.2 V
CS1
0V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
4.5 V
CS2
VDR
0.6 V
0 V ≤ CS2 ≤ 0.2 V
0V
13
HM6264BI Series
Package Dimensions
HM6264BLPI Series (DP-28)
35.6
36.5 Max
15
13.4
14.6 Max
28
Unit: mm
14
1.2
2.54 ± 0.25
0.48 ± 0.10
0.51 Min
1.9 Max
15.24
2.54 Min 5.70 Max
1
+ 0.11
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
14
DP-28
—
Conforms
4.6 g
HM6264BI Series
Package Dimensions (cont.)
HM6264BLFPI Series (FP-28DA)
Unit: mm
18.00
18.75 Max
15
14
1.27
0.15
*0.40 ± 0.08
0.38 ± 0.06
0.15
0.20 +– 0.10
1.12 Max
*0.17 ± 0.05
0.15 ± 0.04
1
3.00 Max
8.40
28
11.80 ± 0.30
1.70
0° – 8°
1.00 ± 0.20
0.20 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-28DA
Conforms
Conforms
0.82 g
15
HM6264BI Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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For further information write to:
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(America) Inc.
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Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
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Germany
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Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
16
HM6264BI Series
Revision Record
Rev.
Date
Contents of Modification
Drawn by
Approved by
0.0
Dec. 1, 1995
Initial issue
I. Ogiwara
K. Yoshizaki
1.0
Sep. 5, 1996
Deletion of Preliminary
I. Ogiwara
K. Imato
2.0
Feb. 9, 1998
Change of subtitle
Change of FP-28DA
I. Ogiwara
K. Imato
3.0
May. 8, 2000
Low VCC Data Retention Characteristics
Note 2: VIL min = −0.3 V to
10 µA max at Ta = –40 to + 40°C
17
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