Cypress CY7C1019CV33-15VC 128k x 8 static ram Datasheet

CY7C1019CV33
128K x 8 Static RAM
Features
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
• Pin and function compatible with CY7C1019BV33
• High speed
— tAA = 10 ns
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Data retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in Pb-free and non Pb-free 48-ball VFBGA,
32-pin TSOP II and 400-mil SOJ package
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in Standard 48-ball FBGA,
32-pin TSOP II and 400-mil-wide SOJ packages
Logic Block Diagram
Pin Configuration
SOJ/TSOP II
Top View
A0
A1
A2
A3
I/O
0
INPUT BUFFER
CE
I/O0
I/O1
VCC
V SS
I/O
1
I/O
2
128K x 8
ARRAY
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O
3
I/O2
I/O3
WE
A4
A5
A6
A7
I/O
4
I/O
5
CE
COLUMN
DECODER
I/O
6
POWER
DOWN
I/O
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
OE
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1019CV33
Pin Configuration[1]
48-ball VFBGA
(Top View)
2
3
4
5
6
NC
OE
A2
A6
A7
NC
A
I/O0
NC
A1
A5
CE
I/O7
B
I/O1
NC
A0
A4
NC
I/O6
C
VSS
NC
NC
A3
NC
VCC
D
VCC
NC
NC
NC
NC
VSS
E
I/O2
NC
A14
A11
I/O4
I/O5
F
I/O3
NC
A15
A12
WE
A8
G
NC
A10
A16
A13
A9
NC
H
1
Selection Guide
-10
-12
-15
Unit
Maximum Access Time
10
12
15
ns
Maximum Operating Current
80
75
70
mA
Maximum Standby Current
5
5
5
mA
Note:
1. NC pins are not connected on the die.
Document #: 38-05130 Rev. *F
Page 2 of 10
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CY7C1019CV33
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current...................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Commercial
Industrial
DC Input Voltage[2] .................................–0.5V to VCC + 0.5V
Ambient
Temperature
VCC
0°C to +70°C
3.3V ± 10%
–40°C to +85°C
3.3V ± 10%
Electrical Characteristics Over the Operating Range
–10
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Min.
–12
Max.
Min.
2.4
VCC = Min.,
IOL = 8.0 mA
Max.
Min.
2.4
0.4
Voltage[2]
–15
Max.
Unit
2.4
0.4
V
0.4
V
V
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
VIL
Input LOW
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current GND < VI < VCC
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–1
+1
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
80
75
70
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
15
15
15
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
5
5
5
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
Notes:
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *F
Page 3 of 10
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CY7C1019CV33
AC Test Loads and Waveforms[4]
R 317Ω
90%
OUTPUT
R2 GND
351Ω
30 pF
High-Z characteristics:
ALL INPUT PULSES
3.0V
3.3V
R 317Ω
90%
3.3V
10%
10%
OUTPUT
R2
351Ω
5 pF
(b)
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(a)
(c)
Switching Characteristics Over the Operating Range[5]
-10
Parameter
Description
Min.
-12
Max.
Min.
-15
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
10
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
12
10
3
15
12
3
ns
15
3
ns
ns
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
OE HIGH to High
CE LOW to Low
0
Z[6, 7]
Z[7]
tHZCE
CE HIGH to High
tPU[8]
tPD[8]
CE LOW to Power-Up
Write
5
3
Z[6, 7]
6
3
5
0
ns
7
3
6
7
ns
ns
15
12
ns
ns
0
0
10
CE HIGH to Power-Down
0
0
ns
Cycle[9, 10]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-Up to Write End
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
ns
[7]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z[6, 7]
3
3
5
3
6
ns
7
ns
Notes:
4. AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using
the test load shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05130 Rev. *F
Page 4 of 10
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CY7C1019CV33
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05130 Rev. *F
Page 5 of 10
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CY7C1019CV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tHZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 16
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
I/O0–I/O7
Mode
Power
CE
OE
WE
H
X
X
High Z
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05130 Rev. *F
Page 6 of 10
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CY7C1019CV33
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
CY7C1019CV33-10VC
51-85033
CY7C1019CV33-10ZXC
51-85095
CY7C1019CV33-10ZXI
12
Commercial
32-pin TSOP II (Pb-Free)
32-pin TSOP II (Pb-Free)
CY7C1019CV33-12VC
51-85033
32-pin 400-Mil Molded SOJ
51-85095
32-pin TSOP II
51-85033
32-pin 400-Mil Molded SOJ
CY7C1019CV33-12ZXC
15
32-pin 400-Mil Molded SOJ
CY7C1019CV33-12ZC
CY7C1019CV33-12VI
Operating
Range
Package Type
Industrial
Commercial
32-pin TSOP II (Pb-Free)
CY7C1019CV33-12BVXI
51-85150
48-ball VFBGA (Pb-Free)
CY7C1019CV33-15VC
51-85033
32-pin 400-Mil Molded SOJ
CY7C1019CV33-15VXC
51-85033
32-pin 400-Mil Molded SOJ (Pb-Free)
CY7C1019CV33-15ZXC
51-85095
32-pin TSOP II (Pb-Free)
CY7C1019CV33-15ZXI
51-85095
32-pin TSOP II (Pb-Free)
Industrial
Commercial
Industrial
Package Diagrams
32-pin (400-Mil) Molded SOJ (51-85033)
51-85033-*B
Document #: 38-05130 Rev. *F
Page 7 of 10
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CY7C1019CV33
Package Diagrams (continued)
32-pin TSOP II (51-85095)
51-85095-**
Document #: 38-05130 Rev. *F
Page 8 of 10
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CY7C1019CV33
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
51-85150-*D
1.00 MAX
0.26 MAX.
SEATING PLANE
C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05130 Rev. *F
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1019CV33
Document History Page
Document Title: CY7C1019CV33 128K x 8 Static RAM
Document Number: 38-05130
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
109245
12/16/01
HGK
New Data Sheet
*A
113431
04/10/02
NSL
AC Test Loads split based on speed
Description of Change
*B
115047
08/01/02
HGK
Added TSOP II Package and I Temp. Improved ICC limits
*C
119796
10/11/02
DFP
Updated standby current from 5 nA to 5 mA
*D
123030
12/17/02
DFP
Updated Truth Table to reflect single Chip Enable option
*E
419983
See ECN
NXR
Added 48-ball VFBGA Package
Added lead-free parts in Ordering Information Table
Replaced Package Name column with Package Diagram in the Ordering
Information Table
*F
493543
See ECN
NXR
Removed 8 ns speed bin from Product offering
Added note #1 on page #2
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information
Document #: 38-05130 Rev. *F
Page 10 of 10
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