ON MC100LVE222FA 3.3 v/5.0 v ecl 1:15 differential ã·1/ã·2 clock driver Datasheet

MC100LVE222
3.3 V/5.0 VECL 1:15
Differential ÷1/÷2 Clock Driver
The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be differential or used
single−ended (with VBB output reference bypassed and connected to the
unused input of a pair). Either of two fully differential clock inputs may
be selected. Each of the four output banks of 2, 3, 4, and 6 differential
pairs may be indwependently configured to fanout 1X or 1/2X of the
input frequency. The LVE222 specifically guarantees low output to
output skew. Optimal design, layout, and processing minimize skew
within a device and from lot to lot.
The fsel pins and CLK_Sel pin are asynchronous control inputs. Any
changes may cause indeterminate output states requiring an MR pulse
to resynchronize any 1/2X outputs.
The device tpd is affected by the quantity of output pairs terminated
with a minimum occurring with only one output pair and increasing
about 10−20 ps for all output pairs. Relative skew distribution is not
affected as more pairs are terminated, but the increased tpd does shift
the entire distribution. Unused output pairs should be left unterminated
(open) to reduce power and switching noise.
The MC100LVE222, as with most ECL devices, can be operated
from a positive VCC/VCCO supply in PECL mode. This allows the
LVE222 to be used for high performance clock distribution in +3.3 V
systems. Operation with >3.8 |(VCC or VCCO−VEE| span will require
special thermal handling considerations. Designers can take advantage
of the LVE222’s performance to distribute low skew clocks across the
backplane or the board. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. All power supply pins must be connected. For more
information on using PECL, designers should refer to Application Note
AN1406/D. For a SPICE model, refer to Application Note AN1560/D.
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MARKING DIAGRAM*
LQFP
FA SUFFIX
CASE 848D
MC100LVE
222
AWLYYWWG
52
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
200 ps Part−to−Part Skew
50 ps Output−to−Output Skew
Selectable 1x or 1/2x Frequency Outputs
ESD Protection: >2 kV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC/VCCO = 3.0 V to 5.25 V with
VEE = 0 V
NECL Mode Operating Range: VCC/VCCO = 0 V with VEE = −3.0 V
to −5.25 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 2
For Additional Information, refer to Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 684 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
October, 2005− Rev. 11
1
Publication Order Number:
MC100LVE222/D
39
38
37
36
35
34
33
32
31
30
29
28
VCCO
NC
NC
VCCO
Qc3
Qc3
Qc2
Qc2
Qc1
Qc1
Qc0
Qc0
VCCO
MC100LVE222
Table 1. PIN DESCRIPTION
27
VCCO
40
26
Qd0
Qb2
41
25
Qd0
Qb2
42
24
Qd1
Qb1
43
23
Qd1
Qb1
44
22
Qd2
Qb0
45
21
Qd2
20
Qd3
MC100LVE222
Qd4
Qa0
50
16
Qd5
Qa0
51
15
Qd5
VCCO
52
14
VCCO
1
2
3
4
5
6
7
8
9
10
11
12
13
VEE
17
fseld
49
fselc
Qa1
VBB
Qd4
CLK1
18
CLK1
48
CLK_Sel
Qa1
CLK0
Qd3
CLK0
19
fselb
47
fsela
VCCO
MR
46
VCC
Qb0
PIN
FUNCTION
CLK0, CLK0
CLK1, CLK1
CLK_Sel
MR
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Qc0:3, Qc0:3
Qd0:5, Qd0:5
fseln
VBB
VCC/VCCO
VEE
ECL Differential Input Clock
ECL Differential Input Clock
ECL Clock Select
ECL Master Reset
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL 1 or 2 Select
Reference Voltage Output
Positive Supply (VCC = VCCO)
Negative Supply
No Connect
NC
Note: All VCC/VCCO, and VEE pins must be
externally connected to Power Supply to
guarantee proper operation. All VCC/VCCO pins
are internally interconnected.
Table 2. FUNCTION TABLE
Function
Figure 1. Pinout Assignment (Top View)
Input
L
H
MR
CLK_Sel
fseln
Active
CLK0
÷1
Reset
CLK1
÷2
MR
CLK0
CLK0
CLK1
CLK1
CLK_Sel
VBB
÷1
2
÷2
Qa0:1
Qa0:1
fsela
3
Qb0:2
Qb0:2
fselb
4
Qc0:3
Qc0:3
fselc
6
Qd0:5
Qd0:5
fseld
Figure 2. Logic Diagram
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2
MC100LVE222
CLK
RESET
Q
1/2Q
Figure 3. Timing Diagram
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC/VCCO
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC or VCCO = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC or VCCO = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
52 LQFP
52 LQFP
70
48
°C/W
°C/W
qJC
Thermal Resistance (Junction to Case)
standard board
52 LQFP
TBD
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI (VCC or VCCO)
VI VEE
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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MC100LVE222
Table 4. LVPECL DC CHARACTERISTICS VCC or VCCO = 3.3 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
122
136
Min
85°C
Typ
Max
122
136
Min
Typ
Max
Unit
125
139
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
Vpp < 500 mV
Vpp y 500 mV
1.3
1.6
2.9
2.9
1.2
1.5
2.9
2.9
1.2
1.5
2.9
2.9
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
Others
CLK0, CLK1
0.5
−300
150
0.5
−300
mA
mA
0.5
−300
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC/VCCO. VEE can vary +0.3 V to −1.95 V. Operation with |VCC or VCCO−VEE| w3.8 V span will
require special thermal handling considerations.
2. Outputs are terminated through a 50 W resistor to (VCC or VCCO) − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC/VCCO. VIHCMR is defined as the range within which the VIH level may vary, with
the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and
greater than or equal to VPP(min).
Table 5. LVNECL DC CHARACTERISTICS VCC or VCCO = 0.0 V; VEE = −3.3 V (Note 4)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
122
136
122
136
125
139
mA
VOH
Output HIGH Voltage (Note 5)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 5)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
Vpp < 500 mV
Vpp y 500 mV
−2.0
−1.7
−0.4
−0.4
−2.1
−1.8
−0.4
−0.4
−2.1
−1.8
−0.4
−0.4
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
Others
CLK0, CLK1
0.5
−300
150
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC/VCCO. VEE can vary +0.3 V to −1.95 V. Operation with |VCC or VCCO−VEE| w3.8 V span will
require special thermal handling considerations.
5. Outputs are terminated through a 50 W resistor to (VCC or VCCO) − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC/VCCO. VIHCMR is defined as the range within which the VIH level may vary, with
the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and
greater than or equal to VPP(min).
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4
MC100LVE222
Table 6. AC CHARACTERISTICS VCC or VCCO = 3.3 V; VEE = 0.0 V or VCC/VCCO = 0.0 V; VEE = −3.3 V (Note 7)
−40°C
Symbol
Characteristic
Min
Typ
1.2
> 1.5
1040
940
1100
1140
1140
1250
25°C
Max
Min
Typ
1.2
> 1.5
1080
980
1170
1180
1180
1320
70°C
Max
Min
Typ
1.2
> 1.5
1120
1020
1220
1220
1220
1370
Max
Unit
fmax
Maximum Toggle Frequency
GHz
tPLH
tPHL
Propagation Delay to Output
IN (differential) (Note 8)
IN (single−ended) (Note 9)
MR
tskew
Within−Device Skew (Note 10)
Part−to−Part Skew
(Differential Configuration)
tJITTER
Random CLOCK Jitter (RMS)
VPP
Input Swing (Differential) (Note 11)
400
1000
400
1000
400
1000
mV
tr/tf
Output Rise/Fall Time 20%−80%
200
600
200
600
200
600
ps
ps
1240
1290
1400
1280
1330
1470
50
200
50
200
< 1.0
1320
1370
1520
50
200
< 1.0
< 1.0
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary +0.3 V to −1.95 V. Operation with |VCC or pVCCO−VEE| w3.8 V span will require special thermal handling considerations.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
11. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output.
Q
Z = 50 W
D
Receiver
Device
Driver
Device
Q
Z = 50 W
50 W
D
50 W
V TT
VTT = (VCC or VCCO) − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
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MC100LVE222
ORDERING INFORMATION
Package
Shipping †
MC100LVE222FA
LQFP−52
160 Units / Rail
MC100LVE222FAR2
LQFP−52
1500 / Tape & Reel
MC100LVE222FAG
LQFP−52
(Pb−Free)
160 Units / Rail
MC100LVE222FAR2G
LQFP−52
(Pb−Free)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1404
−
ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1560
−
Low Voltage ECLinPS SPICE Modeling Kit
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
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MC100LVE222
PACKAGE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 848D−03
ISSUE D
4X
4X 13 TIPS
0.20 (0.008) H L−M N
0.20 (0.008) T L−M N
52
−X−
X=L, M, N
40
1
CL
39
3X
AB
VIEW Y
G
AB
−L−
−M−
VIEW Y
B
V
B1
BASE METAL
F
PLATING
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
V1
J
13
27
14
26
0.13 (0.005)
−N−
A1
M
D
T L−M
U
N
S
S
SECTION AB−AB
S1
ROTATED 90° CLOCKWISE
A
0.05 (0.002)
S
S
W
q1
C
4X
q2
0.10 (0.004) T
C2
q
−T−
4X
K
q3
C1
E
VIEW AA
VIEW AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −H− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −L−, −M− AND −N− TO BE DETERMINED
AT DATUM PLANE −H−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −T−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
θ
θ1
θ2
θ3
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7
R1
0.25 (0.010)
GAGE PLANE
−H−
SEATING
PLANE
2X R
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
−−−
1.70
0.05
0.20
1.30
1.50
0.20
0.40
0.45
0.75
0.22
0.35
0.65 BSC
0.07
0.20
0.50 REF
0.08
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0_
7_
−−−
0_
12 _ REF
12 _ REF
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
−−− 0.067
0.002
0.008
0.051
0.059
0.008
0.016
0.018
0.030
0.009
0.014
0.026 BSC
0.003
0.008
0.020 REF
0.003
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0_
7_
−−−
0_
12 _ REF
12 _ REF
Z
MC100LVE222
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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