ON MC10E131FNG 5v ecl 4-bit d flip-flop Datasheet

MC10E131, MC100E131
5VECL 4-Bit D Flip-Flop
Description
The MC10E/100E131 is a quad master-slave D-type flip-flop with
differential outputs. Each flip-flop may be clocked separately by
holding Common Clock (CC) LOW and using the Clock Enable (CE)
inputs for clocking. Common clocking is achieved by holding the CE
inputs LOW and using CC to clock all four flip-flops. In this case, the
CE inputs perform the function of controlling the common clock, to
each flip-flop.
Individual asynchronous resets are provided (R). Asynchronous set
controls (S) are ganged together in pairs, with the pairing chosen to
reflect physical chip symmetry.
Data enters the master when both CC and CE are LOW, and transfers
to the slave when either CC or CE (or both) go HIGH.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1100 MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Metastability Time Constant is 200 ps.
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 240 devices
Pb−Free Packages are Available*
MARKING DIAGRAM*
1
MCxxxE131G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1
Publication Order Number:
MC10E131/D
MC10E131, MC100E131
D3
D
CE3
R3
D2
CE2
R2
25
24
23
22
VCCO Q3
21
20
Q3
26
18
Q2
D2
D3
27
17
Q2
CE2
S12
28
16
VCC
VEE
1
15
Q1
CC
2
14
Q1
S03
3
13
Q0
D0
4
12
Q0
CE0
6
R0
7
8
9
10
D1
CE1
R1
NC
D
S
R
Q3
Q
Q3
Q
Q2
Q
Q2
Q
Q1
Q
Q1
Q
Q0
Q
Q0
R2
S03
S12
CC
R1
R
CE1
D1
11
D
S
R0
VCCO
R
CE0
* All VCC and VCCO pins are tied together on the die.
D0
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout Diagram
D
S
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN
D0 − D3
CE0 − CE3
R0 − R3
CC
S03, S12
Q0 − Q3, Q0 − Q3
VCC, VCCO
VEE
NC
Q
R3
CE3
5
R
19
Pinout: 28-Lead PLCC
(Top View)
S
FUNCTION
ECL Data Inputs
ECL Clock Enables (Individual)
ECL Resets
ECL Common Clock
ECL Sets (paired)
ECL Differential Outputs
Positive Supply
Negative Supply
No Connect
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2
MC10E131, MC100E131
Table 2. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
Tsol
Wave Solder
265
265
°C
VI v VCC
VI w VEE
Pb
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Min
Characteristic
0°C
Typ
Max
58
70
Min
25°C
Typ
Max
58
70
Min
85°C
Typ
Max
58
70
Min
Typ
Max
Unit
58
70
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
350
450
300
150
mA
IIL
Input LOW Current
CC
S
R, CE
D
350
450
300
150
350
450
300
150
0.5
0.3
350
450
300
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E131, MC100E131
Table 4. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
−40°C
Symbol
Min
Characteristic
0°C
Typ
Max
58
70
Min
25°C
Typ
Max
58
70
Min
85°C
Typ
Max
58
70
Min
Typ
Max
Unit
58
70
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 4)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
CC
S
R, CE
D
IIL
Input LOW Current
350
450
300
150
350
450
300
150
0.5
350
450
300
150
0.3
0.5
350
450
300
150
0.065
0.3
0.2
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 5. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
−40°C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage
(Note 6)
VOL
Output LOW Voltage
(Note 6)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
CC
S
R, CE
D
Min
0°C
Typ
Max
58
70
Min
25°C
Typ
Max
58
70
3975
4050
4120
3190
3295
3975
3835
3355
3190
Typ
Max
58
70
3975
4050
4120
3380
3190
3255
3975
4120
3835
3355
3525
3190
350
450
300
150
Min
Typ
Max
Unit
67
81
mA
3975
4050
4120
mV
3380
3190
3260
3380
mV
3975
4120
3835
3975
4120
mV
3355
3525
3190
3355
3525
mV
350
450
300
150
mA
350
450
300
150
0.5
85°C
0.3
Min
350
450
300
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E131, MC100E131
Table 6. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 7)
−40°C
Symbol
Characteristic
Min
0°C
Typ
Max
58
70
Min
25°C
Typ
Max
58
70
Min
85°C
Typ
Max
58
70
Min
Typ
Max
Unit
67
81
mA
IEE
Power Supply
Current
VOH
Output HIGH
Voltage (Note 8)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW
Voltage (Note 8)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1025
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1645
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
CC
S
R, CE
D
IIL
mA
350
450
300
150
Input LOW Current
350
450
300
150
0.5
0.3
350
450
300
150
0.5
0.25
350
450
300
150
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 7. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 7)
−40°C
Min
Typ
1100
1400
CE
310
275
400
300
600
600
635
550
Setup Time (Note 10)
D
200
tH
Hold Time (Note 10)
D
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
R, S
tSKEW
Within-Device Skew (Note 11)
tJITTER
Random Clock Jitter
tr/tf
Rise/Fall Time (20−80%)
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
CC
R
S
tS
CLK
25°C
Max
Min
Typ
1100
1400
360
325
450
350
500
500
640
550
20
150
225
−20
450
150
750
725
875
775
400
400
275
85°C
Min
Typ
1100
1400
360
325
450
350
500
500
640
550
20
150
20
ps
175
−20
175
−20
ps
400
150
400
150
ps
400
400
Max
700
675
825
725
Max
Unit
MHz
700
675
825
725
400
400
ps
ps
60
60
60
ps
<1
<1
<1
ps
460
725
300
480
300
480
675
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
10. Setup/hold times guaranteed for both CC and CE.
11. Within-device skew is defined as identical transitions on similar paths through a device.
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5
MC10E131, MC100E131
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E131FN
PLCC−28
37 Units / Rail
MC10E131FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E131FNR2
PLCC−28
500 / Tape & Reel
MC10E131FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E131FN
PLCC−28
37 Units / Rail
MC100E131FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E131FNR2
PLCC−28
500 / Tape & Reel
MC100E131FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E131, MC100E131
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E131, MC100E131
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
MC10E131/D
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