Rhombus LVITD-60G Lvitd series lvc low voltage logic 10-tap delay module Datasheet

LVITD Series LVC Low Voltage Logic 10-Tap Delay Modules
Inputs accept voltages up to 5.5 V
LVITD Schematic
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Vcc
Tap1 Tap3 Tap5 Tap7 Tap9 Tap10
14
13
12
11
10
9
8
3
4
5
6
7
Operating Temp. -40OC to +85OC
Low Profile 14-Pin Package
Two Surface Mount Versions
For 5-Tap 8-Pin Versions see LVMDM Series
1
2
IN
N/C
Tap2 Tap4 Tap6 Tap8 GND
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 2ns (>15ns +/- 1.0ns)
LVC Logic
10 Tap P/N
Tap 1
Tap 2
Tap 3
Tap 4
LVITD-12
3
4
5
6
7
LVITD-21
3
5
7
9
11
LVITD-30
3
6
9
12
15
LVITD-50
5
10
15
20
LVITD-60
6
12
18
LVITD-75
7.5
15
LVITD-80
8
LVITD-100
Tap 5
Tap 6
Tap-to-Tap
(ns)
Tap 7
Tap 8
Tap 9
8
9
10
11
12 ± 2.5
1.0 ± 0.4
13
15
17
19
21 ± 2.5
2.0 ± 0.6
18
21
24
27
30 ± 2.5
3.0 ± 0.8
25
30
35
40
45
50 ± 2.5
5.0 ± 1.8
24
30
36
42
48
54
60 ± 3.0
6.0 ± 2.0
22.5
30
37.5
45
52.5
60
67.5
75 ± 3.75
7.5 ± 2.0
16
24
32
40
48
56
64
72
80 ± 4.0
8.0 ± 2.0
10
20
30
40
50
60
70
80
90
100 ± 5.0
10.0 ± 2.0
LVITD-125
12.5
25
37.5
50
62.5
75
87.5
100
112.5
125 ± 6.25
12.5 ± 3.0
LVITD-150
15
30
45
60
75
90
105
120
135
150 ± 7.5
15.0 ± 3.0
Dimensions in Inches (mm)
TEST CONDITIONS -- Low Voltage CMOS, LVC
VCC Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
OPERATING SPECIFICATIONS
Supply Voltage, VCC .......................................... 3.3 ± 0.3 VDC
Supply Current, ICC ........................... 10 mA typ., 30 mA max.
Supply Current, ICCL : VIN = GND ......................... 22 mA max.
Supply Current, ICCH : VIN = VCC ............................. 10 µA max.
Input Voltage, VI ..................................... 0 V min., 5.5 V max.
Logic “1” Input, VIH .................................................. 2.0 V min.
Logic “0” Input, VIL ................................................. 0.8 V max.
Logic “1” Out, VOH: VCC = 3V & IOH = -24 mA ............ 2.0 V min.
Logic “0” Out, VOL: VCC = 3V & IOL = 24 mA ......... 0.55 V max.
Input Capacitance, CI ............................................. 5 pF, typ.
Input Pulse Width, PWI .............................. 40% of Delay min.
Operating Temperature Range ......................... -40O to +85OC
Storage Temperature Range ........................ -65O to +150OC
P/N Description
Examples: LVITD-30G =
LVITD-100 =
.250
.020 (6.35)
(0.51) MAX.
DIP
DIP
.120
(3.05)
MIN.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.365
(9.27)
MAX.
.100
(2.54)
TYP.
.285
(7.24)
MAX.
G-SMD
.050
(1.27)
TYP.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
.008 R
(0.20)
.010
(0.25)
TYP.
.430 (10.92)
.400 (10.16)
.285
(7.24)
MAX.
.265
(6.73)
MAX.
J-SMD
.050
(1.27)
TYP.
G-SMD
.250
(6.35)
MAX.
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.010
(0.25)
TYP.
.300
(7.62)
.785
(19.94)
MAX.
.020
(0.51)
TYP.
.008 R
(0.20)
.100
(2.54)
TYP.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.020 R
(0.51)
.330 (8.38)
MAX.
30ns (3ns per tap) 74LVC, 14-Pin G-SMD
100ns (10ns per tap) 74LVC, 14-Pin DIP
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.285
(7.24)
MAX.
.785
(19.94)
MAX.
LVITD - XXX X
LVC Buffered 10 Tap Delay
Molded Package Series:
14-pin DIP: LVITD
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
Total - Tap 10
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[email protected]
19
TEL: (714) 898-0960
FAX: (714) 896-0971
LVITD 2001-01
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