$GYDQFHG 3RZHU 026)(7 IRLW/I540A FEATURES BVDSS = 100 V ♦ Avalanche Rugged Technology ♦ Rugged Gate Oxide Technology RDS(on) = 0.058Ω ♦ Lower Input Capacitance ♦ Improved Gate Charge ID = 28 A ♦ Extended Safe Operating Area ♦ 175°C Operating Temperature D2-PAK ♦ Lower Leakage Current: 10µA (Max.) @ VDS = 100V ♦ Lower RDS(ON): 0.046Ω (Typ.) I2-PAK 2 1 1 2 3 3 1. Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS ID Characteristic Value Drain-to-Source Voltage 100 Continuous Drain Current (TC=25°C) 28 Continuous Drain Current (TC=100°C) 19.8 Units V A IDM Drain Current-Pulsed VGS Gate-to-Source Voltage ±20 V EAS Single Pulsed Avalanche Energy (2) 522 mJ A A 98 (1) IAR Avalanche Current (1) 28 EAR Repetitive Avalanche Energy (1) 12.1 mJ dv/dt Peak Diode Recovery dv/dt (3) 6.5 V/ns Total Power Dissipation (TA=25°C) * 3.8 W Total Power Dissipation (TC=25°C) 121 W Linear Derating Factor 0.81 W/°C PD TJ , TSTG TL Operating Junction and - 55 to +175 Storage Temperature Range °C Maximum Lead Temp. for Soldering 300 Purposes, 1/8 from case for 5-seconds Thermal Resistance Symbol RθJC Characteristic Typ. Max. Junction-to-Case -- 1.24 RθJA Junction-to-Ambient * -- 40 RθJA Junction-to-Ambient -- 62.5 Units °C/W * When mounted on the minimum pad size recommended (PCB Mount). Rev. B ©1999 Fairchild Semiconductor Corporation 1 1&+$11(/ 32:(5 026)(7 IRLW/I540A Electrical Characteristics (TC=25°C unless otherwise specified) Symbol Characteristic Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage 100 -- -- ∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- 0.1 -- IGSS IDSS RDS(on) Gate Threshold Voltage 1.0 -- 2.0 Gate-Source Leakage , Forward -- -- 100 Gate-Source Leakage , Reverse -- -- -100 -- -- 10 Drain-to-Source Leakage Current Static Drain-Source On-State Resistance µA VGS=20V VGS=-20V VDS=100V VDS=80V,TC=150°C 100 -- -- 0.058 Ω VGS=5V,ID=14A (4) 22 -- VDS=40V,ID=14A (4) -- Ciss Input Capacitance -- 1215 1580 Coss Output Capacitance -- 310 390 Crss Reverse Transfer Capacitance -- 145 180 td(on) Turn-On Delay Time -- 7 25 Rise Time -- 12 35 Turn-Off Delay Time -- 38 85 Fall Time -- 24 60 Qg Total Gate Charge -- 38.4 54 Qgs Gate-Source Charge -- 6.2 -- Qgd Gate-Drain ( Miller ) Charge -- 23.3 -- tf nA VDS=5V,ID=250µA -- Forward Transconductance td(off) V See Fig 7 -- gfs tr V/°C ID=250µA Ω VGS(th) V Test Condition VGS=0V,ID=250µA pF VGS=0V,VDS=25V,f =1MHz See Fig 5 VDD=50V,ID=28A, ns RG=4.6Ω See Fig 13 (4) (5) VDS=80V,VGS=5V, nC ID=28A See Fig 6 & Fig 12 (4) (5) Source-Drain Diode Ratings and Characteristics Symbol Characteristic Min. Typ. Max. Units Test Condition IS Continuous Source Current -- -- 28 ISM Pulsed-Source Current (1) -- -- 98 VSD Diode Forward Voltage (4) -- -- 1.5 V TJ=25°C,IS=28A,VGS=0V trr Reverse Recovery Time -- 132 -- ns TJ=25°C,IF=28A Qrr Reverse Recovery Charge -- 0.63 -- µC diF/dt=100A/µs A Integral reverse pn-diode in the MOSFET (4) Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature (2) L=1mH, IAS=28A, VDD=25V, RG=27Ω, Starting TJ =25°C (3) ISD ≤ 28A, di/dt ≤ 400A/µs, VDD ≤ BV DSS , Starting TJ =25°C (4) Pulse Test: Pulse Width = 250µs, Duty Cycle ≤ 2% (5) Essentially Independent of Operating Temperature 2 1&+$11(/ 32:(5 026)(7 IRLW/I540A Fig 1. Output Characteristics Fig 2. Transfer Characteristics V 2 10 GS Top : 7.0 V 6.0 V 102 ID , Drain Current [A] ID , Drain Current [A] 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 101 Bottom : 3.0 V @ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC 100 10-1 100 175 oC 101 25 oC @ Notes : 1. VGS = 0 V - 55 oC 2. VDS = 40 V 3. 250 µs Pulse Test 100 101 0 2 4 6 8 10 VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage IDR , Reverse Drain Current [A] VGS = 5 V 0.06 0.04 V = 10 V GS 0.02 o @ Note : TJ = 25 C 0.00 0 30 60 90 120 102 101 @ Notes : 1. V = 0 V 175 oC GS o 25 C 100 0.4 I , Drain Current [A] 0.6 2. 250 µs Pulse Test 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 V , Source-Drain Voltage [V] D SD Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage 2500 C iss 1500 C oss 1000 @ Notes : 1. VGS = 0 V 2. f = 1 MHz C rss 500 0 100 1 10 VDS , Drain-Source Voltage [V] 6 VGS , Gate-Source Voltage [V] Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd Crss= Cgd 2000 Capacitance [pF] RDS(on) , [ Ω ] Drain-Source On-Resistance 0.08 VDS = 20 V VDS = 50 V VDS = 80 V 4 2 @ Notes : ID = 28 A 0 0 8 16 24 Q , Total Gate Charge [nC] G 32 40 1&+$11(/ 32:(5 026)(7 IRLW/I540A Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature 3.0 RDS(on) , (Normalized) Drain-Source On-Resistance BVDSS , (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 @ Notes : 1. VGS = 0 V 2.5 2.0 1.5 1.0 @ Notes : 1. VGS = 5 V 2. ID = 14 A 0.5 2. ID = 250 µA 0.8 -75 -50 -25 0 25 50 75 100 125 150 175 0.0 -75 200 -50 -25 TJ , Junction Temperature [oC] 0 25 50 75 100 125 150 175 200 TJ , Junction Temperature [oC] Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature 30 ID , Drain Current [A] Operation in This Area is Limited by R DS(on) 100 µs 1 ms 10 ms 1 10 DC 0 10 @ Notes : 1. TC = 25 oC 24 18 12 6 2. TJ = 175 oC 3. Single Pulse 10-1 0 10 101 0 25 102 50 75 100 125 T , Case Temperature [oC] VDS , Drain-Source Voltage [V] c 100 D=0.5 0.2 @ Notes : 1. Z J C (t)=1.24 o C/W Max. 0.1 2. Duty Factor, D=t /t 0.05 3. TJ M -TC =PD M *Z θ 1 10- 1 θ JC 10- 2 - 5 10 2 (t) PDM 0.02 0.01 t1 θJC Thermal Response Fig 11. Thermal Response Z (t) , ID , Drain Current [A] 102 t2 single pulse 10- 4 t 1 10- 3 10- 2 10- 1 , Square Wave Pulse Duration 100 [sec] 101 150 175 1&+$11(/ 32:(5 026)(7 IRLW/I540A Fig 12. Gate Charge Test Circuit & Waveform Current Regulator VGS Same Type as DUT 50kΩ Qg 200nF 12V 10V 300nF VDS Qgs VGS Qgd DUT 3mA R1 R2 Current Sampling (IG) Resistor Charge Current Sampling (ID) Resistor Fig 13. Resistive Switching Test Circuit & Waveforms RL Vout Vout 90% VDD Vin ( 0.5 rated VDS ) RG DUT Vin 10% 10V tr td(on) td(off) t on tf t off Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD LL VDS Vary tp to obtain required peak ID BVDSS IAS ID RG C DUT ID (t) VDD VDS (t) VDD 5V tp tp Time 5 1&+$11(/ 32:(5 026)(7 IRLW/I540A Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS -- IS L Driver VGS RG VGS VGS ( Driver ) Same Type as DUT VDD dv/dt controlled by RG IS controlled by Duty Factor D Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop 6 D2PAK/TO-263 Package Dimensions 4.50 ±0.20 9.90 ±0.20 +0.10 2.00 ±0.10 (0.75) 3° ~ 0° 0.80 ±0.10 1.27 ±0.10 2.54 TYP 2.54 ±0.30 15.30 ±0.30 0.10 ±0.15 2.40 ±0.20 4.90 ±0.20 1.40 ±0.20 9.20 ±0.20 1.30 –0.05 1.20 ±0.20 +0.10 0.50 –0.05 2.54 TYP (2XR0.45) 9.20 ±0.20 15.30 ±0.30 10.00 ±0.20 (7.20) (1.75) 10.00 ±0.20 (8.00) (4.40) 4.90 ±0.20 (0.40) D2PAK/TO-263 (FS PKG CODE AB) 0.80 ±0.10 Dimensions in Millimeters September 1999, Rev B I2PAK Package Dimensions I2PAK (FS PKG CODE AO) 4.50 ±0.20 (0.40) 9.90 ±0.20 +0.10 MAX13.40 9.20 ±0.20 (1.46) 1.20 ±0.20 1.30 –0.05 0.80 ±0.10 2.54 TYP 2.54 TYP 10.08 ±0.20 1.47 ±0.10 MAX 3.00 (0.94) 13.08 ±0.20 ) 5° (4 1.27 ±0.10 +0.10 0.50 –0.05 2.40 ±0.20 10.00 ±0.20 Dimensions in Millimeters September 1999, Rev B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. E