OKI MSM51V16165DSL 1,048,576-word x 16-bit dynamic ram : fast page mode type with edo Datasheet

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E2G0132-17-61
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1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V16165D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicongate CMOS technology. The MSM51V16165D/DSL achieves high integration, high-speed operation,
and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
double-layer metal CMOS process. The MSM51V16165D/DSL is available in a 42-pin plastic SOJ or
50/44-pin plastic TSOP. The MSM51V16165DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 1,048,576-word ¥ 16-bit configuration
• Single 3.3 V power supply, ±0.3 V tolerance
• Input
: LVTTL compatible, low input capacitance
• Output : LVTTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode with EDO, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• CAS before RAS self-refresh capability (SL version)
• Package options:
42-pin 400 mil plastic SOJ
(SOJ42-P-400-1.27)
(Product : MSM51V16165D/DSL-xxJS)
50/44-pin 400 mil plastic TSOP
(TSOPII50/44-P-400-0.80-K) (Product : MSM51V16165D/DSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
ar
This
version: Mar. 1998
MSM51V16165D/DSL
in
¡ Semiconductor
MSM51V16165D/DSL
¡ Semiconductor
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
MSM51V16165D/DSL-50 50 ns 25 ns 13 ns 13 ns
84 ns
360 mW
MSM51V16165D/DSL-60 60 ns 30 ns 15 ns 15 ns
104 ns
324 mW
MSM51V16165D/DSL-70 70 ns 35 ns 20 ns 20 ns
124 ns
288 mW
1.8 mW/
0.72 mW (SL version)
1/17
¡ Semiconductor
MSM51V16165D/DSL
PIN CONFIGURATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
WE 13
42 VSS
VCC 1
50 VSS
41 DQ16
DQ1 2
49 DQ16
40 DQ15
DQ2 3
48 DQ15
39 DQ14
DQ3 4
47 DQ14
38 DQ13
DQ4 5
46 DQ13
37 VSS
VCC 6
45 VSS
36 DQ12
DQ5 7
44 DQ12
35 DQ11
DQ6 8
43 DQ11
34 DQ10
DQ7 9
42 DQ10
33 DQ9
DQ8 10
41 DQ9
32 NC
NC 11
40 NC
31 LCAS
30 UCAS
RAS 14
29 OE
A11R 15
28 A9R
NC 15
36 NC
A10R 16
27 A8R
NC 16
35 LCAS
A0 17
26 A7
WE 17
34 UCAS
A1 18
25 A6
RAS 18
33 OE
A2 19
24 A5
A11R 19
32 A9R
A3 20
23 A4
A10R 20
31 A8R
VCC 21
22 VSS
42-Pin Plastic SOJ
A0 21
30 A7
A1 22
29 A6
A2 23
28 A5
A3 24
27 A4
VCC 25
26 VSS
50/44-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A7,
A8R - A11R
Address Input
RAS
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
UCAS
Upper Byte Column Address Strobe
DQ1 - DQ16
OE
Note :
Function
Data Input/Data Output
Output Enable
WE
Write Enable
VCC
Power Supply (3.3 V)
VSS
Ground (0 V)
NC
No Connection
The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/17
¡ Semiconductor
MSM51V16165D/DSL
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
8
I/O
Controller
8
Column
Address
Buffers
Internal
Address
Counter
A0 - A7
8
A8R - A11R
4
Refresh
Control Clock
Row
Row
Address 12 DecoBuffers
ders
8
DQ1 - DQ8
Column Decoders
8
Output
Buffers
Sense Amplifiers
I/O
Selector
16
8
Input
Buffers
8
8
Input
Buffers
8
16
Memory
Cells
Word
Drivers
DQ9 - DQ16
8
Output
Buffers
8
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1 - DQ8
DQ9 - DQ16
H
*
H
*
*
High-Z
High-Z
Standby
L
*
H
High-Z
Refresh
L
H
*
L
High-Z
L
*
H
DOUT
High-Z
Lower Byte Read
L
H
L
H
L
High-Z
DOUT
Upper Byte Read
L
L
L
H
L
DOUT
DOUT
Word Read
L
L
H
L
H
DIN
H
L
L
H
Don't Care
Don't Care
DIN
Lower Byte Write
L
Upper Byte Write
L
L
L
L
H
DIN
DIN
Word Write
L
L
L
H
H
High-Z
High-Z
—
*: "H" or "L"
3/17
¡ Semiconductor
MSM51V16165D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–0.5 to 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
3.0
3.3
3.6
V
VSS
0
0
0
V
Input High Voltage
VIH
2.0
—
VCC + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Capacitance
Parameter
Input Capacitance
(A0 - A7, A8R - A11R)
Input Capacitance
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)
(VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
—
5
pF
CIN2
—
7
pF
CI/O
—
7
pF
4/17
¡ Semiconductor
MSM51V16165D/DSL
DC Characteristics
Parameter
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
Symbol
Condition
MSM51V16165 MSM51V16165 MSM51V16165
D/DSL-50
D/DSL-60
D/DSL-70 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –2.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 2.0 mA
0
0.4
0
0.4
0
0.4
V
Input Leakage Current
ILI
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
75
—
70
—
65
mA
1, 2
—
2
—
2
—
2
—
0.5
—
0.5
—
0.5
mA
1
—
200
—
200
—
200
mA
1, 5
—
75
—
70
—
65
mA
1, 2
—
5
—
5
—
5
mA
1
—
75
—
70
—
65
mA
1, 2
—
100
—
90
—
80
mA
1, 3
—
400
—
400
—
400
mA
—
300
—
300
—
300
mA
0 V £ VI £ VCC + 0.3 V;
All other pins not
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
DQ disable
0 V £ VO £ VCC
RAS, CAS cycling,
tRC = Min.
RAS, CAS = VIH
Power Supply
Current (Standby)
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
Average Power
Supply Current
ICC3 CAS = VIH,
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5 CAS = VIL,
DQ = enable
Average Power
Supply Current
ICC6
(CAS before RAS Refresh)
CAS before RAS
RAS = VIL,
Average Power
Supply Current
RAS cycling,
ICC7 CAS cycling,
(Fast Page Mode)
tHPC = Min.
Average Power
tRC = 31.3 ms,
Supply Current
ICC10 CAS before RAS,
tRAS £ 1 ms
(Battery Backup)
1, 4,
5
Average Power
Supply Current
(CAS before RAS
ICCS
RAS £ 0.2 V,
CAS £ 0.2 V
1, 5
Self-Refresh)
Notes : 1.
2.
3.
4.
5.
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V.
SL version.
5/17
¡ Semiconductor
MSM51V16165D/DSL
AC Characteristics (1/2)
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Random Read or Write Cycle Time
Symbol
tRC
MSM51V16165 MSM51V16165 MSM51V16165
D/DSL-50
D/DSL-60
D/DSL-70 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
—
—
—
124
160
30
—
—
—
ns
ns
ns
Read Modify Write Cycle Time
tRWC
84
110
—
—
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
tHPC
20
—
104
135
25
tHPRWC
58
—
68
—
78
—
ns
Access Time from RAS
tRAC
—
50
—
60
—
70
ns
4, 5, 6
Access Time from CAS
tCAC
—
13
—
15
—
20
ns
4, 5
Access Time from Column Address
Access Time from CAS Precharge
tAA
tCPA
—
—
25
30
—
—
30
35
—
—
35
40
ns
ns
4, 6
4, 13
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
13
—
—
0
15
—
—
0
20
—
ns
ns
4
4
Data Output Hold After CAS Low
tDOH
5
—
5
—
5
—
ns
CAS to Data Output Buffer Turn-off Delay Time
tCEZ
0
0
15
15
0
0
20
20
7, 8
tREZ
13
13
ns
RAS to Data Output Buffer Turn-off Delay Time
0
0
ns
7, 8
OE to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
tOEZ
tWEZ
0
0
13
13
0
0
15
15
0
0
20
20
ns
ns
7
7
Transition Time
Refresh Period
tT
tREF
1
—
50
64
1
—
50
64
1
—
50
64
ns
ms
3
16
Refresh Period (SL version)
tREF
—
128
—
128
—
128
ms
RAS Precharge Time
tRP
30
—
40
—
50
—
ns
RAS Pulse Width
tRAS
50
10,000
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode with EDO) tRASP
50
100,000
60
100,000
70
100,000
ns
RAS Hold Time
RAS Hold Time referenced to OE
tRSH
tROH
7
10
10
—
—
13
13
—
—
ns
7
—
—
CAS Precharge Time (Fast Page Mode with EDO)
tCP
7
—
10
—
10
—
ns
ns
15
CAS Pulse Width
tCAS
7
10,000
10
10,000
13
10,000
ns
CAS Hold Time
tCSH
—
40
—
45
—
13
CAS to RAS Precharge Time
tCRP
35
5
—
5
—
5
—
ns
ns
RAS Hold Time from CAS Precharge
tRHCP
30
—
35
—
40
—
ns
13
OE Hold Time from CAS (DQ Disable)
tCHO
RAS to CAS Delay Time
tRCD
—
37
5
14
—
45
5
14
—
50
RAS to Column Address Delay Time
tRAD
5
11
9
25
12
30
12
35
ns
ns
ns
5
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
7
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
12
12
Column Address Hold Time
tCAH
7
—
10
—
13
—
ns
Column Address to RAS Lead Time
tRAL
25
—
30
—
35
—
ns
6/17
¡ Semiconductor
MSM51V16165D/DSL
AC Characteristics (2/2)
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Symbol
MSM51V16165MSM51V16165 MSM51V16165
D/DSL-50
D/DSL-60
D/DSL-70 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
12
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
9, 12
Read Command Hold Time referenced to RAS
Write Command Set-up Time
tRRH
tWCS
0
0
—
—
0
0
—
—
0
0
—
—
ns
ns
9
10, 12
Write Command Hold Time
tWCH
7
—
10
—
13
—
ns
12
Write Command Pulse Width
tWP
7
—
10
—
10
—
ns
WE Pulse Width (DQ Disable)
tWPE
7
—
10
—
10
—
ns
OE Command Hold Time
7
—
10
—
13
—
ns
OE Precharge Time
tOEH
tOEP
7
—
10
—
10
—
ns
OE Command Hold Time
tOCH
7
—
10
—
10
—
ns
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tRWL
tCWL
7
7
—
—
10
10
—
—
13
13
—
—
ns
ns
Data-in Set-up Time
Data-in Hold Time
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
tDS
tDH
tOED
tCWD
tAWD
tRWD
—
—
—
—
—
—
0
10
15
34
49
79
—
—
—
—
—
—
0
13
20
44
59
94
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
11, 12
11, 12
RAS to WE Delay Time
0
7
13
30
42
67
CAS Precharge WE Delay Time
tCPWD
47
—
54
—
64
—
ns
10
CAS Active Delay Time from RAS Precharge
tRPC
5
—
5
—
5
—
ns
12
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)
tCSR
tCHR
5
10
—
—
5
10
—
—
5
10
—
—
ns
ns
12
13
tRASS
100
—
100
—
100
—
ms
16
tRPS
90
—
110
—
130
—
ns
16
tCHS
–50
—
–50
—
–50
—
ns
16
RAS Pulse Width
(CAS before RAS Self-Refresh)
RAS Precharge Time
(CAS before RAS Self-Refresh)
CAS Hold Time
(CAS before RAS Self-Refresh)
14
10
10
10
7/17
¡ Semiconductor
Notes:
MSM51V16165D/DSL
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 2 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early
write cycle, and to the WE leading edge in an OE control write cycle, or a read modify
write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS,
whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS,
whichever is later.
14. tCWL should be satisfied by both UCAS and LCAS.
15. tCP is determined by the time both UCAS and LCAS are high.
16. Only SL version.
8/17
E2G0104-17-41Q
,
,,
,
,
,,,,
,,
¡ Semiconductor
MSM51V16165D/DSL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tCRP
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRSH
tCAS
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
OE
VIH –
VIL –
tAA
tROH
tREZ
tOEA
VIH –
VIL –
tCAC
tRAC
DQ
VOH –
tOEZ
Open
VOL –
tRCH
tRRH
tCEZ
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tCRP
tCRP
VIH –
CAS
VIL –
VIH –
VIL –
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCSH
tRCD
tASC
Row
tCAH
tRAL
Column
tWCS
VIH –
WE
VIL –
tWCH
tWP
tCWL
tRWL
VIH –
OE
VIL –
tDS
DQ
VIH –
VIL –
tDH
Valid Data-in
Open
"H" or "L"
9/17
,
,,
¡ Semiconductor
MSM51V16165D/DSL
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH –
VIL –
tRP
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
10/17
,,
,,
,
,
¡ Semiconductor
MSM51V16165D/DSL
Fast Page Mode Read Cycle (Part-1)
tRASP
RAS
VIH –
VIL –
tRHCP
tCRP
CAS
WE
tHPC
tRCD
tCP
tCP
tCAS
VIH –
VIL –
tCAS
tCAS
tRAD
tASR
Address
tRP
VIH –
VIL –
tRAH
tASC
Row
tCSH
tCAH
tASC
Column
tASC
tCAH
Column
Column
tRCS
tRRH
VIH –
VIL –
tCHO
DQ
tOCH
tRAC
tAA
OE
tCAH
tOEP
tCPA
tOEA
tCAC
VOH –
VOL –
tOEZ
tCAC
Valid
Data-out
Valid
Data-out
tCLZ
tOEA
tOEA
tCAC
tDOH
tOEP
tAA
tAA
VIH –
VIL –
tOEZ
Valid*
Data-out
* : Same Data,
tREZ
Valid*
Data-out
"H" or "L"
Fast Page Mode Read Cycle (Part-2)
tRASP
RAS
VIH –
VIL –
tRHCP
WE
OE
DQ
VIH –
VIL –
VIH –
VIL –
tCP
tRAH
tCSH
tASC tCAH
Row
tASC
Column
tCAH
Column
tRCS
tCAS
tASC
tCAH
Column
tRCS
tRAC
tAA
VIH –
VIL –
VOH –
VOL –
tCP
tCAS
tRAD
tASR
Address
tRCD
tCAS
VIH –
VIL –
tCRP
tHPC
tCRP
CAS
tRP
tRCH
tWPE
tAA
tAA
tCPA
tOEA
tCAC
tCLZ
tWEZ
Valid
Data-out
tCAC
tDOH
tCAC
Valid
Data-out
tCEZ
Valid
Data-out
"H" or "L"
11/17
,,,
,
,
¡ Semiconductor
MSM51V16165D/DSL
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
VIH –
VIL –
CAS
tRAD
tRAH
VIH –
VIL –
VIH –
VIL –
OE
VIH –
VIL –
VIH –
VIL –
tCAS
tCAH
tASC
Column
tWCH
tDS
DQ
tASC
Column
tWCS
WE
tCP
tCAS
tCSH
tASC tCAH
Row
tHPC
tCP
tCAS
VIH –
VIL –
tASR
Address
tHPC
tRCD
tCRP
tWCS
tDH
Valid
Data-in
Column
tWCH
tDS
tRSH
tCAH
tDH
Valid
Data-in
tWCS
tWCH
tDS
tDH
Valid
Data-in
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
tRWD
VIH –
VIL –
tCRP
CAS
VIH –
VIL –
VIH –
VIL –
tCWD
tRAD
tASR
Address
tCP
tRCD
Row
tCWL
tCAH
tRCS
tAWD
VIH –
VIL –
tAWD
tDS tWP
tOED
tOEA
tCAC
DQ
tOEZ
Valid
Data-out
tCLZ
tRWL
tCWD
tRAC
VIH –
VIL –
VI/OH –
VI/OL –
tCPA
tCAH
Column
tAA
OE
tASC
Column
tRCS
WE
tCPWD
tHPRWC
tRAH
tASC
tAA
tOEH
tDS
tOED
tOEA
tCAC
tDH
Valid
Data-in
tOEZ
Valid
Data-out
tCLZ
tWP
tOEH
tDH
Valid
Data-in
"H" or "L"
12/17
,
¡ Semiconductor
MSM51V16165D/DSL
RAS-Only Refresh Cycle
tRC
RAS
CAS
Address
VIH –
VIL –
VIH –
VIL –
tRP
tRAS
tCRP
tRPC
tASR
VIH –
tRAH
Row
VIL –
tCEZ
DQ
VOH –
Open
VOL –
Note: WE, OE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
RAS
VIH –
VIL –
DQ
VIH –
VIL –
VOH –
VOL –
tRP
tRPC
tRPC
tCP
CAS
tRAS
tCSR
tCHR
tCEZ
Open
Note: WE, OE, Address = "H" or "L"
13/17
,
,,
,,
,
,,
¡ Semiconductor
MSM51V16165D/DSL
Hidden Refresh Read Cycle
tRC
tRAS
RAS
CAS
VIH –
VIL –
tCRP
tRAD
tASC
tASR
Address
WE
OE
VIH –
VIL –
tRSH
tRCD
VIH –
VIL –
tRRH
tRAL
tAA
tROH
tOEA
VIH –
VIL –
tCAC
tCLZ
tRAC
DQ
tCHR
Column
tRCS
VIH –
VIL –
VOH –
VOL –
tRP
tCAH
tRAH
Row
tRC
tRAS
tRP
tOEZ
Open
Valid Data-out
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRAS
RAS
CAS
Address
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
tCRP
tASR
tRCD
tRAD
tASC
tRAH
VIH –
VIL –
OE
VIH –
VIL –
DQ
VIH –
VIL –
tRSH
tCAH
tRP
tCHR
tRAL
Column
Row
tWCS
WE
tRC
tRAS
tRP
tRWL
tWCH
tWP
tDS
tDH
Valid Data-in
"H" or "L"
14/17
¡ Semiconductor
CAS before RAS Self-Refresh Cycle
tRASS
tRP
RAS
VIH –
VIL –
tRPC
tCP
CAS
VIH –
VIL –
VOH –
VOL –
tRPS
tRPC
tCHS
tCSR
tCEZ
DQ
,
MSM51V16165D/DSL
Open
Note: WE, OE, Address = "H" or "L"
Only SL version
"H" or "L"
15/17
¡ Semiconductor
MSM51V16165D/DSL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ42-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.86 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM51V16165D/DSL
(Unit : mm)
TSOPII50/44-P-400-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
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