Renesas HD74HC109RPEL Dual j-k flip-flops (with preset and clear) Datasheet

HD74HC109
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0561-0200
(Previous ADE-205-434)
Rev.2.00
Oct 11, 2005
Description
Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to
the clock input and changes state on the positive going transition of the clock pulse. Clear and preset are independent of
the clock and accomplished by a low logic level on the corresponding input.
Features
•
•
•
•
•
•
High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
Package Type
HD74HC109P
DILP-16 pin
HD74HC109FPEL
SOP-16 pin (JEITA)
HD74HC109RPEL
SOP-16 pin (JEDEC)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
P
—
FP
EL (2,000 pcs/reel)
RP
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Clear
H
Clock
X
J
X
K
X
Q
H
Q
L
H
L
L
L
X
X
X
X
X
X
L
1
H*
H
1
H*
H
H
H
H
L
H
L
L
L
H
H
H
H
L
H
H
H
Q0
H
Note:
H:
L:
X:
Outputs
Preset
L
H
Toggle
Q0
L
H
H
L
X
X
Q0
Q0
1. Q and Q will remain high as long as preset and clear input are low, but Q and Q are unpredictable if preset
and clear input go high simultaneously.
High level
Low level
Irrelevant
Rev.2.00, Oct 11, 2005 page 1 of 7
HD74HC109
Pin Arrangement
1CLR
1
16
VCC
1J
2
15
2CLR
1K
3
14
2J
1CK
4
13
2K
1PR
5
12
2CK
1Q
6
11
2PR
1Q
7
10
2Q
GND
8
9
2Q
J CK K
PR CLR
Q
Q
K CK J
CLR PR
Q
Q
(Top view)
Logic Diagram (1/2)
PR
CLR
C
C
Q
J
K
CK
Q
C
C
C
C
C
C
C
C
Absolute Maximum Ratings
Item
Supply voltage range
Symbol
VCC
Ratings
–0.5 to 7.0
Unit
V
Input / Output voltage
Input / Output diode current
Vin, Vout
IIK, IOK
–0.5 to VCC +0.5
±20
V
mA
Output current
VCC, GND current
IO
ICC or IGND
±25
±50
mA
mA
PT
Tstg
500
–65 to +150
mW
°C
Power dissipation
Storage temperature
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00, Oct 11, 2005 page 2 of 7
HD74HC109
Recommended Operating Conditions
Symbol
Ratings
Unit
Supply voltage
Input / Output voltage
Item
VCC
VIN, VOUT
2 to 6
0 to VCC
V
V
Operating temperature
Ta
–40 to 85
0 to 1000
°C
0 to 500
0 to 400
ns
Input rise / fall time
Note:
*1
tr , tf
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C
Item
Input voltage
Output voltage
Symbol VCC (V)
Typ
—
—
—
Max
—
—
—
Min
1.5
3.15
4.2
Max
—
—
—
Unit
V
Test Conditions
VIH
2.0
4.5
6.0
Min
1.5
3.15
4.2
VIL
2.0
4.5
6.0
2.0
—
—
—
1.9
—
—
—
2.0
0.5
1.35
1.8
—
—
—
—
1.9
0.5
1.35
1.8
—
4.5
6.0
4.4
5.9
4.5
6.0
—
—
4.4
5.9
—
—
4.5
6.0
4.18
5.68
—
—
—
—
4.13
5.63
—
—
2.0
4.5
6.0
4.5
6.0
—
—
—
—
—
0.0
0.0
0.0
—
—
0.1
0.1
0.1
0.26
0.26
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
V
6.0
6.0
—
—
—
—
±0.1
2.0
—
—
±1.0
20
µA Vin = VCC or GND
µA Vin = VCC or GND, Iout = 0 µA
VOH
VOL
Input current
Quiescent supply
current
Ta = –40 to+85°C
Iin
ICC
V
V
Vin = VIH or VIL IOH = –20 µA
IOH = –4 mA
IOH = –5.2 mA
Vin = VIH or VIL IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Removal time
Symbol VCC (V)
fmax
tPLH, tPHL
trem
Ta = 25°C
Ta = –40 to +85°C
Unit
Min
Typ Max
Min
Max
2.0
4.5
—
—
—
—
5
27
—
—
4
21
6.0
2.0
—
—
—
—
32
175
—
—
25
220
4.5
6.0
—
—
15
—
35
30
—
—
44
37
2.0
4.5
—
—
—
14
190
38
—
—
240
48
6.0
2.0
—
25
—
—
32
—
—
32
41
—
4.5
6.0
5
4
1
—
—
—
6
5
—
—
Rev.2.00, Oct 11, 2005 page 3 of 7
Test Conditions
ns
ns
Clock to Q or Q
ns
Preset or Clear to Clock
ns
HD74HC109
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Item
Setup time
Symbol VCC (V)
tsu
Hold time
th
Pulse width
tw
Output rise/fall
time
Input capacitance
tTLH, tTHL
Cin
Ta = –40 to +85°C
2.0
Min
100
Typ
—
Max
—
Min
125
Max
—
4.5
6.0
20
17
4
—
—
—
25
21
—
—
2.0
4.5
0
0
—
–4
—
—
0
0
—
—
6.0
2.0
0
80
—
—
—
—
0
100
—
—
4.5
6.0
16
14
5
—
—
—
20
17
—
—
2.0
4.5
—
—
—
5
75
15
—
—
95
19
6.0
—
—
—
—
5
13
10
—
—
16
10
Unit
Test Conditions
ns
Data to Latch Enable
ns
Latch Enable to Data
ns
Latch Enable
ns
pF
Test Circuit
Input
Pulse generator
Zout = 50 Ω
Input
Pulse generator
Zout = 50 Ω
VCC
See Function Table
VCC
Output
Preset
J
Q
CL = 50 pF
Clock
K
Output
Q
Clear
Note: C L includes the probe and jig capacitance.
Rev.2.00, Oct 11, 2005 page 4 of 7
CL = 50 pF
HD74HC109
Waveforms
• Waveform − 1
tr
tf
VCC
90 %
Clock
50 %
10 %
50 %
50 %
10 %
tw
VOH
90 %
50 %
90 %
50 %
10 %
Q or Q
0V
t THL
t TLH
10 %
t PLH
t PHL
t PHL
t PLH
VOL
VOH
90 %
Q or Q
50 %
10 %
50 %
10 %
VOL
t TLH
t THL
• Waveform − 2
tf
Clear
tr
VCC
90 %
50 %
10 %
90 %
50 %
10 %
0V
t w(clear)
tf
tr
90 %
50 %
90 %
50 %
Preset
10 %
t w(preset)
t PHL
t PLH
90 %
50 %
10 %
Q
t THL
t PLH
Q
0V
VOH
50 %
VOL
t PHL
VOH
90 %
50 %
10 %
VCC
50 %
VOL
t TLH
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct 11, 2005 page 5 of 7
HD74HC109
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.15g
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
θ
bp
e
Dimension in Millimeters
Min
9
c
*2
Index mark
HE
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
9.90
10.30
E
3.95
A2
1
Z
8
e
*3
bp
x
A1
0.10
0.14
0.25
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
1.75
A
M
L1
bp
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
5.80
1.27
e
x
0.25
y
0.15
Z
0.635
0.40
L
L
Rev.2.00, Oct 11, 2005 page 6 of 7
8°
1
0.60
1.08
1.27
HD74HC109
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
9
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
bp
Nom
D
10.06
E
5.50
Max
10.5
A2
8
e
Dimension in Millimeters
Min
x
A1
M
0.00
0.10
0.20
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
2.20
A
L1
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
1.27
e
x
0.12
y
0.15
Z
0.80
0.50
L
L
Rev.2.00, Oct 11, 2005 page 7 of 7
8°
1
0.70
1.15
0.90
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