Revised April 1999 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs General Description The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Note 1: Outputs in OFF-State. Features ■ High speed: fMAX = 140 MHz (typ) at TA = 25°C ■ High noise immunity: VIH = 2.0V, VIL = 0.8V ■ Power down protection is provided on all inputs and outputs ■ Low power dissipation: ICC = 4 µA (max) @ TA = 25°C ■ Pin and function compatible with 74HCT374 Ordering Code: Order Number Package Number 74VHCT374AM 74VHCT374ASJ 74VHCT374AMTC 74VHCT374AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation Description D0–D7 Data Inputs CP Clock Pulse Input 3-STATE OE Output Enable Input 3-STATE O0–O7 Outputs DS500030.prf www.fairchildsemi.com 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs July 1997 74VHCT374A Functional Description Truth Table The VHCT374A consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs Dn CP H L X Outputs OE On L H L L X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 6) 4.5V to +5.5V Supply Voltage (VCC) DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN ) (Note 3) −0.5V to VCC + 0.5V (Note 4) −0.5V to +7.0V (Note 3) 0V to VCC −20 mA (Note 4) 0V to 5.5V Input Diode Current (IIK) Output Voltage (VOUT) Output Diode Current (IOK) −40°C to +85°C Operating Temperature (TOPR) ±20 mA (Note 5) DC Output Current (IOUT) ±25 mA DC VCC/GND Current (ICC) ±75 mA Input Rise and Fall Time (tr, tf) VCC = 5.0V ± 0.5V −65°C to +150°C Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0 ns/V ∼ 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: When outputs are in OFF-State or when VCC = OV. Note 5: VOUT < GND, V OUT > VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH HIGH Level 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Typ Max Min Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level 4.5 LOW Level 4.40 ICC Quiescent Supply Current ICCT Maximum ICC/Input IOFF Output Leakage Current 4.40 V 3.80 V VIN = VIH IOH = −50 µA or VIL IOH = −8 mA VIN = VIH IOL = +50 uA 0.1 V 0.44 V 5.5 ±0.25 ±2.5 µA 0–5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND 5.5 1.35 1.50 mA OFF-State Current Input Leakage Current V 0.1 3-STATE Output (Power Down State) 0.0 Conditions 0.36 4.5 IIN 4.50 3.94 Units V LOW Level Output Voltage IOZ TA = −40°C to +85°C Min Output Voltage VOL TA = 25°C VCC (V) Parameter 0.0 0.5 5.0 µA or VIL IOL = +8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 3.4V Other Inputs = VCC or GND VOUT = 5.5V Noise Characteristics Symbol VOLP TA = 25°C VCC (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL = 50 pF Quiet Output Minimum Dynamic VOL 5.0 −1.2 −1.6 V CL = 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL = 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL = 50 pF Parameter Units Conditions (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT374A Absolute Maximum Ratings(Note 2) 74VHCT374A AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Time tPHL tPZL 3-STATE Output Enable Time tPZH tPLZ 3-STATE Output Disable Time tPHZ tOSLH Output to Output Skew tOSHL fMAX CIN Maximum Clock Frequency VCC (V) TA = 25°C Min 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 Max Min Max 4.1 9.4 1.0 10.5 5.6 10.4 1.0 11.5 6.5 10.2 1.0 11.5 7.3 11.2 1.0 12.5 7.0 5.0 ± 0.5 5.0 ± 0.5 TA = −40°C to +85°C Typ 11.2 1.0 140 80 85 130 75 Input 4 Capacitance ns ns 1.0 90 Conditions CL = 15 pF ns 12.0 1.0 Units CL = 50 pF RL = 1 kΩ CL = 15 pF CL = 50 pF RL = 1 kΩ CL = 50 pF (Note 8) CL = 15 pF MHz 10 10 pF CL = 50 pF VCC = Open COUT Output Capacitance 9 pF VCC = 5.0V CPD Power Dissipation Capacitance 25 pF (Note 9) Note 8: Parameter guaranteed by design. tOSLH = |tPLH max − t PLH min|; tOSHL = |tPHL max − tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pcs. of the octal D Flip-Flop operates can be calculated by the equation: CPD(total) = 20 + 12m. AC Operating Requirements Symbol Parameter TA = 25°C VCC (V) Min 5.0 ± 0.5 6.5 Typ TA = −40°C to +85°C Max Min tW(H) Minimum Pulse tW(L) Width (CP) tS Minimum Set-up Time 5.0 ± 0.5 2.5 2.5 tH Minimum Hold Time 5.0 ± 0.5 2.5 2.5 www.fairchildsemi.com 4 8.5 Max Units ns ns 74VHCT374A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHCT374A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)